CN110035244B - Training method of multichannel low-frequency CMOS serial image data - Google Patents
Training method of multichannel low-frequency CMOS serial image data Download PDFInfo
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Abstract
A training method for multi-channel low-frequency CMOS serial image data relates to a training method for multi-channel low-frequency CMOS serial image datainterOf CMOS serial clock and frequency of fiodelayIs fed into the imaging controller. The imaging controller will have a frequency finterThe CMOS serial clock is sent into the multi-channel CMOS detector, and multi-channel data output by the multi-channel CMOS detector is sent into the imaging controller for serial-parallel conversion. FIG. 2 is a flow chart of the processing of single channel low frequency CMOS serial image data within an imaging controller, serial data at a frequency of 2finterUnder the control of low-frequency clock of/n, the passing reference frequency is fiodelayIs subjected to fine phase delay and then adopts the frequency finterThe DDR clock of/2 carries out serial-parallel conversion based on Iserdes, and finally outputs n bits of parallel data. The invention respectively processes according to the distribution conditions of the five sampling unstable positions, thereby obtaining the data stable sampling time sequence allowance as wide as possible and ensuring the stable and reliable work of the system.
Description
Technical Field
The invention relates to a training method of multichannel low-frequency CMOS serial image data, in particular to a training method of multichannel low-frequency CMOS serial image data based on aerospace application.
Background
Usually, the clock frequency of serial image data output by the CMOS image sensor is higher than the reference clock frequency of IODELAY, and the sampling position of the serial data traverses the whole clock period in the process of carrying out bit correction; however, in some high-orbit low-resolution earth observation applications, the serial image data clock frequency is lower than the reference clock frequency of IODELAY, the adjustable sampling range is lower than the data clock period, and only one data unstable area or even no data unstable area can be detected according to the conventional serial data training method. If a plurality of DCMs are used for changing the phase of the sampling clock, the sampling position can traverse the whole data clock period, but the problems of power consumption and volume increase caused by the use of a plurality of FPGAs due to the limited number of the DCMs in a single FPGA exist. If the optimal data sampling position is determined only according to the sampling information obtained in the narrow sampling range, the sampling area is directly and blindly enlarged, so that the problem of metastable state of sampling is caused.
Disclosure of Invention
The invention provides a training system for multi-channel low-frequency CMOS serial image data, aiming at solving the problems that only one data jump region can be detected or even the data jump region cannot be detected in the existing serial data training method, the optimal data sampling position is determined according to sampling information obtained in a narrow sampling range, and the sampling metastable state occurs due to small sampling margin or blind expansion of the sampling region.
The training system of the multi-channel low-frequency CMOS serial image data comprises an imaging controller, a clock splitter and a low-frequency crystal oscillator; after the clock generated by the low-frequency crystal oscillator passes through the clock splitter, the frequency division generates the frequency finterWith CMOS serial clock and reference frequency of fiodelayAnd fed to an imaging controller which will have a frequency finterThe CMOS serial clock is sent to a multi-channel CMOS detector, and multi-channel data output by the multi-channel CMOS detector is sent to an imaging controller for serial-parallel conversion; the training system performs data training of all channels after being powered on, trains again after the temperature of the multi-channel CMOS detector reaches thermal balance, and finally outputs a photosensitive image;
serial data at frequency 2finterUnder the control of low-frequency clock of/n, passing through reference frequencyIs fiodelayThe Iodelay element performs phase delay and adopts the frequency finterThe DDR clock of/2 carries out serial-parallel conversion based on Iserdes, and finally outputs nbit parallel data;
the implementation manner of the bit correction is specifically as follows:
setting the minimum Delay of the Iodelay element to Delaystart with a value of 0 and the maximum Delay of the Iodelay element to Delay end with a value of tapmaxThe final sampling point is eye middle, the first effective sampling eye is eye start, and the second effective sampling eye is eye end; different processing modes are adopted for the following five cases;
firstly, if the unstable data sampling position is not detected in the delay process, the eye middle at the final sampling point is at the maximum delay value tap of the Iodelay elementmaxThe Delay direction of the Iodelay element is from 0 to the maximum Delay value tapmaxIncreasing progressively; the final sampled eye value is then:
tapeye middle＝tapmax/2
secondly, detecting an unstable Data sampling position Data unstable smaller than the central delay value Data in the delay process, and finally sampling the eye start and the maximum delay value tap of the Iodelay element at the final sampling point eye middlemaxA midpoint of (a); the delay direction Delaydirection of the Iodelay element is from 0 to the maximum delay value tapmaxIncreasing progressively; the final sampled eye value is then:
tapeye middle＝(tapeye start+tapmax)/2
thirdly, detecting a Data unstable position which is larger than the central delay value Data sampling in the delay process, wherein the final sampling point eyemiddle is at the midpoint of the minimum delay value 0 of the first effective sampling eye eyestart and the Iodelay element; the delay direction Delaydirection of the Iodelay element is a value tap from 0 to the first sampling eyeeye startIncrement and then sample the value of the eye tap from the firsteye startDecreasing to 0; the final sampled eye value is then:
tapeye middle＝tapeye start/2
detecting more than one unstable data sampling position datanstable in the delay process, namely, the first effective sampling eye value is smaller than the central delay value of the Iodelay element, and when the unstable data sampling position is not detected at the end of the delay, the final sampling point eye middle is at the first effective sampling eye start and the maximum delay value tap of the Iodelay elementmaxA midpoint of (a); the Delay direction of the Iodelay element is from 0 to the maximum Delay value tapmaxIncreasing progressively; the final sampled eye value is then:
tapeye middle＝(tapeye start+tapmax)/2
detecting more than one unstable data sampling position datanstable in the delay process, namely, the first effective sampling eye value is smaller than the center delay value of the Iodelay element, and the unstable sampling position is detected before the delay is finished, so that the final sampling point eye midle is positioned at the middle point of the first effective sampling eye start and the second unstable sampling position; the delay direction Delaydirection of the Iodelay element is a value tap from 0 to the second valid sampling eyeeye endIncreasing progressively; the final sampled eye value is then:
tapeye middle＝(tapeye start+tapeye end)/2。
the invention has the beneficial effects that:
1. the training of low-frequency serial image data is not required to be carried out based on DCM, and only a single-chip FPGA is used, so that the volume and the power consumption of the system can be greatly reduced;
2. the clock frequency of serial image data does not need to be improved, so that the working frequency of the detector is reduced, the power consumption of the detector can be reduced, the influence on an optical-mechanical part is reduced, the distance between the detector and a post-stage processing circuit can be increased, and the influence on the optical-mechanical part is further reduced;
3. through two times of training in the power-on process, unstable sampling caused by phase change of output data due to temperature change of the CMOS detector can be avoided.
4. By respectively processing various different sampling states, the width of a stable sampling eye can be improved to the maximum extent, and the problem of metastable state of sampling caused by blind expansion of a sampling region is avoided.
Drawings
FIG. 1 is a diagram of a training system for multi-channel low frequency CMOS serial image data according to the present invention;
FIG. 2 is a flow chart of the processing of single channel low frequency CMOS serial image data within the imaging controller according to the present invention;
FIG. 3 is a schematic diagram of a state machine in the training system for multi-channel low-frequency CMOS serial image data according to the present invention;
FIG. 4 is a schematic diagram of a position where data sampling is unstable in a first case of a delay process in a training system for multi-channel low-frequency CMOS serial image data according to the present invention;
FIG. 5 is a schematic diagram of a position where data sampling is unstable in a second case of a delay process in a training system for multi-channel low-frequency CMOS serial image data according to the present invention;
FIG. 6 is a schematic diagram of a position where data sampling is unstable in a third case of a delay process in a training system for multi-channel low-frequency CMOS serial image data according to the present invention;
FIG. 7 is a schematic diagram of a position where data sampling is unstable in a fourth situation during a delay process in a training system for multi-channel low-frequency CMOS serial image data according to the present invention;
FIG. 8 is a schematic diagram of a position where data sampling is unstable in a fifth case of a delay process in the multi-channel low-frequency CMOS serial image data training system according to the present invention;
Detailed Description
First embodiment, a training system for multi-channel low-frequency CMOS serial image data according to the first embodiment will be described with reference to fig. 1 to 8. In the training system of the multi-channel low-frequency CMOS serial image data, a clock generated by a low-frequency crystal oscillator passes through a clock splitter, and the frequency generated by frequency division is finterOf CMOS serial clock and frequency of fiodelayIs fed into the imaging controller. The imaging controller will have a frequency finterThe CMOS serial clock is sent into a multi-channel CMOS detectorAnd sending the multi-channel data output by the channel CMOS detector to an imaging controller for serial-parallel conversion. FIG. 2 is a flow chart of the processing of single channel low frequency CMOS serial image data within an imaging controller, serial data at a frequency of 2finterUnder the control of low-frequency clock of/n, the passing reference frequency is fiodelayIs subjected to fine phase delay and then adopts the frequency finterThe DDR clock of/2 carries out serial-parallel conversion based on Iserdes, and finally outputs nbit parallel data.
The implementation manner of the bit correction is specifically as follows:
setting the minimum Delay of the Iodelay element to Delaystart with a value of 0 and the maximum Delay of the Iodelay element to Delay end with a value of tapmaxThe final sampling point is eye middle, the first effective sampling eye is eye start, and the second effective sampling eye is eye end; the delay directions Delaydirection of the Iodelay elements are one increasing, in the figure the arrow is from left to right, one decreasing, in the figure the arrow is from right to left. Different processing modes are adopted for the following five cases;
firstly, if the unstable data sampling position is not detected in the delay process, the eye middle at the final sampling point is at the maximum delay value tap of the Iodelay elementmaxThe delay direction of the Iodelay element is from 0 to tapmaxIncreasing progressively; then:
tapeye middle＝tapmax/2
secondly, detecting an unstable Data sampling position Data unstable smaller than the central delay value Data in the delay process, and finally sampling point eyemiddle at the first effective sampling eye eyestart and the maximum delay value tap of the Iodelay elementmaxA midpoint of (a); the delay direction of the Iodelay element is from 0 to tapmaxIncreasing progressively; then:
tapeye middle＝(tapeye start+tapmax)/2
thirdly, detecting an unstable Data unstable position greater than the central delay value Data sampling in the delay process, and finally sampling point eyemiddle in the first effective sampling eye eyMidpoint of e-start and Iodelay element minimum delay value 0; the delay direction Delaydirection of the Iodelay element is a value tap from 0 to the first sampling eyeeye startIncrement and then sample the value of the eye tap from the firsteye startDecreasing to 0; then:
tapeye middle＝tapeye start/2
detecting more than one unstable data sampling position datanstable in the delay process, namely, the value of the first effective sampling eye position is smaller than the central delay value of the Iodelay element, and when the unstable sampling position is not detected at the end of the delay, the final sampling point eye middle is at the first effective sampling eye start and the maximum delay value tap of the Iodelay elementmaxA midpoint of (a); the Delay direction of the Iodelay element is from 0 to tapmaxIncreasing progressively; then:
tapeye middle＝(tapeye start+tapmax)/2
detecting more than one unstable data sampling position datanstables in the delay process, namely, the value of the first effective sampling eye position is smaller than the center delay value of the Iodelay element, and the sampling unstable position is detected before the delay is finished, so that the final sampling point eyemidle is at the middle point of the first effective sampling eye eyestart and the second unstable sampling position (the value is equal to eye end); the Delay direction of the Iodelay element is a value tap from 0 to the second valid sampling eye positioneye endIncreasing progressively; then:
tapeye middle＝(tapeye start+tapeye end)/2。
in this embodiment, according to the characteristic that the heating of the CMOS detector in the working process will cause the relative phase of the output serial data to change, in order to ensure the CMOS detector to work stably and reliably, the training steps are designed as follows: after all channel data training is carried out on electrification and the temperature of the detector reaches thermal balance, training is carried out again, and normal work is started at last; before normal work, whether to send out the training command again is determined by detecting the training state. As shown in FIG. 3, the designed training state machine contains three states: a training idle state, a training start state and a training end judgment state. Entering a training starting state from a default training idle state during power-on, and then entering a training ending judging state; when the training completion judgment state detects that all the training channels are completely trained, the training starting state is entered again when the total training times is 1; when the training completion judgment state detects that all the training channels are completely trained and the total training times are more than 1, training in an idle state is carried out; and if a training command is received in the training idle state, the training starting state is also entered.
In this embodiment, the bit correction is implemented as follows:
delaystart is the minimum tap number 0 of the Iodelay element Delay, and Delay start is the maximum tap number tap of the Iodelay element Delaymax。tapmaxThe value of (c) is typically between 32 and 256, depending on the device type. The final sampling point is eye middle, the first valid sampling eye is eye start, and the second valid sampling eye is eye end. Different treatment measures are adopted for the following five cases.
(1) And the unstable data sampling position is not detected in the delay process, and the eye middle of the final sampling point is at the center of the Iodelay maximum delay number. The delay direction of Iodelay is from 0 to tapmaxAnd (4) increasing.
tapeye middle＝tapmax/2
(2) Detecting a position where 1 is less than the unstable sampling of the central delay value data in the delay process, wherein the eye middle of the final sampling point is at the maximum value tap of the maximum delay numbers of the first effective sampling eye start and IodelaymaxThe midpoint of (a). The delay direction of Iodelay is from 0 to tapmaxAnd (4) increasing.
tapeye middle＝(tapeye start+tapmax)/2
(3) During the delay process, 1 unstable sampling position which is larger than the central delay value data is detected, and the eye middle of the final sampling point is in the middle point of the eye start of the first effective sampling and the minimum value 0 of the Iodelay delay. The delay direction of Iodelay is from 0 to tapeye startIncrement, then from tapeye startAnd decremented to 0. The delay direction of Iodelay is from 0 to tapmaxAnd (4) increasing.
tapeye middle＝tapeye start/2
(4) More than 1 unstable data sample position is detected in the delay process (the first effective sampling eye position is smaller than the Iodelay central delay value, and the unstable data sample position is not detected at the end of the delay), and the eye middle of the final sampling point is at the first effective sampling eye start and the Iodelay delay maximum value tapmaxThe midpoint of (a). The delay direction of Iodelay is from 0 to tapmaxAnd (4) increasing.
tapeye middle＝(tapeye start+tapmax)/2
(5) More than 1 unstable data sampling position is detected in the delay process (the value of the first effective sampling eye position is smaller than the Iodelay central delay value, and the unstable sampling position is also detected before the delay is finished), and the final sampling point eye midle is positioned at the middle point of the first effective sampling eye start and the second unstable sampling position (the value is equal to eye end). The delay direction of Iodelay is from 0 to tapeye endAnd (4) increasing.
tapeye middle＝(tapeye start+tapeye end)/2
In this embodiment, the flag indicating the end of bit correction may be any one of the following:
(1) iodelay delay 2 times maximum tap number tapmaxOr if no unstable sample point is detected;
(2) after the first effective sampling eye is detected, detecting a 2 nd unstable sampling point;
(3) after the first effective sampling eye is detected, in the increasing process of the Iodelay delay value, the delay reaches the maximum value tapmax；
(4) After the first effective sampling eye is detected, in the process of decreasing the Iodelay delay value, the delay reaches the minimum value of 0;
in this embodiment, the criterion for determining whether the effective sampling eye is effective is as follows: forward or backward from the current position there is a stable sampling region not less than i in length, i.e., the Iodelay element delays the value tap from the first valid sampling eyeeye startIs decreased to whenIodelay element delay value tap with forward positioneye start-iOr the value tap from the first valid sampling eyeeye startIodelay element delay value tap incremented backwards to current positioneye start+iThe collected serial data is stable.
In the embodiment, the low-frequency crystal oscillator is a product of Wuhan Haisha corporation; the clock splitter adopts CDCM7005 of TI company; the imaging controller adopts Virtex 5 series FPGA; the CMOS image sensor adopts a TDI CMOS image sensor of a long-photosen core company.
Claims (5)
1. The training system of the multi-channel low-frequency CMOS serial image data comprises an imaging controller, a clock splitter and a low-frequency crystal oscillator; after the clock generated by the low-frequency crystal oscillator passes through the clock splitter, the frequency division generates the frequency finterWith CMOS serial clock and reference frequency of fiodelayAnd fed to an imaging controller which will have a frequency finterThe CMOS serial clock is sent to a multi-channel CMOS detector, and multi-channel data output by the multi-channel CMOS detector is sent to an imaging controller for serial-parallel conversion; the method is characterized in that: the training system performs data training of all channels after being powered on, trains again after the temperature of the multi-channel CMOS detector reaches thermal balance, and finally outputs a photosensitive image;
serial data at frequency 2finterUnder the control of low-frequency clock of/n, the passing reference frequency is fiodelayThe Iodelay element performs phase delay and adopts the frequency finterThe DDR clock of/2 carries out serial-parallel conversion based on Iserdes, and finally outputs n-bit parallel data;
the implementation manner of the bit correction is specifically as follows:
setting the minimum Delay of the Iodelay element as Delay start, the minimum Delay start value as 0, the maximum Delay of the Iodelay element as Delay end, the maximum Delay end value as tapmaxThe final sampling point is eye middle, the first effective sampling eye is eye start, and the second effective sampling eye is eye end; different processing modes are adopted for the following five cases;
yiyan teaIf the unstable Data unstable position is not detected in the late process, the eye middle at the final sampling point is at the maximum delay value tap of the Iodelay elementmaxThe Delay direction of the Iodelay element is from 0 to the maximum Delay value tapmaxIncreasing progressively; the final sampled eye value is then:
tapeye middle＝tapmax/2
secondly, detecting a Data sampling unstable position Data unstable smaller than the central delay value Data in the delay process, and finally sampling eye middle at the first effective sampling eye start and the maximum delay value tap of the Iodelay elementmaxA midpoint of (a); the Delay direction of the Iodelay element is from 0 to the maximum Delay value tapmaxIncreasing progressively; the final sampled eye value is then:
tapeye middle＝(tapeye start+tapmax)/2
thirdly, detecting a Data unstable position which is larger than the central delay value Data sampling in the delay process, wherein the eye middle of the final sampling point is at the midpoint of the minimum delay value 0 of the first effective sampling eye start and the Iodelay element; the Delay direction of the Iodelay element is a value tap from 0 to the first sampling eyeeye startIncrement and then sample the value of the eye tap from the firsteye startDecreasing to 0; the final sampled eye value is then:
tapeye middle＝tapeye start/2
detecting more than one Data sampling unstable position Data unstable in the delay process, namely, the first effective sampling eye value is smaller than the center delay value of the Iodelay element, and when the sampling unstable position is not detected at the end of the delay, the final sampling point eye middle is at the first effective sampling eye start and the maximum delay value tap of the Iodelay elementmaxA midpoint of (a); the Delay direction of the Iodelay element is from 0 to the maximum Delay value tapmaxIncreasing progressively; the final sampled eye value is then:
tapeye middle＝(tapeye start+tapmax)/2
fifth, more than one is detected in the delay processData sampling unstable position Data unstable, namely, the first effective sampling eye value is smaller than the center delay value of the Iodelay element, and the sampling unstable position is detected before the delay is finished, so that the final sampling point eye midle is at the middle point of the first effective sampling eye start and the sampling unstable position appearing for the second time; the Delay direction of the Iodelay element is the value tap from 0 to the second valid sampling eyeeye endIncreasing progressively; the final sampled eye value is then:
tapeye middle＝(tapeye start+tapeye end)/2。
2. the training system for multichannel low frequency CMOS serial image data according to claim 1, characterized by: in the delay process, when any one of the following four conditions occurs, the bit correction is finished;
delay of Iodelay element by 2 times of tapmaxOr if no unstable sample point is detected;
secondly, after the first effective sampling eye is detected, detecting a 2 nd unstable sampling point;
thirdly, after the first effective sampling eye is detected, in the process of increasing the delay value of the Iodelay element, the delay reaches the maximum delay value tapmax；
And thirdly, after the first effective sampling eye is detected, in the process of decreasing the delay value of the Iodelay element, the delay reaches the minimum value of 0.
3. The training system for multichannel low frequency CMOS serial image data according to claim 1, characterized by: in the delay process, the judgment standard for judging whether the effective sampling eye is effective is as follows:
forward or backward from the current position there is a stable sampling region not less than i in length, i.e., the Iodelay element delays the value tap from the first valid sampling eyeeye startIodelay element delay value tap decremented to the forward of current positioneye start-iOr the value tap from the first valid sampling eyeeye startIodelay element delay value tap incremented backwards to current positioneye start+iCollected serialIf the data are stable, the data are effective sampling eyes;
i is greater than 6 and less than the maximum delay value tapmaxIs a natural number of (1).
4. The training system for multichannel low frequency CMOS serial image data according to claim 1, characterized by: the tapmaxIs typically between 32 and 256 depending on the device type.
5. The training system for multichannel low frequency CMOS serial image data according to claim 1, characterized by: the training state machine contains three states: training idle state, training starting state and training ending judging state; when the system is powered on, the system enters a training starting state from a default training idle state and then enters a training ending judgment state; when the training completion judgment state detects that all the training channels are completely trained, the training starting state is entered again when the total training times is 1; when the training completion judgment state detects that all the training channels are completely trained and the total training times are more than 1, training in an idle state is carried out; and if a training command is received in the training idle state, the training starting state is also entered.
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| CN112118441B (en) * | 2020-09-22 | 2021-06-15 | 中国科学院长春光学精密机械与物理研究所 | Bit correction improved serial CMOS image data training method |
| CN113141476B (en) * | 2021-04-21 | 2022-05-17 | 中国科学院长春光学精密机械与物理研究所 | Training method for high-frequency and low-frequency serial image data |
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