CN110034179A - Groove metal-oxide-semiconductor element - Google Patents
Groove metal-oxide-semiconductor element Download PDFInfo
- Publication number
- CN110034179A CN110034179A CN201810212670.8A CN201810212670A CN110034179A CN 110034179 A CN110034179 A CN 110034179A CN 201810212670 A CN201810212670 A CN 201810212670A CN 110034179 A CN110034179 A CN 110034179A
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- Prior art keywords
- electrode
- oxide
- groove
- semiconductor element
- upper electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000036632 reaction speed Effects 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of groove metal-oxide-semiconductor element, including substrate and multiple trenched electrode structures.Substrate has multiple grooves, and groove extends along a first direction and arranges along second direction, and first direction intersects with second direction.Trenched electrode structures are set in groove.Each trenched electrode structures include lower electrode, upper electrode and the first dielectric layer.Lower electrode is set in groove.Upper electrode is set in groove and is located on lower electrode.Upper electrode has the bottom surface for the electrode that faces toward.Upper electrode has the multiple recessed portions arranged along a first direction on bottom surface.First dielectric layer is set between upper electrode and lower electrode.Above-mentioned groove metal-oxide-semiconductor element can reduce the parasitic capacitance between upper electrode and adjacent doped region, and have faster reaction speed.
Description
Technical field
The present invention relates to a kind of semiconductor element more particularly to a kind of groove metal-oxide-semiconductor elements.
Background technique
With the development and product demand of semiconductor industry, the groove metal-oxide-semiconductor element with dhield grid is extensive
It applies in power switch (power switch) element on ground.Due to such shielded gate trench metal-oxide half field effect transistor
(shielded gate trench MOSFET) element has many excellent performances, compares traditional MOS transistor and opens
Structure is closed, shielded gate trench metal-oxide half field effect transistor element has lower transistor gate drain capacitance, lesser electric conduction
Resistance, and higher breakdown voltage (breakdown voltage) is provided.
In general, traditional shielded gate trench metal-oxide half field effect transistor element have in the trench lower electrode with it is upper
Portion's electrode, and lower electrode is as dhield grid.However, parasitism can be generated between the upper electrode of groove and adjacent doped region
Capacitor, and reduce the reaction speed of element.
Summary of the invention
The present invention provides a kind of groove metal-oxide-semiconductor element, can reduce between upper electrode and adjacent doped region
Parasitic capacitance, and there is faster reaction speed.
The present invention proposes a kind of groove metal-oxide-semiconductor element, including substrate and multiple trenched electrode structures.Substrate has
Multiple grooves, groove extends along a first direction and arranges along second direction, and first direction intersects with second direction.Groove
Electrode structure is set in groove.Each trenched electrode structures include lower electrode, upper electrode and the first dielectric layer.Lower part electricity
Pole is set in groove.Upper electrode is set in groove and is located on lower electrode.Upper electrode has the electrode that faces toward
Bottom surface.Upper electrode has the multiple recessed portions arranged along a first direction on bottom surface.First dielectric layer is set to top
Between electrode and lower electrode.
According to described in one embodiment of the invention, in above-mentioned groove metal-oxide-semiconductor element, the shape of bottom surface is wave
Shape.
According to described in one embodiment of the invention, in above-mentioned groove metal-oxide-semiconductor element, lower electrode can have face
To the first top surface of upper electrode.Lower electrode has arrange along a first direction multiple first to protrude on the first top surface
Portion.Recessed portion corresponds to the first protruding portion and is configured.
According to described in one embodiment of the invention, in above-mentioned groove metal-oxide-semiconductor element, the first dielectric layer has face
To the second top surface of upper electrode.First dielectric layer has arrange along a first direction multiple second to protrude on the second top surface
Portion.Recessed portion corresponds to the second protruding portion and is configured.
According to described in one embodiment of the invention, in above-mentioned groove metal-oxide-semiconductor element, trenched electrode structures are located at
In active region.
According to described in one embodiment of the invention, in above-mentioned groove metal-oxide-semiconductor element, the first dielectric layer also extends
To between substrate and upper electrode.
According to described in one embodiment of the invention, in above-mentioned groove metal-oxide-semiconductor element, each trenched electrode structures
It further include the second dielectric layer.Second dielectric layer is set between substrate and lower electrode.
It further include doped region in above-mentioned groove metal-oxide-semiconductor element according to described in one embodiment of the invention.Doping
Area is in the substrate between two neighboring trenched electrode structures.
Based on above-mentioned, in groove metal-oxide-semiconductor element proposed by the invention, since upper electrode has on bottom surface
There are the multiple recessed portions arranged along a first direction, so the sectional area of upper electrode in a first direction can be reduced, therefore can
The parasitic capacitance between upper electrode and adjacent doped region is reduced, and it is faster anti-that groove metal-oxide-semiconductor element is had
Answer speed.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the perspective view of the groove metal-oxide-semiconductor element of one embodiment of the invention；
Fig. 2 is the perspective view of the groove metal-oxide-semiconductor element of another embodiment of the present invention.
Drawing reference numeral explanation:
10,20: groove metal-oxide-semiconductor element
100: substrate
102: groove
104,204: lower electrode
104a, 208a: protruding portion
106: upper electrode
106a: recessed portion
108,110,208: dielectric layer
AA: active region
BR: matrix area
BS: bottom surface
D1: first direction
D2: second direction
DR: doped region
S1, S2, S3: top surface
TS1, TS2: trenched electrode structures
Specific embodiment
Fig. 1 is the perspective view of the groove metal-oxide-semiconductor element of one embodiment of the invention.
Fig. 1 is please referred to, groove metal-oxide-semiconductor element 10 includes substrate 100 and multiple trenched electrode structures TS1, and is more wrapped
Include doped region DR.Substrate 100 has multiple grooves 102, and D1 extends and arranges along second direction D2 groove 102 along a first direction
Column, and first direction D1 intersects with second direction D2.The material of substrate 100 can be semiconductor material.For example, substrate 100
It may include silicon substrate, and further include the epitaxy silicon layer being set on silicon substrate.In this embodiment, two trench electrodes are only shown
It is illustrated for structure TS1, but the present invention is not limited thereto.
Trenched electrode structures TS1 is set in groove 102, and is located in active region AA.Each trenched electrode structures TS1 packet
Lower electrode 104, upper electrode 106 and dielectric layer 108 are included, and further includes dielectric layer 110.
Lower electrode 104 is set in groove 102.Lower electrode 104 has the top surface S1 towards upper electrode 106.Under
Portion's electrode 104 has the multiple protruding portion 104a of D1 arrangement along a first direction on the S1 of top surface.The material of lower electrode 104 is
The conductors material such as DOPOS doped polycrystalline silicon or metal (e.g., tungsten, copper or aluminium).
Upper electrode 106 is set in groove 102 and is located on lower electrode 104.Upper electrode 106, which has, to face toward
The bottom surface BS of electrode 104.Upper electrode 106 has multiple recessed portion 106a of D1 arrangement along a first direction on the BS of bottom surface,
The sectional area of upper electrode 106 in the first direction dl is reduced whereby.The shape of bottom surface BS is wavy.In addition, upper electrode
The protruding portion 104a that 106 recessed portion 106a can correspond to lower electrode 104 is configured.The material of upper electrode 106 is to mix
The conductors material such as miscellaneous polysilicon or metal (e.g., tungsten, copper or aluminium).
Dielectric layer 108 is set between upper electrode 106 and lower electrode 104, may make upper electrode 106 under whereby
Portion's electrode 104 is electrically insulated from.In this embodiment, dielectric layer 108 is conformally arranged at the top surface S1 of lower electrode 104
On.In addition, dielectric layer 108 further extends between substrate 100 and upper electrode 106, substrate 100 and upper electrode may make whereby
106 are electrically insulated from.The material of dielectric layer 108 can be the dielectric materials such as silicon oxide or silicon nitride.
Dielectric layer 110 is set between substrate 100 and lower electrode 104, makes substrate 100 and lower electrode 104 whereby
It is electrically insulated from.The material of dielectric layer 110 is the dielectric materials such as silicon oxide or silicon nitride.It can be seen from the above, this embodiment
Lower electrode 104, upper electrode 106 are electrically insulated from substrate 100 by dielectric layer 108 and dielectric layer 110.
Doped region DR is in the substrate 100 between two neighboring trenched electrode structures TS1, and the base below doped region DR
Matrix area (body region) BR is configured in bottom 100.In this embodiment, doped region DR is matrix area with N-type heavy doping
BR is to be illustrated so that p-type is adulterated as an example, but the present invention is not limited thereto.Skilled artisan can be according to production
Product design requirement adjusts the dopant profile and doping concentration of doped region DR and matrix area BR.
Based on the above embodiment it is found that in groove metal-oxide-semiconductor element 10, since upper electrode 106 is on the BS of bottom surface
Multiple recessed portion 106a with the arrangement of D1 along a first direction whereby can reduce upper electrode 106 in the first direction dl
Sectional area to reduce the parasitic capacitance between upper electrode 106 and adjacent doped region DR, and makes groove metal-oxide-semiconductor (MOS) first
Part 10 has faster reaction speed.In addition, groove metal-oxide-semiconductor element 10 by adjusting recessed portion 106a in a first direction
Sectional area on D1 adjusts the parasitic capacitance between upper electrode 106 and adjacent doped region DR.
Fig. 2 is the perspective view of the groove metal-oxide-semiconductor element of another embodiment of the present invention.
Please refer to Fig. 1 and Fig. 2, groove metal-oxide-semiconductor element 20 (Fig. 2) and groove metal-oxide-semiconductor element 10 (Fig. 1's)
Difference is as follows.In the trenched electrode structures TS2 of groove metal-oxide-semiconductor element 20, the top surface S2 of lower electrode 204 is flat
Surface.Dielectric layer 208 has the top surface S3 towards upper electrode 106.Dielectric layer 208 has along a first direction on the S3 of top surface
The multiple protruding portion 208a of D1 arrangement.In addition, the recessed portion 106a of upper electrode 106 corresponds to the protruding portion of dielectric layer 208
208a is configured.In addition, groove metal-oxide-semiconductor element 20 is with identical component in groove metal-oxide-semiconductor element 10 with phase
Same symbol indicates, and is at large illustrated in above-described embodiment, is not repeated to illustrate in this.
Based on the above embodiment it is found that groove metal-oxide-semiconductor element 20 is by being located on the bottom surface BS of upper electrode 106
Multiple recessed portion 106a, to reduce the sectional area of upper electrode 106 in the first direction dl, with reduce upper electrode 106 with
Parasitic capacitance between adjacent doped region DR, and there is faster reaction speed.In addition, groove metal-oxide-semiconductor element 20 can
It is adjusted between upper electrode 106 and adjacent doped region DR by adjusting the sectional area of recessed portion 106a in the first direction dl
Parasitic capacitance.
In conclusion multiple on bottom surface of the groove metal-oxide-semiconductor element of above-described embodiment by being located at upper electrode
Recessed portion to reduce the parasitic capacitance between upper electrode and adjacent doped region, and has faster reaction speed.In addition,
Groove metal-oxide-semiconductor element can be mixed by adjusting the sectional area of the recessed portion of upper electrode to adjust upper electrode with adjacent
Parasitic capacitance between miscellaneous area.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention
Subject to range ought be defined depending on claim.
Claims (8)
1. a kind of groove metal-oxide-semiconductor element characterized by comprising
Substrate, wherein the substrate has multiple grooves, the multiple groove extends along a first direction and along second direction
Arrangement, and the first direction intersects with the second direction；And
Multiple trenched electrode structures are set in the multiple groove, and each trenched electrode structures include:
Lower electrode is set in the groove；
Upper electrode is set in the groove and is located on the lower electrode, and has the bottom towards the lower electrode
Face, wherein the upper electrode has the multiple recessed portions arranged along the first direction on the bottom surface；And
First dielectric layer is set between the upper electrode and the lower electrode.
2. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that the shape of the bottom surface includes wave
Shape.
3. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that the lower electrode has towards institute
The first top surface of upper electrode is stated, is arranged wherein the lower electrode has on first top surface along the first direction
Multiple first protruding portions, and the multiple recessed portion correspond to the multiple first protruding portion be configured.
4. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that first dielectric layer have towards
Second top surface of the upper electrode, wherein first dielectric layer has on second top surface along the first direction
Multiple second protruding portions of arrangement, and the multiple recessed portion corresponds to the multiple second protruding portion and is configured.
5. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that the multiple trenched electrode structures position
In active region.
6. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that first dielectric layer also extends to
Between the substrate and the upper electrode.
7. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that each trenched electrode structures further include
Second dielectric layer is set between the substrate and the lower electrode.
8. groove metal-oxide-semiconductor element according to claim 1, which is characterized in that further include doped region, be located at adjacent
In the substrate between two trenched electrode structures.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107101144A TW201931600A (en) | 2018-01-12 | 2018-01-12 | Trench metal oxide semiconductor device |
| TW107101144 | 2018-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110034179A true CN110034179A (en) | 2019-07-19 |
Family
ID=67234565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810212670.8A Pending CN110034179A (en) | 2018-01-12 | 2018-03-15 | Groove metal-oxide-semiconductor element |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110034179A (en) |
| TW (1) | TW201931600A (en) |
-
2018
- 2018-01-12 TW TW107101144A patent/TW201931600A/en unknown
- 2018-03-15 CN CN201810212670.8A patent/CN110034179A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| TW201931600A (en) | 2019-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20190726 Address after: Taiwan Hsinchu County China jhubei City, Taiwan 5 yuan a Street No. 9 Building 1 Applicant after: Upi Semiconductor Corp. Address before: 6, No. 5, Taiyuan street, No. 5, Taiyuan street, bamboo North City, county Applicant before: UBIQ Semiconductor Corp. |
|
| TA01 | Transfer of patent application right | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190719 |
|
| WD01 | Invention patent application deemed withdrawn after publication |