CN110034025B - Bump structure and preparation method thereof - Google Patents
Bump structure and preparation method thereof Download PDFInfo
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- CN110034025B CN110034025B CN201910277516.3A CN201910277516A CN110034025B CN 110034025 B CN110034025 B CN 110034025B CN 201910277516 A CN201910277516 A CN 201910277516A CN 110034025 B CN110034025 B CN 110034025B
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000001465 metallisation Methods 0.000 claims abstract description 97
- 238000005530 etching Methods 0.000 claims abstract description 80
- 230000002265 prevention Effects 0.000 claims abstract description 67
- 238000002161 passivation Methods 0.000 claims abstract description 66
- 239000010410 layer Substances 0.000 claims description 286
- 230000002093 peripheral effect Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 239000003292 glue Substances 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 238000007639 printing Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 12
- 239000010949 copper Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000011161 development Methods 0.000 description 4
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- 238000004806 packaging method and process Methods 0.000 description 4
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- 239000000126 substance Substances 0.000 description 3
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
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- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a bump structure and a preparation method thereof. The preparation method of the bump structure comprises the following steps: forming a first etching prevention layer on the under bump metallization layer; forming a plurality of first openings in the first etch-resistant layer; etching the under bump metallization layer below the first opening to form an under bump metallization pattern layer; the under bump metallization pattern layer exposes a first area without a passivation layer above the bonding pad and covers a second area without the passivation layer above the bonding pad. The invention removes the under bump metallization layer above the partial area without the passivation layer above the bonding pad, prevents most areas of the upper surface of the bump from being bonded with the substrate due to the existence of gas, avoids the phenomenon of poor contact, improves the reliability of the product, and improves the roughness and the flatness of the bump.
Description
Technical Field
The present invention relates to semiconductor package structures, and more particularly, to a bump structure and a method for fabricating the same.
Background
With the rapid development of the electronic industry, electronic products gradually enter into the direction of multi-functional and high-performance research and development. In order to meet the requirements of high Integration and Miniaturization of semiconductor devices, the requirements of semiconductor package structures are increasing.
In order to further improve various characteristics of the package structure, the related art is not diligent in developing. How to provide a package structure with better characteristics belongs to one of the important research and development issues, and becomes the object of the related art that needs to be improved. In the existing packaging structure, the surface of the lug, which is far away from the bonding pad, has the condition of high periphery and low middle, and during subsequent packaging, the periphery is firstly bonded together, so that the gas in the middle cannot be discharged, and the reliability of the product is reduced.
Disclosure of Invention
The invention mainly aims to provide a bump structure and a preparation method thereof, which can enable the bump structure to be better bonded with a substrate and increase the reliability of a product.
In order to achieve the purpose, the invention adopts a technical scheme that: a method for preparing a bump structure is provided, which comprises:
forming a first etching prevention layer on the under bump metallization layer;
forming a plurality of first openings in the first etch-resistant layer;
etching the under bump metallization layer below the first opening to form an under bump metallization pattern layer;
the under bump metallization pattern layer covers a first area without a passivation layer above the bonding pad and exposes a second area without the passivation layer above the bonding pad.
Wherein the step of forming a plurality of first openings in the first etch-resistant layer comprises:
the first etching prevention layer is a photoresist layer, and the first etching prevention layer is exposed and developed to form a first opening on the first etching prevention layer;
or the first anti-etching layer is an imprinting glue layer and is imprinted so as to form a first opening on the first anti-etching layer.
Wherein the forming a solder layer on the under bump metallization pattern layer to obtain a bump covering the under bump metallization pattern layer disposed above the first region and the second region comprises:
removing the first etching prevention layer;
forming a solder layer on the under bump metallization pattern layer;
forming a second etching prevention layer on the solder layer;
forming a plurality of second openings on the second etching prevention layer to form a second etching prevention pattern layer;
etching the solder layer below the second opening to obtain a plurality of bumps;
and removing the second etching prevention layer.
Wherein the forming a solder layer on the under bump metallization pattern layer to obtain a bump covering the under bump metallization pattern layer disposed above the first region and the second region comprises:
removing the first etching prevention layer;
forming a second etching prevention layer on the under-bump metallization pattern layer;
forming a plurality of second openings on the second etching prevention layer;
filling solder to the second opening by electroplating or stencil printing to form a bump;
and removing the second etching prevention layer.
The second opening exposes the under bump metallization pattern layer arranged in the area without the passivation layer above the bonding pad.
And the second etching-proof pattern layer covers the under bump metallization pattern layer arranged in the area without the passivation layer above the bonding pad.
Wherein the step of forming a plurality of second openings on the second etching prevention layer comprises: the second etching prevention layer is an imprinting adhesive layer and is imprinted so as to form a second opening on the second etching prevention layer; or
The forming of the plurality of second openings on the second etching prevention layer includes: the second etching-proof layer is a photoresist layer, and the second etching-proof layer is exposed and developed to form a second opening on the second etching-proof layer.
In order to achieve the purpose, the invention adopts a technical scheme that: providing a bump structure, the structure comprising;
a wafer;
a pad disposed on an active surface of a wafer;
a passivation layer covering the active surface of the wafer and exposing at least a portion of the bonding pad;
the under bump metallization pattern layer covers a first region, which is not provided with the passivation layer, above the pad and exposes a second region, which is not provided with the passivation layer, above the pad;
and the bump covers the under bump metallization pattern layer arranged above the second area and the first area.
The area without the passivation layer above the bonding pad comprises a middle area and a peripheral area surrounding the middle area, the second area is the peripheral area, and the first area is the middle area.
The under bump metallization pattern layer also exposes the area of the passivation layer close to the bonding pad;
the bump covers the area of the passivation layer close to the pad.
Above scheme, the under bump metallization layer of the partial region top that does not be equipped with the passivation layer above the pad is got rid of, can let the lug upper surface that prepares next on under bump metallization pattern layer form one or more low valleys, from this in lug structure packaging process, the gas of middle zone can run toward this low valley department, prevent to lead to most regions of lug upper surface unable and substrate bonding because of the existence of gas, thereby avoid the existence of bad contact's phenomenon, improve product reliability, and improve the roughness and the roughness of lug.
Drawings
FIG. 1 is a schematic structural diagram of a bump structure according to an embodiment of the present invention;
FIG. 2 is an enlarged schematic view of a bump structure at A according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a region of a bonding pad without a passivation layer according to an embodiment of a bump structure of the invention;
FIG. 4 is a schematic flow chart illustrating a method for fabricating a bump structure according to an embodiment of the present invention;
FIG. 5 is a schematic flow chart illustrating a method for fabricating a bump structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a region without a passivation layer on a bonding pad according to an embodiment of the method for manufacturing a bump structure of the invention;
FIG. 7 is a schematic flow chart illustrating the opening of the first anti-etching layer in one embodiment of the method for fabricating a bump structure according to the invention;
FIG. 8 is a schematic flow chart illustrating a method for fabricating a bump structure according to another embodiment of the present invention;
FIG. 9 is a schematic flow chart illustrating a method for fabricating a bump structure according to another embodiment of the present invention;
FIG. 10 is a schematic flow chart illustrating a method for fabricating a bump structure according to another embodiment of the present invention;
fig. 11 is a schematic flow chart illustrating a method for fabricating a bump structure according to another embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of a bump structure according to an embodiment of the present invention; fig. 2 is an enlarged schematic view of a structure at a in an embodiment of the bump structure of the invention. The bump structure comprises a wafer 201, a pad 202, a passivation layer 203, an under bump metallization pattern layer 210 and a bump 216, the pad 202 being disposed on an active surface of the wafer 201; a passivation layer 203 covering the active surface of wafer 201 but exposing at least a portion of pad 202; the under bump metallization pattern layer 210 covers a first region 218 over the pad 202 where the passivation layer 203 is not disposed and exposes a second region 219 over the pad 202 where the passivation layer 203 is not disposed; the bump 216 covers the under bump metallization pattern layer 210 disposed over the first region 218 and the second region 219.
One or more pads 202 may be disposed on the active surface of the wafer 201, and the shape of the pads 202 may be various, and may be circular, rectangular, or oval, or any other shape. The passivation layer 203 may expose all or part of the pad 202. A portion of the region 206 over the pad 202 where the passivation layer 203 is not disposed is provided with an under bump metallization pattern layer 210, and the portion is named as a "first region 218", which is named for convenience only; but another portion is not provided with the under bump metallization pattern layer 210 and the other portion is named as "second region 219", which is just for convenience. The second region 219 is not provided with the under bump metallization pattern layer 210: may be due to the removal of the under bump metallization pattern layer 210 previously provided in the second region 219; or alternatively, when the under bump metallization pattern layer 210 is formed on the wafer structure, the under bump metallization pattern layer 210 is not formed in the second region 219. When the under bump metallization pattern layer 210 is formed on the wafer structure, the method for forming the under bump metallization pattern layer 210 in the second region 219 may be: when the under bump metallization pattern 210 is formed on the wafer structure, a later removable patterned layer having a plurality of openings is present on the wafer structure, a metal material is deposited in the plurality of openings of the patterned layer to form the under bump metallization pattern 210, and the patterned layer covers the second region 219 and exposes the first region 218.
When the bump 216 is formed on the combined structure of the wafer 201, the pad 202, the passivation layer 203 and the under bump metallization pattern layer 210, the surface of the bump 216 away from the pad 202 (hereinafter "the surface of the bump 216 away from the pad 202" is named "the upper surface of the bump 216", which is only used for convenience of expression "the surface of the bump 216 away from the pad 202", and no orientation effect is actually specified; that is, "the surface of the bump 216 away from the pad 202", may be the upper surface of the bump 216, or the lower surface of the bump 216, or the surface of the bump 216 in other orientations) has a flatness that is equal to the flatness of the surface of the bump 216 close to the pad 202 (hereinafter "the surface of the bump 216 close to the pad 202" is named "the lower surface of the bump 216", which is only used for convenience of expression "the bump 216 close to the surface of the pad 202", and no orientation effect is actually specified; that is, which may be the upper surface of the bump 216, or the lower surface of the bump 216, or other surface orientation of the bump 216), that is, if the lower surface of the bump 216 has a high level, the upper surface of the bump 216 will have a corresponding high level, and the lower area of the lower surface of the bump 216 will correspond to the lower area of the upper surface of the bump 216, and the upper area of the lower surface of the bump 216 will correspond to the upper area of the upper surface of the bump 216, and the high level will correspond to the low level.
The pads 202 exposed by the under bump metallization pattern layer 210 may be corrugated or have other patterns. Wherein the pads 202 with the wavy shape exposed by the under bump metallization pattern layer 210 can be regarded as a combination of one or more ring structures. The ring structure may be similar or identical to the frame structure of the pad 202, or may be dissimilar from the frame structure of the pad 202. The ring structure may be circular, rectangular, triangular, elliptical or strip. The ring width of the ring structure may be in the range of 0.5 μm to 3 μm, and specifically, the ring width of the ring structure may be 0.5 μm, 1 μm, 2 μm … …. the plurality of ring structures may be arranged uniformly, that is, in a regular manner, for example, the intervals between the ring structures may be the same. In other embodiments, the plurality of ring structures may also be arranged non-uniformly, i.e., in a manner that is not regular. The region 206 over the pad 202 where the passivation layer 203 is not disposed includes a middle region 207 and a peripheral region 208 surrounding the middle region 207. The width of the peripheral region 208 may be in the range of 0.5 μm to 5 μm, i.e., 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc. in the above range.
In one of the application scenarios, the first region 218 may be the middle region 207 and the second region 219 may be the peripheral region 208. That is, the middle region 207 is covered by the under bump metallization pattern layer 210, and the entire peripheral region 208 is exposed by the under bump metallization pattern layer 210. Thus, during the bump structure package, the trapped gas will go to the valley 217 corresponding to the peripheral region 208, so that the upper surface of the bump 216 corresponding to the middle region 207 will be better bonded to the substrate without being affected by the trapped gas, and the flatness of the upper surface of the bump 216, i.e., the roughness of the upper surface of the bump 216, can be improved.
In another application scenario, the first region 218 may be the middle region 207 and a portion of the peripheral region 208, and the second region 219 may be another portion of the peripheral region 208. That is, the middle region 207 and a portion of the peripheral region 208 are covered by the under bump metallization pattern layer 210, and another portion of the peripheral region 208 is exposed by the under bump metallization pattern layer 210.
In another application scenario, as shown in fig. 3, the first region 218 may be a portion of the middle region 207 and a portion of the peripheral region 208, and the second region 219 may be another portion of the middle region 207 and another portion of the peripheral region 208. That is, a portion of the middle region 207 and a portion of the peripheral region 208 are covered by the under bump metallization pattern layer 210, and another portion of the middle region 207 and another portion of the peripheral region 208 are exposed by the under bump metallization pattern layer 210.
In another application scenario, the first region 218 may be a portion of the middle region 207 and the peripheral region 208, and the second region 219 may be another portion of the middle region 207. That is, a portion of the middle region 207 and the peripheral region 208 is covered by the under bump metallization pattern layer 210, and another portion of the middle region 207 is exposed by the under bump metallization pattern layer 210.
Further, the under bump metallization pattern layer 210 also exposes a region of the passivation layer 203 near the pad 202;
the bump 216 covers a region of the passivation layer 203 near the pad 202.
Wherein the under bump metallization pattern layer 210 on the passivation layer 203 near the pad 202 may be removed or the under bump metallization pattern layer 210 may not have been previously formed on the passivation layer 203 near the pad 202. In other embodiments, the under bump metallization pattern layer 210 may expose the entire passivation layer 203. Thus, when the bump 216 is formed thereon, the height of the area corresponding to the upper surface of the bump 216 disposed near the passivation layer 203 on the pad 202 is reduced, so that when packaging with a substrate, the trapped gas is much less than when the area of the passivation layer 203 near the pad 202 is not exposed by the under-bump metallization pattern layer 210, and thus the under-bump metallization pattern layer 210 only needs to expose less pad area to prevent poor contact due to the presence of the trapped gas, thereby improving product reliability and further improving the flatness and roughness of the upper surface of the bump 216.
Referring to fig. 4 and 5, an embodiment of the method for fabricating the bump structure of the invention includes:
s101: a first etch-resistant layer 205 is formed over the under bump metallization layer 204.
Wherein, before forming the first etch-resistant layer 205 on the under bump metallization layer 204: providing a wafer structure, wherein the wafer structure comprises a wafer 201, a bonding pad 202 and a passivation layer 203, the bonding pad 202 is arranged on an active surface of the wafer 201, the passivation layer 203 covers the active surface of the wafer 201 but exposes at least part of the bonding pad 202, namely, the passivation layer 203 can cover part of the bonding pad 202 or can expose all the bonding pads 202; an under bump metallization layer 204 is then formed on the wafer structure to form a structure as shown in fig. a, wherein the material of the under bump metallization layer 204 may be titanium (Ti), chromium-copper (Cr-Cu), copper (Cu), aluminum (Al), nickel-vanadium (Ni-V), or a combination thereof, and the under bump metallization layer 204 may be formed on the wafer structure by metal sputtering deposition. A first etch-resistant layer 205 is then applied uniformly over the under bump metallization layer 204 to form the structure shown in fig. (b).
The area 206 without the passivation layer 203 above the pad 202 is shown in fig. 6, and the area 206 without the passivation layer 203 above the pad 202 includes a middle area 207 and a peripheral area 208 surrounding the middle area 207, where the dotted line in fig. 6 has no practical meaning, and is only used to illustrate the division of the middle area and the peripheral area, where the middle area is inside the dotted line, and the peripheral area is outside the dotted line. It is understood that one or more bonding pads 202 are disposed on wafer 201, and bonding pads 202 disposed on wafer 201 may be in various shapes such as circular, rectangular, oval, etc. It should be understood that the middle region 207 and the peripheral region 208 surrounding the middle region 207 may also be various shapes such as a circle, a rectangle, an ellipse, etc., and are not limited to the shapes shown in fig. 6.
S102: a plurality of first openings 209 are formed in the first etch-resistant layer 205.
Here, the plurality of first openings 209 may be formed in the first etching prevention layer 205 in different manners according to the property of the first etching prevention layer 205, so as to form the structure shown in fig. (c). Wherein a portion of the first opening 209 may correspond to a portion of the pad 202 where the passivation layer 203 is not disposed. Further, one or more first openings 209 are disposed corresponding to a portion of the pad 202 where the passivation layer 203 is not disposed: wherein the one or more first openings 209 may all be disposed corresponding to the peripheral region 208; or may be disposed to correspond entirely to the middle region 207; or a part is disposed corresponding to the peripheral region 208 and another part is disposed corresponding to the intermediate region 207. Further, the plurality of first openings 209 may be disposed in a corrugated form over the region 206 over the pad 202 where the passivation layer 203 is not disposed. The width of the first opening 209 may be in a range of 0.5 μm to 3 μm, and specifically, the width of the first opening 209 may be 0.5 μm, 1 μm, 2 μm, or the like.
S103: the under bump metallization layer 204 under the first opening 209 is etched to form an under bump metallization pattern layer 210.
Wherein the under bump metallization layer 204 under the first opening 209 may be etched away by wet etching, which may be chemical etching, and after the operation is completed, the under bump metallization pattern layer 210 and the structure shown in fig. (d) are formed. The under bump metallization pattern layer 210 covers a first region 218 over the pad 202 where the passivation layer 203 is not disposed and exposes a second region 219 over the pad 202 where the passivation layer 203 is not disposed. The width of the peripheral region 208 may be in a range of 0.5 μm to 3 μm, that is, the distance between the middle region 207 and the passivation layer 203 is in a range of 0.5 μm to 3 μm. Wherein the second region 219 may be at least part of the peripheral region 208 and the first region 218 may be the middle region 207 and the remaining middle region 207. In other embodiments, the second region 219 may be at least a portion of the intermediate region 207 and the first region 218 may be the entire peripheral region 208 and the remaining intermediate region 207.
In the present embodiment, the under bump metallization layer 204 above the partial area of the pad 202 without the passivation layer 203 is etched away, so that one or more valleys 217 are formed above the bump 216 prepared on the under bump metallization pattern layer 210, and thus, during the bump structure packaging process, the gas in the middle area 207 will go to the valley 217, thereby preventing the middle area 207 of the bump 216 from being unable to be bonded to the substrate due to the presence of the gas, and avoiding the occurrence of poor contact.
Optionally, as shown in fig. 7, fig. 7 is a schematic flow chart of the positive photoresist opening. The first etching prevention layer 205 is a photoresist layer, and the step S102 may include exposing and developing the first etching prevention layer 205 to form a first opening 209 on the first etching prevention layer 205.
The photoresist layer is a medium for transferring patterns by utilizing a material photochemical reaction and is divided into a positive photoresist layer and a negative photoresist layer. After the positive photoresist layer is exposed to ultraviolet light, the exposed area is subjected to photolysis or degradation reaction, so that the property is changed and is preferentially dissolved in a positive developing solution, and the unexposed part is reserved to form a positive pattern. Negative-working photoresists are the very opposite in nature in that the unexposed portions are dissolved in a negative-working developer.
Generally, before removing the photoresist, the photoresist layer needs to be covered by a mask plate 211 or a half mask plate with a certain shape, then exposed under ultraviolet light, and through exposure, the dissolving speed of the part of the photoresist layer irradiated by the ultraviolet light in a developing solution is different from that of the unexposed part of the photoresist, so as to achieve the process of transferring the pattern on the mask plate.
And then development is performed. Among the developing solutions, the exposed portion of the (positive) photoresist can be quickly dissolved in the developing solution (the negative photoresist is just opposite to the unexposed portion, and the unexposed portion is dissolved in the developing solution), and the unexposed portion of the photoresist is slowly dissolved, so that the pattern on the mask plate 211 can be developed by controlling the developing time.
In other embodiments, further, the first etching prevention layer 205 is an imprint glue layer, and the step S102 may include imprinting the first etching prevention layer 205 to form the first opening 209 on the first etching prevention layer 205.
The imprinting adhesive layer can be a fluorine-containing organic substance, such as a fluorine-containing silane material, and can avoid the phenomenon of adhesive during demolding. And (3) impressing the surface of the impressing glue layer by using an impressing die, demolding to obtain a corresponding group, carrying out nano-size processing by using the impressing glue as a mask, etching the surface of the under-bump metallization layer 204, and cleaning to remove the impressing residual glue. Optionally, the under bump metallization layer 204 is etched by using an inductively coupled plasma etching method, a reactive ion etching method, or a chemical etching method; in other embodiments, other methods may be used to etch the under bump metallization layer 204.
With further reference to fig. 8 and 9, the following steps may be included after step S103:
s104: a solder layer 212 is formed on the under bump metallization pattern layer 210.
Wherein, before forming the solder layer 212 on the under bump metallization pattern layer 210, the first etching prevention layer 205 on the structure shown in fig. d is removed, so as to obtain the structure shown in fig. e. The solder layer 212 may be formed on the under bump metallization pattern layer 210 by chemical deposition, electroplating, screen printing or sputtering, etc., to obtain the structure shown in fig. (f). The solder layer 212 may be made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), phosphorus (P), bismuth (Bi), germanium (Ge), or a combination thereof.
S105: a second etching prevention layer 213 is formed on the solder layer 212.
Here, the second etching prevention layer 213 may be formed on the solder layer 212 by coating to form a structure as shown in fig. (g).
S106: a plurality of second openings 214 are formed on the second etch preventing layer 213 to form a second etch preventing pattern layer 215.
In which a plurality of second openings 214 are formed on the second etch-resistant layer 213 to form the structure shown in fig. (h). The second etch prevention pattern layer 215 may be disposed corresponding to a region 206 over the pad 202 where the passivation layer 203 is not disposed, and may be disposed corresponding to the passivation layer 203 under which the pad 202 is disposed, and may be disposed corresponding to a region of the passivation layer 203 near the pad 202. In addition, there are various opening methods, such as imprinting, exposure and development, according to the material and chemical and physical properties of the second etching resist layer 213.
In one of the application scenarios: the second etching prevention layer 213 is an imprint glue layer, and the second etching prevention layer 213 is imprinted to form a second opening 214 on the second etching prevention layer 213.
In another application scenario: the second etching prevention layer 213 is a photoresist layer, and the second etching prevention layer 213 is exposed and developed to form a second opening 214 on the second etching prevention layer 213.
S107: the solder layer 212 under the second opening 214 is etched to obtain a plurality of bumps 216.
Wherein the solder layer 212 under the second opening 214 is etched to obtain the structure shown in fig. (i). After obtaining a plurality of bumps 216, the second etching resist pattern layer 215 above the bumps 216 is removed to form the structure shown in fig. (j).
In other embodiments, further referring to fig. 10 and 11, the following steps may be included after step S103:
s108: a second etch-resistant layer 213 is formed on the under bump metallization pattern layer 210.
Wherein, before forming the solder layer 212 on the under bump metallization pattern layer 210, the first etching prevention layer 205 on the structure shown in fig. d is removed, so as to obtain the structure shown in fig. e. The second etching prevention layer 213 may be formed on the structure shown in fig. (e) by coating to form the structure shown in fig. (k).
S109: a plurality of second openings 214 are formed on the second etch preventing layer 213.
Wherein a plurality of second openings 214 are formed on the second etch-resistant layer 213 to form the structure shown in fig. (m). The second opening 214 may be disposed corresponding to the region 206 over the pad 202 where the passivation layer 203 is not disposed, and may be disposed corresponding to the passivation layer 203 under which the pad 202 is disposed, and may be disposed corresponding to a region of the passivation layer 203 near the pad 202. In addition, there are various opening methods, such as imprinting, exposure and development, according to the material and chemical and physical properties of the second etching resist layer 213.
In one of the application scenarios: the second etching prevention layer 213 is an imprint glue layer, and the second etching prevention layer 213 is imprinted to form a second opening 214 on the second etching prevention layer 213.
In another application scenario: the second etching prevention layer 213 is a photoresist layer, and the second etching prevention layer 213 is exposed and developed to form a second opening 214 on the second etching prevention layer 213.
S110: solder is filled into the second opening 214 by electroplating or stencil printing to form a bump 216, so as to form the structure shown in fig. (n).
After obtaining a plurality of bumps 216, the second etching-resistant layer 213 is removed above the bumps 216 to form the structure shown in (j). Because the area 206 over the pad 202 not having the passivation layer 203 is not entirely provided with the under bump metallization pattern 210, the upper surface area of the bump 216 corresponding to the second area 219 may be lower than the upper surface areas of the other bumps 216, such that the upper surface area of the bump 216 corresponding to the second area 219 and the upper surface area of the bump 216 adjacent to the periphery form a valley 217. The gas trapped between the substrate and the bump 216 will be gradually pressed to one or more valleys 217 during packaging, so that most surface areas of the bump 216 will not be bonded to the substrate due to the trapped gas, thereby preventing poor contact and improving the reliability of the product.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A method for preparing a bump structure is characterized in that:
forming a first etching prevention layer on the under bump metallization layer;
forming a plurality of first openings in the first etch-resistant layer;
etching the under bump metallization layer below the first opening to form an under bump metallization pattern layer, wherein the under bump metallization pattern layer covers a first region without a passivation layer above the bonding pad and exposes a second region without the passivation layer above the bonding pad;
and forming a solder layer on the under bump metallization pattern layer to obtain a bump covering the under bump metallization pattern layer arranged above the first area and the second area.
2. The method of claim 1, wherein the step of forming the bump structure comprises:
the step of forming a plurality of first openings in the first etch-resistant layer includes:
the first etching prevention layer is a photoresist layer, and the first etching prevention layer is exposed and developed to form the first opening on the first etching prevention layer; or
The first etching prevention layer is an imprinting glue layer, and the first etching prevention layer is imprinted so as to form the first opening on the first etching prevention layer.
3. The method of claim 1, wherein the step of forming the bump structure comprises:
forming a solder layer on the under bump metallization pattern layer to obtain a bump covering the under bump metallization pattern layer and the second region disposed above the first region, comprising:
removing the first etching prevention layer;
forming a solder layer on the under bump metallization pattern layer;
forming a second etching prevention layer on the solder layer;
forming a plurality of second openings on the second etching prevention layer to form a second etching prevention pattern layer;
etching the solder layer below the second opening to obtain a plurality of bumps;
and removing the second etching prevention layer.
4. The method of claim 1, wherein the step of forming the bump structure comprises:
forming a solder layer on the under bump metallization pattern layer to obtain a bump covering the under bump metallization pattern layer and the second region disposed above the first region, comprising:
removing the first etching prevention layer;
forming a second etching prevention layer on the under bump metallization pattern layer;
forming a plurality of second openings on the second etching prevention layer;
filling solder to the second opening by electroplating or stencil printing to form a bump;
and removing the second etching prevention layer.
5. The method of claim 4, wherein the step of forming the bump structure comprises:
the second opening exposes the under bump metallization pattern layer arranged in the area without the passivation layer above the bonding pad.
6. The method of claim 3, wherein the step of forming the bump structure comprises:
the second etching-proof pattern layer covers the under bump metallization pattern layer arranged in the area without the passivation layer above the bonding pad.
7. The method of claim 3 or 4, wherein:
the step of forming a plurality of second openings on the second etching prevention layer includes: the second etching prevention layer is an imprinting adhesive layer and is imprinted so as to form a second opening on the second etching prevention layer; or
The step of forming a plurality of second openings on the second etching prevention layer includes: the second etching prevention layer is a photoresist layer, and the second etching prevention layer is exposed and developed to form a second opening on the second etching prevention layer.
8. A bump structure, comprising:
a wafer;
a pad disposed on an active surface of the wafer;
a passivation layer covering the active surface of the wafer and exposing at least a portion of the bonding pads;
an under bump metallization pattern layer covering a first region over the pad where the passivation layer is not disposed and exposing a second region over the pad where the passivation layer is not disposed;
a bump overlying the under bump metallization pattern layer disposed over the second region and the first region.
9. The bump structure of claim 8, wherein:
the area, which is not provided with the passivation layer, above the pad includes a middle area and a peripheral area surrounding the middle area, the first area is the middle area, and the second area is the peripheral area.
10. The bump structure of claim 8, wherein:
the under bump metallization pattern layer also exposes a region of the passivation layer close to the pad;
the bump covers the area of the passivation layer close to the bonding pad.
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| CN201910277516.3A CN110034025B (en) | 2019-04-08 | 2019-04-08 | Bump structure and preparation method thereof |
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| CN201910277516.3A CN110034025B (en) | 2019-04-08 | 2019-04-08 | Bump structure and preparation method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841667A (en) * | 2005-03-28 | 2006-10-04 | 联华电子股份有限公司 | Method for manufacturing metal coupling |
| CN106328618A (en) * | 2015-06-30 | 2017-01-11 | 台湾积体电路制造股份有限公司 | Under bump metallurgy (UBM) and methods of forming same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI244184B (en) * | 2002-11-12 | 2005-11-21 | Siliconware Precision Industries Co Ltd | Semiconductor device with under bump metallurgy and method for fabricating the same |
| US7364998B2 (en) * | 2005-07-21 | 2008-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming high reliability bump structure |
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2019
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841667A (en) * | 2005-03-28 | 2006-10-04 | 联华电子股份有限公司 | Method for manufacturing metal coupling |
| CN106328618A (en) * | 2015-06-30 | 2017-01-11 | 台湾积体电路制造股份有限公司 | Under bump metallurgy (UBM) and methods of forming same |
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