CN110033807B - Word line ladder and method for alleviating read disturbance by using same - Google Patents
Word line ladder and method for alleviating read disturbance by using same Download PDFInfo
- Publication number
- CN110033807B CN110033807B CN201910159885.2A CN201910159885A CN110033807B CN 110033807 B CN110033807 B CN 110033807B CN 201910159885 A CN201910159885 A CN 201910159885A CN 110033807 B CN110033807 B CN 110033807B
- Authority
- CN
- China
- Prior art keywords
- bit line
- state
- signal
- input
- line tracking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Ladders (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention provides a word line ladder and a method for alleviating read disturbance by using the same, comprising the following steps: the inverter, the PMOS tube and the NMOS tube; the input end of the phase inverter is connected with an input signal, and the output end of the phase inverter, the source electrode of the PMOS tube and the grid electrode of the NMOS tube are connected with a word line; the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube; the grid of the PMOS tube is connected with the output end of the NOT gate; the bit line tracking unit is connected with one input end of the NOT gate. When no external enabling signal is input, the number of the bit line tracking units is changed, so that the working time of the step-up transformer is prolonged, and reading disturbance and half-select interference are reduced; when an external enabling signal is input, the number of the bit line tracking units is adjusted by comparing the charging and discharging time of the input signal of the bit line tracking unit with the charging and discharging time of the external enabling signal, so that the reading disturbance and half-select interference of the step-up transformer are reduced, the instability of the circuit under low-voltage operation is reduced, and the low yield is avoided.
Description
Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly to a word line ladder and a method for mitigating read disturb using the same.
Background
Static Random-Access Memory (SRAM) is widely used in a system on a chip (SoC) and a cache of a processor, and it also occupies a large portion of the chip area, limiting the chip minimum voltage Vmin due to power and the like. The design rules used for static access memory are the most stringent and are therefore very sensitive to process, voltage, temperature, etc. variations. The circuit technology proposed so far can be a word line reduction technology, which mainly alleviates the disturbance generated during reading and half select disturb (half select disturb), but this technology is used to reduce the ability of writing at low voltage.
Therefore, it is desirable to provide a new word line ladder and a method for using the word line ladder to alleviate the read disturb to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a word line ladder and a method for alleviating read disturb using the same, which are used to solve the problem of the prior art that the write capability is reduced at low voltage due to the half-select disturb and disturb caused during read.
To achieve the above and other related objects, the present invention provides a word line ladder comprising: the inverter, the PMOS tube and the NMOS tube; the input end of the phase inverter is connected with an input signal, and the output end of the phase inverter, the source electrode of the PMOS tube and the grid electrode of the NMOS tube are connected with a word line; the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, and the source electrode of the NMOS tube is grounded; the grid electrode of the PMOS tube is connected with the output end of the NOT gate; a bit line tracking unit connected to one of the inputs of the not gate.
Preferably, the inverter further comprises a decoder, and the input signal connected to the input end of the inverter is provided by the decoder.
Preferably, the inverter further comprises another inverter INV, and an output end of the inverter INV is connected to another input end of the not gate.
Preferably, an input end of the inverter INV is connected to the enable signal EB.
Preferably, the number of the bit line tracking cells ranges from 8 to 512.
Preferably, the bit line tracking cell has a cell number of 16, 64 or 128.
The invention also provides a method for alleviating read disturbance by using the word line elevator, which at least comprises the following steps: step one, the state of the decoder input decoding signal is 0, so that the step lifter is in a reading or writing state; the state of an initial signal input by the bit line tracking unit is 1, and the input state of the enable signal EB is 1; selecting the unit number of the bit line tracking unit, changing the initial signal state of the bit line tracking unit from 1 to 0, and enabling the word line waveform to climb in a step shape; and step three, changing the unit number of the bit line tracking unit, changing the initial signal state of the bit line tracking unit from 1 to 0, and enabling the word line waveform to climb in a step shape.
Preferably, the method further comprises a fourth step of selecting the number of the bit line tracking units, setting the input signal state of the decoder to 0, changing the input state of the enable signal EB from 0 to 1, and simultaneously changing the initial signal state of the bit line tracking units from 1 to 0, so as to prolong the working time of the ramp up device and reduce the read disturbance.
Preferably, the number of the bit line tracking cells ranges from 8 to 512.
Preferably, the number of cells of the selected bit line tracking cell is 16, 64 or 128.
Preferably, when the state of the decoder input decoding signal is 1, the state of the enable signal is 0 or 1; the input signal state of the bit line tracking cell is 1.
As described above, the word line ladder and the method for mitigating read disturbance using the word line ladder of the present invention have the following advantages: when no external enabling signal is input, the number of the bit line tracking units is changed, so that the working time of the step-up transformer is prolonged, and reading disturbance and half-select interference are reduced; when an external enabling signal is input, the number of the bit line tracking units is adjusted by comparing the charging and discharging time of the input signal of the bit line tracking unit with the charging and discharging time of the external enabling signal, so that the reading disturbance and half-select interference of the step-up transformer are reduced, the instability of the circuit under low-voltage operation is reduced, and the low yield is avoided.
Drawings
FIG. 1 is a schematic circuit diagram of a word line ladder according to the present invention;
FIG. 2 is a schematic diagram showing the word line waveforms corresponding to different numbers of bit line tracking cells according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, fig. 1 is a circuit diagram of a word line ladder according to the present invention. The present embodiment provides an word line ladder, including: an inverter INV _ WL, a PMOS tube MP1 and an NMOS tube MN 1; the input end of the inverter INV _ WL is connected with an input signal, and the output end of the inverter INV _ WL, the source electrode of the PMOS transistor MP1 and the gate electrode of the NMOS transistor MN1 are connected with a word line WL; the drain electrode of the PMOS tube MP1 is connected with the drain electrode of the NMOS tube MN1, and the source electrode of the NMOS tube MN1 is grounded; in the present embodiment, the word line elevator further includes a decoder (decoder) as shown in fig. 1, and the input signal connected to the input terminal of the inverter INV _ WL is provided by the decoder. That is, the decoded signal is provided by the decoder, and after the decoded signal passes through the inverter INV _ WL, the decoded signal is inverted, for example, if the state of the provided decoded signal is 1, the representative signal is not decoded, if the state is 0, the representative signal is decoded, after the signal passes through the inverter INV _ WL, the signal with the original state of 1 is inverted to the signal with the state of 0, and conversely, after the signal with the original state of 0 passes through the inverter INV _ WL, the signal with the original state of 1 is inverted to the signal with the state of 1. When a signal passing through the inverter INV _ WL is high level 1, the word line WL is charged.
As shown in fig. 1, the wordline ramp-up device of the present invention further includes a NOR gate having two input terminals and a bitline tracking unit BLTC, wherein the gate of the PMOS transistor MP1 is connected to the output terminal of the NOR gate; a bit line Tracking Cell (BL Tracking Cell) connected to one of the inputs of the not gate NOR. The number of cells in the bit line tracking cell may vary the duration of time the ramp is operated. Therefore, the cell number of the bit line tracking cell ranges from 8 to 512. Further, the bit line tracking cell preferably has a cell number of 16, 64 or 128.
As shown in fig. 1, the elevator lift preferably further includes another inverter INV, and an output terminal of the inverter INV is connected to another input terminal of the not gate NOR. Further, an input end of the inverter INV is connected to the enable signal EB. That is, the not gate NOR has two inputs, one of which receives the signal EB2 output by the bit line tracking unit and the other of which receives the signal EB1 output from the inverter INV.
When the state of the input signal of the decoder is 1, no decoding action is indicated. Therefore, the word line WL is low. At this time, if the input signal EB2 of the bit line tracking unit is set to 1, the state of the signal EB3 is 0 after the not gate NOR, and the ramp is in a standby state. When the input signal state of the decoder is 0, the decoder represents that a signal is decoded, the decoded signal is inverted after passing through the inverter INV _ WL, the signal state is changed to 1, and the word line WL is at a high level.
The invention also comprises a method for alleviating reading disturbance by using the elevator, which specifically comprises the following steps:
step one, the state of the decoder input decoding signal is 0, so that the step lifter is in a reading or writing state; the state of the bit line tracking unit inputting an initial signal is 1, and the input state of the enable signal EB is 1. That is, when the state of the input signal of the decoder is 0, it means that the signal is decoded, and after the decoded signal passes through the inverter INV _ WL, the signal state is inverted to become a signal of state 1, and the word line WL is charged to a high level. The lift is then in a read or write (R/W) state. At this time, the state of the bit line tracking unit to which the initial signal is input is set to 1 (the state of the signal EB2 is set to 1), and the input state of the enable signal EB is set to 1.
See the following truth table, which is shown as a truth table for each signal of the ladder lift. It can be seen that in the first read/write state in the truth table, in the initial state of the above signals, the enable signal EB (initial state is 1) is inverted to the signal EB1 with state 0 after passing through the inverter INV, and the two input terminals of the not gate NOR receive the EB1 signal with state 0 and the EB2 signal with state 1 respectively, and the two signals are output to the EB3 signal with state 0 after passing through the not gate NOR.
For the PMOS transistor MP1, it is turned on when the gate is low, so when the EB3 signal state is a low signal of 0, the PMOS transistor MP1 is turned on. Referring to FIG. 2, FIG. 2 is a schematic diagram of the word line WL waveforms corresponding to different numbers of bit line tracking cells according to the present invention. The waveform line 01 is a word line waveform when the number of bit line tracking cells is 16, the waveform line 02 is a word line waveform when the number of bit line tracking cells is 64, and the waveform line 03 is a word line waveform when the number of bit line tracking cells is 128. And the PMOS transistor MP1 is turned on, the waveform of the word line rises sharply in a short time and a first step occurs.
Selecting the unit number of the bit line tracking unit, changing the initial signal state of the bit line tracking unit from 1 to 0, and enabling the word line waveform to climb in a step shape; preferably, the number of the bit line tracking cells ranges from 8 to 512. Further, the number of cells of the selected bit line tracking cell is 16, 64, or 128. In this embodiment, the number of the bit line tracking cells is selected to be 16. With reference to the truth table, the state of the initial signal BE2 of the bit line tracking unit is changed from 1 to 0, that is, the signal EB2 of the bit line tracking unit is discharged in the process of changing from 1 to 0, the state of the EB3 signal is changed from 0 to 1, and when the signal EB3 is in a state of 0, the PMOS transistor MP1 is turned off. As can be seen from fig. 2, the word line waveform begins to ramp up after the first step.
And step three, changing the unit number of the bit line tracking unit, changing the initial signal state of the bit line tracking unit from 1 to 0, and enabling the word line waveform to climb in a step shape. Referring to the above truth table, it can be seen that, in the case that the number of the bit line tracking cells in step two is 16, when the state of the initial signal EB2 of the bit line tracking cell changes from 1 to 0, the word line waveform is the waveform line 01. In step two, the cell number of the bit line tracking cell is changed, preferably from 16 to 64 or 128. Setting the state of a decoding signal input by the decoder to be 0, and enabling the elevator to be in a reading or writing state; and changes the signal EB2 state of the bit line tracking unit from 1 to 0, and the input state of the enabling signal EB is still set to be 1. At this time, a word line waveform 02 corresponding to the bit line tracking cell of fig. 2 having a cell number of 64 appears, and a 03 waveform line corresponding to the bit line tracking cell of fig. 2 having a cell number of 128 appears. It can be seen that the larger the number of the bit line tracking cells, the longer the corresponding word line waveform delay. The more stable the operating time of the elevator, the less read disturbances.
Example two
After the three steps of the first embodiment are performed, the number of the bit line tracking units is selected, so that the working stability of the step-up transformer corresponding to different numbers of the bit line tracking units can be compared, and the read disturbance and half-select disturbance can be reduced. In the embodiment, an external signal is input to the step-up transformer without changing the number of the bit line tracking units, so that the stability of the operation of the step-up transformer is adjusted, and the read disturbance and half-select interference are reduced.
The steps of this embodiment may be supplemented by the steps performed after the three steps in embodiment one are performed. Or may be implemented independently. Preferably, after the three steps of the first embodiment, the fourth step is performed to select the cell number of the bit line tracking cell, and the cell number of the bit line tracking cell preferably ranges from 8 to 512. Further, the number of cells of the selected bit line tracking cell is 16, 64, or 128. Referring to the truth table, the input signal state of the decoder is set to be 0, the input state of the enable signal EB is changed from 0 to 1, and simultaneously the initial signal EB2 state of the bit line tracking unit is changed from 1 to 0, so that the working time of the ramp is prolonged, and the read disturbance is reduced. That is, the initial state of the enable signal EB is 0 and changes its state to 1; in the process of changing the enabling signal EB from 0 to 1 and simultaneously changing the initial signal EB2 of the bit line tracking unit from 1 to 0, when the enabling signal state is 0, the EB1 signal state is 1, the EB2 signal state is selected to be 1, and after the EB1 signal (state is 1) and the EB2 signal (state is selected to be 1) pass through the NOT gate NOR, the EB3 signal state is 0; when the enable signal EB is changed from 0 to 1, the signal state of EB1 is 0, and the signal state of EB2 is changed from 1 to 0, so that the signal state of EB3 is 1 after the EB1 signal (state is 0) and the EB2 signal (state is selected to be 0) pass through the NOR gate NOR. When the EB3 state is 1, the PMOS transistor MP1 is turned off.
However, the enabling signal EB is changed from 0 to 1 and the EB2 signal is changed from 1 to 0, which are not synchronous, and the working state of the step-up transformer lasts for different time when the time required by the enabling signal EB and the time required by the EB2 signal to change the state are different. Therefore, when the number of cells of the bit line tracking cell is selected in advance, the time required for the enable signal EB to change from 0 to 1 does not coincide with the time required for the EB2 signal to change from 1 to 0, the operating state of the step-up converter can be continued for a short time. In order to maintain the duration of the operating state of the ramp-up device and reduce the read disturb, the number of cells of the appropriate bitline tracking cells can be selected, step four of the present embodiment is executed, the time when the enable signal EB changes from 0 to 1 and the time when the EB2 signal changes from 1 to 0 are selected, the two times are compared, and the number of the appropriate bitline tracking cells is selected, so that the operating duration of the ramp-up device can be effectively increased and the read disturb can be reduced, and the Read Static Noise Margin (RSNM), half select disturb (half select disturb) and write margin (write margin) can be reduced.
Preferably, when the state of the decoder input decoding signal is 1, the state of the enable signal EB is 0 or 1; the input signal state of the bit line tracking cell EB2 is 1. In this state, the elevator is in a standby state.
In summary, in the present invention, when no external enable signal is input, the number of the bit line tracking cells is changed, so as to extend the operating time of the ramp, thereby reducing the read disturb and half-select disturb; when an external enabling signal is input, the number of the bit line tracking units is adjusted by comparing the charging and discharging time of the input signal of the bit line tracking unit with the charging and discharging time of the external enabling signal, so that the reading disturbance and half-select interference of the step-up transformer are reduced, the instability of the circuit under low-voltage operation is reduced, and the low yield is avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. An wordline elevator, comprising:
the inverter, the PMOS tube and the NMOS tube; the input end of the phase inverter is connected with an input signal, and the output end of the phase inverter, the source electrode of the PMOS tube and the grid electrode of the NMOS tube are connected with a word line; the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, and the source electrode of the NMOS tube is grounded;
the grid electrode of the PMOS tube is connected with the output end of the NOT gate;
a bit line tracking unit connected to one of the inputs of the not gate;
a decoder, wherein the input signal connected with the input end of the inverter is provided by the decoder;
the output end of the inverter INV is connected with the other input end of the NOT gate;
the input end of the inverter INV is connected with an enable signal EB.
2. The word line elevator as recited in claim 1, wherein: the number of the bit line tracking cells ranges from 8 to 512.
3. The word line elevator as recited in claim 2, wherein: the bit line tracking cell has a cell number of 16, 64, or 128.
4. A method of mitigating read disturb using the wordline ramp of claim 3, wherein: the method at least comprises the following steps:
step one, the state of the decoder input decoding signal is 0, so that the step lifter is in a reading or writing state; the state of an initial signal input by the bit line tracking unit is 1, and the input state of the enable signal EB is 1;
selecting the unit number of the bit line tracking unit, changing the initial signal state of the bit line tracking unit from 1 to 0, and enabling the word line waveform to climb in a step shape;
and step three, changing the unit number of the bit line tracking unit, changing the initial signal state of the bit line tracking unit from 1 to 0, and enabling the word line waveform to climb in a step shape.
5. The method of mitigating read disturb using a wordline ramp as recited in claim 4, wherein: the method also comprises a fourth step of selecting the unit number of the bit line tracking unit, setting the input signal state of the decoder to be 0, changing the input state of the enable signal EB from 0 to 1, and simultaneously changing the initial signal state of the bit line tracking unit from 1 to 0, so that the working time of the step-up transformer is prolonged, and the reading disturbance is reduced.
6. The method of mitigating read disturb using a wordline ramp as recited in claim 5, wherein: the number of the bit line tracking cells ranges from 8 to 512.
7. The method of mitigating read disturb using a wordline ramp as recited in claim 6, wherein: the number of cells of the selected bit line tracking cell is 16, 64 or 128.
8. The method of mitigating read disturb using a wordline ramp as recited in claim 7, wherein: when the state of the decoder input decoding signal is 1, the state of the enabling signal is 0 or 1; the state of the input signal of the bit line tracking unit is 1, and in this state, the step-up transformer is in a standby state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910159885.2A CN110033807B (en) | 2019-03-04 | 2019-03-04 | Word line ladder and method for alleviating read disturbance by using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910159885.2A CN110033807B (en) | 2019-03-04 | 2019-03-04 | Word line ladder and method for alleviating read disturbance by using same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110033807A CN110033807A (en) | 2019-07-19 |
| CN110033807B true CN110033807B (en) | 2021-06-15 |
Family
ID=67235080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910159885.2A Active CN110033807B (en) | 2019-03-04 | 2019-03-04 | Word line ladder and method for alleviating read disturbance by using same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110033807B (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100282044B1 (en) * | 1998-08-04 | 2001-03-02 | 윤종용 | Semiconductor memory device |
| US6031768A (en) * | 1998-12-18 | 2000-02-29 | Stmicroelectronics, Inc. | Self boosted wordline |
| US7277315B2 (en) * | 2005-12-14 | 2007-10-02 | Etron Technology, Inc. | Multiple power supplies for the driving circuit of local word line driver of DRAM |
| KR100877103B1 (en) * | 2007-06-01 | 2009-01-07 | 주식회사 하이닉스반도체 | Method of reading flash memory device for depressing read disturb |
| JP2014063555A (en) * | 2012-09-24 | 2014-04-10 | Toshiba Corp | Nonvolatile semiconductor memory device and control method of the same |
| CN203376978U (en) * | 2013-08-17 | 2014-01-01 | 赵训彤 | Bit line negative voltage circuit capable of improving SRAM writing capacity |
| US9311968B2 (en) * | 2013-09-18 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Read tracking mechanism |
| CN108665931B (en) * | 2018-05-21 | 2021-04-13 | 上海华力集成电路制造有限公司 | Bit line pre-step down transformer |
-
2019
- 2019-03-04 CN CN201910159885.2A patent/CN110033807B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110033807A (en) | 2019-07-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Kanda et al. | 90% write power-saving SRAM using sense-amplifying memory cell | |
| Pilo et al. | A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements | |
| JP5932133B2 (en) | Memory cell with improved write margin | |
| CN102859601B (en) | There is the stability of improvement and the low-power 5T SRAM of the bit location size of reduction | |
| TWI464745B (en) | Static random access memory with data controlled power supplying | |
| US5302870A (en) | Apparatus for providing multi-level potentials at a sense node | |
| US7420835B2 (en) | Single-port SRAM with improved read and write margins | |
| US10847208B2 (en) | Memory device system-on-chip including the same and method of operating the same | |
| TWI543157B (en) | Static randoom access memory and method thereof | |
| Lien et al. | A 40 nm 512 kb cross-point 8 T pipeline SRAM with binary word-line boosting control, ripple bit-line and adaptive data-aware write-assist | |
| Kim et al. | A 1.85 fW/bit ultra low leakage 10T SRAM with speed compensation scheme | |
| JP2009543267A (en) | Integrated circuit having memory for reading / writing operation at low voltage | |
| US20130121065A1 (en) | Dynamic wordline assist scheme to improve performance tradeoff in sram | |
| CN103077741A (en) | Low-voltage operation storage unit circuit of SRAM (Static Random Access Memory) | |
| CN110277120B (en) | Single-ended 8-tube SRAM memory cell circuit capable of improving read-write stability under low voltage | |
| Xue et al. | A 28-nm 320-kb TCAM macro using split-controlled single-load 14T cell and triple-margin voltage sense amplifier | |
| US20140340977A1 (en) | Low power transient voltage collapse apparatus and method for a memory cell | |
| US11776623B2 (en) | Bitline precharge system for a semiconductor memory device | |
| Akashe et al. | Analysis of power in 3T DRAM and 4T DRAM cell design for different technology | |
| CN110033807B (en) | Word line ladder and method for alleviating read disturbance by using same | |
| KR102502535B1 (en) | Capacitive wordline boosting | |
| Nayak et al. | Power efficient design of a novel SRAM cell with higher write ability | |
| Ye et al. | A 6-GHz 16-kB L1 cache in a 100-nm dual-V/sub T/technology using a bitline leakage reduction (BLR) technique | |
| US11017848B2 (en) | Static random-access memory (SRAM) system with delay tuning and control and a method thereof | |
| US5206551A (en) | Method for providing multi-level potentials at a sense node |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |