CN110018407A - TSV failure non-contact type test method based on complex incentive - Google Patents
TSV failure non-contact type test method based on complex incentive Download PDFInfo
- Publication number
- CN110018407A CN110018407A CN201910095503.4A CN201910095503A CN110018407A CN 110018407 A CN110018407 A CN 110018407A CN 201910095503 A CN201910095503 A CN 201910095503A CN 110018407 A CN110018407 A CN 110018407A
- Authority
- CN
- China
- Prior art keywords
- tsv
- test
- signal
- peak
- failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of TSV failure non-contact type test method based on complex incentive, it is related to electrical testing, the multi-tone signal of optimization with additive white Gaussian noise is amplified and the composite test pumping signal being modulated with the radio-frequency carrier signal of a same frequency is applied on TSV circuit to be measured by being based on capacity coupled non-contact optical probe, the peak-to-average force ratio of output response is detected and calculated by envelope detector, again compared with the peak-to-average force ratio of fault-free TSV, determine that tested TSV whether there is failure according to peak-to-average force ratio difference, then emulation testing is carried out according to the equivalent electrical model of through silicon via for building known physical fault on circuit simulating software and obtains the relational graph of peak-to-average force ratio Yu fault signature size, finally by the measured value failure in contrast estimated there are which kind of size, this method can detect small ruler Very little failure improves the sensitivity of test to a certain extent.
Description
Technical field
The present invention relates to three dimensional integrated circuits fault test field, in particular to a kind of TSV failure based on complex incentive
Non-contact type test method.
Background technique
With the fast development of integrated circuit technique and semiconductor fabrication process, it is very big that integrated circuit presents scale
The features such as change, size microminiaturization, function diversification, material newcooperative medical system, signal high frequency.Nowadays the transistor ruler in integrated circuit
It is very little to have been decreased to 14nm, the 10nm epoch will be striden into quickly.Traditional two-dimentional integrated technology can not effectively solve high speed signal
The challenge that transmission requirement is proposed, it is more difficult to continue Moore's Law.Therefore to the high speed development of maintenance IC, there is an urgent need to expand
New development space.The multiple bare chips of vertical stacking or circuit module are simultaneously electrically connected shape between the different layer devices of TSV realization
At three dimensional integrated circuits (3D IC), interconnection length can not only be highly shortened and significantly improve device integration density,
It can also realize the heterogeneous integrated of different technologies node, the device of different function or module, become having for super Moore's Law development
Sharp scheme.TSV technology is the integrated core of 3D IC, it can make product have better electric property, lower power consumption, higher
Bandwidth and density, smaller size, lighter weight, obtained extensive fortune on the circuit functions unit such as modulus, radio frequency
With.Although TSV technology has many advantages, huge technique and test challenge are also brought.
Signal transmission passage of the TSV as multiple bare die vertical stackings, reliability directly affect entire chip circuit
Yields.Due to the complexity of current TSV preparation process and still immature, so that all may be used during TSV manufacture, binding etc.
Failure relevant to TSV can occur, be divided into cavity, pin hole, dislocation, crackle etc. by physical structure；The technique rank generated by failure
Section be divided into binding before, binding in and binding after failure.Simultaneously in the case where high-frequency high-speed, change of the signal transmission performance to size
Change extremely sensitive, TSV physical structure failure will cause the decaying of transmission signal, even distortion completely, especially receive ruler in sub-micro
Very little lower problems of Signal Integrity is more prominent.In addition in execution circuit function, the weak failure in TSV may be degenerated to calamity
Failure.These recessive problems have direct and significant influence to the overall performance of the reliability of TSV and 3D IC.Current system
Making technology allows TSV density to be up to 10k/mm2, TSV quantity sharply increases, shadow of these structures vulnerable to mechanical and thermal stress etc.
It rings so as to cause different degrees of failure, finally chip yield is substantially reduced.And high technology complexity and height in 3D IC
Cost makes yield requirement higher.Therefore, in order to guarantee the quality of 3D IC, the fault detection for TSV just becomes especially
It is important.
The domestic and international scheme tested for TSV in 3D IC and process are not also very perfect at present, can only detect one kind mostly
Or two kinds of rough logic faults and test peripheral circuit area overhead it is big, size and position for failure are not deeply
Research.In face of complicated fault type, deep-submicron dimensional structure and magnanimity high-density test object, lack effective inspection
The problems such as surveying the method and special equipment of TSV failure brings unprecedented challenge for the measuring technology of TSV failure.Cause
This, has very important significance for the further further investigation tool of the test method of micro-nano size and ultra high density TSV array.Electricity
Learning test is a kind of test method being widely noticed in recent years, it can not only complete TSV fault test, while can also realize 3D
The function and performance test of IC.Test and excitation used in existing electrical detection method is simple single source signal mostly, and is surveyed
The selection for trying excitation is particularly important in the case where circuit structure is fixed, and test resolution can be improved by designing suitable test and excitation
Rate.Another point considers the application problem of excitation, and with the increase of super large-scale integration density, tradition machinery probe technique is
It is unable to satisfy growing nanoscale detection demand, it and TSV scale matching problem and contact pressure are caused by wafer
The contact problems such as damage have seriously affected 3D IC development, and furthermore contact probe itself can be damaged because contacting and sliding repeatedly
It is bad, periodic maintenance is needed to increase testing cost, therefore is badly in need of the breakthrough of TSV fault test theoretical method and technology.Therefore
Efficient TSV fault test new method is explored and studied, while persistently improving the detection accuracy, stability and inspection of all kinds of methods
Surveying efficiency is the important topic of semicon industry and research institution from now on.The non-contact testing and diagnostic measurement of rising in recent years
Method can solve many challenges relevant to traditional wafer test, its not restriction by measurand structure has non-damage
The features such as wound is tested, peripheral test circuit frame is flexible has wide research and application prospect in TSV test.
Summary of the invention
To solve the above problems, the present invention provides a kind of TSV failure non-contact type test method based on complex incentive.
This be it is a kind of based on multitone shake 3-D IC in TSV failure non-contact type test method.It is also based on electricity
Test method, mainly by the composite excitation signal based on multi-tone signal, supplemented by radio-frequency modulations by being based on capacitive coupling
Non-contact probe deactivate TSV interlock circuit to be measured, then circuit is received to obtain output response by envelope detector etc. --
Peak-to-average force ratio (PAR) carrys out detection circuit fault condition.By analyze and compare between the PAR with and without failure TSVs difference degree come
Realize the diagnosis of TSV fault type and size.
The main body of complex incentive -- multi-tone signal is composed of according to different needs multiple tone signals, is wrapped in signal
The information contained is also just more, carries out fault test with it, the output signal of circuit carries a variety of amplitude-frequencies letter related to phase
Breath, therefore the fault sample packet collected just contains more identifiability features, and diagnostic accuracy can be improved.The multitone of this method
Signal is to be formed by stacking by a reference sinusoidal signal by multiple sounds that the random phase shift of Gaussian distributed generates, and it is right
Phase distortion is more sensitive.Test fault-free and faulty circuit, their output voltage meeting under the conditions of the excitation of identical multitone
Have that accumulated phase is poor, this cumulative phase variation causes the rms voltage (Vrms) of the output signal there are faulty circuit to have
Significant changes.The value can change with the type of the defect of introducing, and additionally depend on the tuple and frequency of multi-tone signal.For
The variation of the phase shift and its Vrms value is effectively utilized, therefore the peak-to-average force ratio (PAR) of circuit-under-test output is referred to as test
Mark characterization, expression formula are as follows:Wherein crest voltage is Vpeak=maxt| u (t) }, rms voltage
ForUsing crosstalk couplings theory, with TSV for aggrieved carrier, spy disk is signal to attack carrier,
It establishes and is based on capacity coupled non-contact testing structure, formed by non-contact spy disk and micro convex point (Bump) combination of miniature scale
One capacitor, and the surface of non-contact spy disk and Bump are very close, know only through 3 D electromagnetic emulation when its spacing is enough
The electric field strength of small formation is just enough to realize the purpose of non-contact testing.The size of coupled capacitor depends on visiting between disk and TSV
Distance and the size of overlapping region.However, since capacitor plate spacing is compared with the non-contact size for visiting disk, edge at this time
Capacitor cannot be ignored, and fully consider when doing equivalent circuit.It is had studied by HFSS full-wave simulation and visits disk and pad pitch
Insertion loss of the difference under higher frequency and transfer impedance and both overlapping region, further determine that visit disk and micro convex point it
Between optimum signal transmission range be 2um, and dielectric material therebetween be silicon nitride, and visit plate-like probe size and TSV it is micro-
The size of salient point (Bump) is consistent.This method can be measured with faster technique and simple instrument high density and it is close between
Away from TSVs, this coupling technique can be used for carrying out the TSV before and after each bonding test.
Since test and excitation passes through non-contact testing structure -- capacitive coupling, significantly signal decaying certainly will be had,
The composite test signal for needing specially to design guarantees the resolution ratio of final fault test.Complex incentive is mainly by required survey
It tries to amplify the multi-tone signal with additive white Gaussian noise by low-noise amplifier under frequency, re-modulation radio-frequency carrier signal
Come what is generated.Influence of the complicated test and excitation for the resolution ratio of TSV failure non-contact testing, is somewhat dependent on
The design of modulator, we mainly consider mixing and two kinds of frequency modulation herein.The first pursues signal to overcome signal to decay
Maximum power transfer using the design of active Gilbert double balanced mixer, and does the impedance matching under corresponding high-frequency test.
The variable phase shift method in second of main circuit LC constituted using varactor realizes indirect frequency modulation.Multi-tone signal experienced by
The RMS value of intermodulation effect caused by mission nonlinear and gain, output signal varies widely.And the multi-tone signal of modulation
Have more combination frequency components, decaying of the signal in transmission process can be made up, fault coverage can be improved, be conducive to whole
The raising of the fault test precision of body.Simultaneously as the complexity of synthesis test signal, test the output response of circuit for
The internal information of TSV equivalent fault circuit has preferable reaction, there is the test of TSV small fault compared with high-resolution.Test electricity
Road also only includes TSV equivalent circuit and fault equivalence circuit, does not need to do particularly design and goes to take test circuit built, avoids
The test error of test circuit itself, while also reducing testing cost and time.The event of TSV need to only be changed using this method
Hinder equivalent circuit, so that it may test TSV difference physical structure failure, certain specific fault can only be tested in contrast to those
Test method improve fault coverage.In addition, the accuracy of test method and sensitivity can also pass through optimization multitone letter
Number change.Different due to choosing to the parameters in multi-tone signal, the resolving power of test result also can not be identical.In order to mention
High fault diagnosis rate, particularly as being number of tones i, fundamental frequency f to multi-tone signal0, angular frequency the π Δ of changes delta ω=2 f0, first phase
Position θiAnd the amplitude A of each soundiParameter is preferentially chosen.Its
Middle i indicates the number of tones of multi-tone signal, AiAnd θiIt is expressed as the amplitude and initial phase of i-th of sound, f0Indicate fundamental frequency, Δ f0
Indicate side frequency interval.Wherein number of tones is more, and the root-mean-square value of produced pumping signal is higher, and the increase of i can improve this
The accuracy of test method, but number of tones also implies that generation process is more complicated, therefore want balance test precision and signal
The complexity of generation must choose suitable number of tones and generate multi-tone signal.The amplitude range of each sound is by operating voltage and tone
Number codetermines.Fundamental frequency, the respectively arranged difference in side frequency interval make the period of multi-tone signal different, and the two also can shadow
Ring the resolution ratio for arriving fault test.Experiments verify that setting initial phase is 0, there is higher PAR value, and multitone can be made to shake
Test signal PAR value when test is with and without failure TSV circuit has bigger difference, therefore does not consider the initial phase of multi-tone signal.
This method can be carried out using following steps:
1) there are the TSVs equivalent-circuit models of physics structure failure for foundation.Equivalent electricity is carried out by object of GS-TSV structure
Gas modeling, then analyzes the formation mechenism of each physical fault and establishes corresponding fault equivalence circuit model, exports equivalent circuit
The formula of mathematical of each parameter, then the correctness of each model is verified with Q3D simulation modeling result, it is finally that GS-TSV is equivalent
Electrical model is combined with fault model, obtains the GS-TSV equivalent-circuit model there are physics structure failure.
2) generation of test and excitation signal is synthesized.Design generation one meets survey in SABER and ADS simulation Software Platform
The multi-tone signal of examination demand, and additive white Gaussian noise is added on multi-tone signal, then by the signal through low-noise amplifier
Amplification, then be modulated with the radio-frequency carrier signal of a same frequency, generate synthesis test and excitation signal.
3) theoretical using crosstalk couplings, with TSV for aggrieved carrier, spy disk is signal to attack carrier, establishes and is based on capacitor coupling
The non-contact testing structure of conjunction.Disk size is probed by HFSS, visits disk and different the inserting under higher frequency of pad pitch
Enter loss and transfer impedance, further determines that and visit dish structure and its optimum signal transmission range between pad.Then it derives
The equivalent circuit of the related lumped parameter RLCG of non-contact testing structure out, and this is verified through HFSS three-dimensional artificial modeling result
The correctness of model.
4) multitone jitter test is carried out to fault-free GS-TSV circuit.Setup test circuit passes through synthesis test and excitation
Non-contact testing structure is applied to trouble-free GS-TSV equivalent circuit and carries out emulation testing, then is measured by envelope detector defeated
The root-mean-square value and crest voltage of outlet record test result, calculate peak-to-average force ratio.
5) corresponding emulation testing is carried out to faulty GS-TSV equivalent circuit, records test result, and it is equal to calculate peak
Than, then change the factors such as the type of physical structure failure, characteristic size and carry out emulation testing again and record peak-to-average force ratio, arrange data
And draw out the relational graph of peak-to-average force ratio Yu TSV fault signature size.
6) test result compares, and test result when by TSV with and without failure compares and calculate peak-to-average force ratio difference, when
The absolute value of difference illustrates TSV there are failure when being greater than 0.1, and judge fault type and greatly according to the difference degree of peak-to-average force ratio
It is small, to realize the detection to failure.The changing rule between the physical damnification factor of these failures and peak-to-average force ratio is analyzed, is continued
Optimization composite excitation signal simultaneously carries out dependence test, improves the resolution of TSV fault detection.
7) the multitone synthesis test and excitation signal used in step 2 is generated with actual hardware circuit.Utilize any wave
Shape generator generates required multi-tone signal, and adds white Gaussian noise, amplifies using low-noise amplifier to it.Make
Radio-frequency carrier signal is generated with radio-frequency signal generator, and multi-tone signal is modulated with treated, it is multiple to obtain multitone shake
Close test signal.
8) practical TSVs to be measured is connected by contactless structure with the pin of test platform, and multitone is shaken compound
Test signal is applied to the non-contact spy disk of test platform, obtains the peak value and root mean square of output end by envelope detector measurement
Threshold voltage calculates to obtain peak-to-average force ratio.
9) actually detected value and the peak-to-average ratio in the relational graph of peak-to-average force ratio-TSV fault signature size are compared, according to
Peak-to-average force ratio difference determines that tested TSVs whether there is failure and there are which kind of failures.
If mismatch or erroneous judgement then advanced optimize multitone shake composite excitation signal and update TSV fault equivalence circuit
It is tested, the number of tones for such as increasing multi-tone signal recombines multitone jittered test signal and tested, and can improve test essence
Degree.
On the whole, the non-contact type test method of multitone shake can be to as low as several microns of TSV physical structure failure
It is effectively differentiated, and can be in the case where not damaging to geodesic structure to different single failures (pin hole, cavity, crackle etc.)
Effectively detected.This method survey based on capacity coupled TSVs failure using radio-frequency carrier signal modulation multi-tone signal
Examination, the peripheral test circuit design that can be effectively solved conventional probe test and large area are damaged and are perplexed to TSV bring,
Testing cost and time are greatly reduced simultaneously.
The present invention is based on the non-contact type test methods of multitone shake complex incentive to be examined by test index peak-to-average force ratio
Break out of order type and size, this method provides presence in relation to failure, position and geometrical characteristic as much as possible
Infomation detection improves the sensitivity tested small fault in deep submicron structures, improves physical structure fault identification
Accuracy.
Detailed description of the invention
Fig. 1 is empty failure GS-TSV electric test model in embodiment provided by the invention；
Fig. 2 is the single TSV general structure schematic diagram in embodiment provided by the invention with non-contact optical probe；In the figure
Mark 1 is silicon base, and 2 be bottom oxide layer, and 3 be passivation layer, and 4 be metal intermetallic dielectric layer, and 5 be TSV insulating layer, and 6 be the center TSV
Copper conductor, 7 be air layer or silicon nitride layer, and 8 be contactless spy disk；
Fig. 3 is the waveform diagram that test and excitation signal is synthesized in embodiment provided by the invention；
Fig. 4 is the waveform diagram of the output response of fault-free GS-TSV in embodiment provided by the invention；
Fig. 5 is the output response wave that the GS-TSV of fault-free and four kinds of empty failures is tested in embodiment provided by the invention
Shape figure；
Fig. 6 is empty failure measure figure in embodiment provided by the invention；
Fig. 7 is hole leaks failure measure figure in embodiment provided by the invention.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application embodiment clearer, implement below in conjunction with the application
Fig. 1~7 in mode are clearly and completely described the technical solution in the application embodiment, it is clear that described
Embodiment is a part of embodiment of the application, rather than whole embodiments.Based on the embodiment in the application, originally
Field those of ordinary skill every other embodiment obtained without creative efforts, belongs to this Shen
The range that please be protect.Therefore, the detailed description of the presently filed embodiment provided in the accompanying drawings is not intended to limit below
Claimed scope of the present application, but it is merely representative of the selected embodiment of the application.Based on the embodiment party in the application
Formula, every other embodiment obtained by those of ordinary skill in the art without making creative efforts, all belongs to
In the range of the application protection.
The various abbreviations that use below or write a Chinese character in simplified form respectively indicate.
TSV English spelling is " Through Silicon Via ", and the Chinese meaning is through silicon via (across the channel of silicon wafer).
TSVs indicates a plurality of through silicon via (across the channel of silicon wafer).
GS-TSV:(Ground-Signal TSV)-signal through-silicon via structure (channel).
Q3D:(Q3D Extractor) it a kind of high performance is mentioned for the modeling of arbitrary structures 3D/2D passive device and SPICE
The quasi-electrostatic field simulator taken.
SABER: simulation software (software is a eda software of Synopsys company, the U.S., can do system integration project,
Module level emulation and device level emulation are mainly used for mixed signal, hybrid technology design and simulating, verifying).
ADS:(Advanced Design System) i.e. Advanced Design System is a high frequency of agilent company research and development
Mixed signal Electronic Design software, it is able to achieve system, circuit, the emulation of full 3 D electromagnetic field and verifying, supports in high frequency, high speed
The design and simulation platform of collaborative design is carried out by integrated circuit, encapsulation and circuit board in.
HFSS:(High Frequency Simulator Structure) it is used for the ANSYS of radio frequency and wireless design
HFSS all-wave three-dimensional electromagnetic field stimulation device is interconnected for designing with artificial antenna, aerial array, radio frequency or microwave components, high speed
The high-frequency electronics product such as line, filter, connector, integrated antenna package and printed circuit board.
RLCG: resistance-inductance-conductance-capacitance parameter can construct RLGC model.
S parameter: refer to the relationship of the incidence wave and back wave of transmission line between the two, alternatively referred to as scattering parameter, be to retouch line
Property electrical network variation stable state electric signal excitation when electrical behavior.It is an important parameter of gauge signal transmission,
Mainly use S11Return loss and S21Insertion loss.
Ropen: equivalent empty resistance.
Cvoid: equivalent empty capacitor.
Rshort: equivalent pin hole short-circuit impedance.
In order to more clearly introduce this method, now by taking empty failure GS-TSV electric test model as shown in Figure 1 as an example,
The present invention is described in detail.GS-TSV structure is selected, test access is 15 μm by radius, high 5 μm of non-contact spy disk electricity
Appearance is coupled to circuit under test terminal, and it is as shown in Figure 2 to visit disk shape.Using the TSV size of a set of fixation, it is electrical to calculate fault-free
Model parameter.Then the number of tones i for choosing multi-tone signal, can determine that the amplitude model of each sound because only that number of tones has been determined
It encloses.Here circuit voltage is set to 5V, chooses 10 sounds, then the amplitude of each sound is then no more than 0.5V, so the value of Ai
0 to arbitrarily being chosen between 0.5V, pseudo-random number generator may be used herein and obtain value.Do not consider initial phase, enabling fundamental frequency is f0=
1GHz, Δ f=0.2GHz, then the π Δ of Δ ω=2 f.The multi-tone signal of generation is added into additive white Gaussian noise, using low noise
Acoustic amplifier amplifies certain multiple, then is modulated with the radiofrequency signal of 200MHz.
Specifically, using following steps:
1) there are the TSVs equivalent-circuit models of physics structure failure for foundation.Equivalent electricity is carried out by object of GS-TSV structure
Gas modeling, then analyzes the formation mechenism of each physical fault and establishes corresponding fault equivalence circuit model, exports equivalent circuit
The formula of mathematical of each parameter, then the correctness of each model is verified with Q3D simulation modeling result, it is finally that GS-TSV is equivalent
Electrical model is combined with fault model, obtains the GS-TSV equivalent-circuit model there are physics structure failure.
2) generation of test and excitation signal is synthesized.Design generation one meets survey in SABER and ADS simulation Software Platform
The multi-tone signal of examination demand, and additive white Gaussian noise is added on multi-tone signal, then by the signal through low-noise amplifier
Amplification, then be modulated with the radio-frequency carrier signal of a same frequency, generate composite test pumping signal.Answering in the present embodiment
It is as shown in Figure 3 to close test and excitation signal.
3) theoretical using crosstalk couplings, with TSV for aggrieved carrier, spy disk is signal to attack carrier, establishes and is based on capacitor coupling
The non-contact testing structure of conjunction.Disk size is probed by HFSS, visits disk and different the inserting under higher frequency of pad pitch
Enter loss and transfer impedance, further determines that and visit dish structure and its optimum signal transmission range between pad.Then it derives
The equivalent circuit of the related lumped parameter RLCG of non-contact testing structure out, and this is verified through HFSS three-dimensional artificial modeling result
The correctness of model.
4) multitone jitter test is carried out to fault-free GS-TSV circuit.Setup test circuit passes through synthesis test and excitation
Non-contact testing structure is applied to trouble-free GS-TSV equivalent circuit and carries out emulation testing, then is measured by envelope detector defeated
The root-mean-square value and crest voltage of outlet record test result, calculate peak-to-average force ratio.In the present embodiment, to fault-free GS-TSV electricity
The waveform that road carries out multitone jitter test is as shown in Figure 4.
5) corresponding emulation testing is carried out to faulty GS-TSV equivalent circuit, records test result, and it is equal to calculate peak
Than, then change the factors such as the type of physical structure failure, characteristic size and carry out emulation testing again and record peak-to-average force ratio, arrange data
And draw out the relational graph of peak-to-average force ratio Yu TSV fault signature size.
6) test result compares, and test result when by TSV with and without failure compares and calculate peak-to-average force ratio difference, when
The absolute value of difference illustrates TSV there are failure when being greater than 0.1, and judge fault type and greatly according to the difference degree of peak-to-average force ratio
It is small, to realize the detection to failure.The changing rule between the physical damnification factor of these failures and peak-to-average force ratio is analyzed, is continued
Optimization composite excitation signal simultaneously carries out dependence test, improves the resolution of TSV fault detection.
7) the multitone synthesis test and excitation signal used in step 2 is generated with actual hardware circuit.Utilize any wave
Shape generator generates required multi-tone signal, and adds white Gaussian noise, amplifies using low-noise amplifier to it.Make
Radio-frequency carrier signal is generated with radio-frequency signal generator, and multi-tone signal is modulated with treated, it is multiple to obtain multitone shake
Close test signal.
8) practical TSVs to be measured is connected by contactless structure with the pin of test platform, and multitone is shaken compound
Test signal is applied to the non-contact spy disk of test platform, obtains the peak value and root mean square of output end by envelope detector measurement
Threshold voltage calculates to obtain peak-to-average force ratio.
9) actually detected value and the peak-to-average ratio in the relational graph of peak-to-average force ratio-TSV fault signature size are compared, according to
Peak-to-average force ratio difference determines that tested TSVs whether there is failure and there are which kind of failures.
There is cavity in the not completely filled copper post conductor that will lead to the center TSV of copper in the plating process.In metal deposit
When the cavity that generates may be considered close to open-circuit fault.Later wafer be thinned and stacking process in, due to mechanical stress
And the effect of fuel factor, the cavity generated before will lead to since filling is uneven become larger, and complete open-circuit fault occur
Appearance so that failure TSV becomes floating electrically.The effective coverage that cavity in TSV center conductor transmits signal
Reduce, form a high resistance pathways Ropen, bring additional power consumption, simultaneous transmission of signals decaying increases, and influences the transmission of TSV
Performance.Due to the appearance in cavity, the copper medium of air dielectric and surrounding can form capacitor Cvoid, to sum up therefore can be by empty failure
Equivalent Electrical Modeling is the parallel connection of resistance and capacitor.Fault model and GS-TSV equivalent-circuit model are integrated as shown in Figure 1, utilizing
Above-mentioned synthesis test and excitation signal motivates the cavity TSVs fault equivalence circuit by non-contact spy disk, measures and records peak-to-average force ratio.
Here cavity is modeled as a radius rvoid=k*rTSVSphere, i.e., the size in cavity is corresponded into the percentage of TSV radius
Than changing the size in cavity by changing k, the event of corresponding size being calculated in the case where considering high frequency skin effect
Barrier value, is tested in this, as fault point.In the present embodiment, to the defeated of the GS-TSV of four kinds of empty failures (k takes 25-90%)
Response wave shape is as shown in Figure 5 out.Every change primary fault value emulates primary test circuit, obtains the output under different faults value
As a result peak-to-average force ratio, arrange and calculate PAR difference between different empty failures and fault-free is as shown in Figure 6.With empty ruler
Very little increase, TSV copper column missing is more serious, and the equivalent capacity that offresistance increases cavity also increases with it, and overall impedance increases
Add, so that the signal phase shift of circuit output end changes, the rms voltage of output voltage is just had significantly for this variation
Variation.The peak-to-average force ratio of equivalent fault circuit shows a increasing trend with the increase in cavity.By peak-to-average force ratio difference-cavity fault relationship figure
Know that peak-to-average force ratio just has obvious variation when the k of empty failure is 20%.And k corresponding pore size when being 20%
Radius is equal to 2 μm of cavity.Therefore multitone jitter test is 2 μm for the distinguishable minimum dimension of test of the cavity TSV failure.
Since the insulating layer of TSV is extremely thin, technological level is limited in addition, therefore it is easy to appear failures.Silica is exhausted
Edge layer then will lead to and short circuit occur between TSV and silicon substrate, a low impedance path occur, flow through the electricity of TSV if there is needle pore defect
Stream will flow into silicon substrate along this low impedance path, the leakage of electric current occur.Such case will lead to the signal of chip chamber
Transmission decays, if pin hole failure is serious, it is likely that so that the attenuation degree of signal is excessive so that Signal Fail.Pin hole
Defect increases a low resistance path by TSV copper column to silicon substrate, is equivalent to short trouble, can be modeled as TSV and silicon substrate
The size of variable impedance Rshort between plate, resistance value characterize the degree of short circuit of TSV.Here pin hole is modeled as annulus song
Face, wherein h, ω respectively indicate radian corresponding to the height and its arc length of pin hole.Multitone shake composite excitation signal is passed through
Contactless spy disk is applied to TSVs pin hole fault equivalence circuit.The size for changing pin hole, obtains corresponding fault value.Every change
Primary fault value emulates primary test circuit, obtains the output result peak-to-average force ratio under different faults value, as shown in Figure 7.Insulating layer
Impedance is generally at tens of megaohms or more, so that the buffer action of insulating layer reduces, isolated impedance value reduces for the appearance of pin hole.With
The reduction of insulating layer resistance, what the electric current for flowing through TSV will be more leaks into silicon substrate.The TSV pin hole unlike cavity
The peak-to-average force ratio of fault equivalence circuit reduces as pin hole increases.The pin hole failure tested using multitone jitter test method is small
To arriving several megohms, the height of corresponding pin hole failure is 3 μm, and arc length is 2 μm.
Generally speaking, based on multitone shake complex incentive non-contact type test method can by test index peak-to-average force ratio come
Out of order type and size are diagnosed, this method provides presence, position and geometrical characteristic in relation to failure as much as possible
Infomation detection, improve in deep submicron structures small fault test sensitivity, improve physical structure fault identification
Accuracy.
Claims (8)
1. a kind of TSV failure non-contact type test method based on complex incentive, which comprises the following steps:
S1, establish there are multiple through silicon vias of physics structure failure (across the channel of silicon wafer, Through Silicon Vias,
TSVs) equivalent-circuit model and the correctness of circuit model is verified；
S2, synthesis composite test pumping signal；
S3, using crosstalk couplings theory, with through silicon via (TSV) for aggrieved carrier, spys disk is signal to attack carrier, is established based on electric
Hold the non-contact testing structure of coupling；
S4, to trouble-free multiple through silicon via (across the channel of silicon wafer, Through Silicon Vias, TSVs) equivalent circuits
It carries out multitone and shakes emulation testing；
S5, to faulty multiple through silicon via (across the channel of silicon wafer, Through Silicon Vias, TSVs) equivalent circuits
Corresponding emulation testing is carried out, records test result, and calculate peak-to-average force ratio, then change the type of physical structure failure, feature ruler
Very little factor carries out emulation testing again and records peak-to-average force ratio, arranges data and draws out peak-to-average force ratio and-through silicon via fault signature size
Relational graph；
S6, test result comparison, test result when by through silicon via (TSV) with and without failure compares and to calculate peak-to-average force ratio poor
It is worth, illustrating through silicon via (TSV) when the absolute value of difference is greater than 0.1, there are failures, and are judged according to the difference degree of peak-to-average force ratio
Fault type and size, to realize the detection to failure；
S7, the multitone synthesis test and excitation signal used in step 2 is generated with actual hardware circuit, utilize random waveform
Generator generates required multi-tone signal, and adds white Gaussian noise, amplifies using low-noise amplifier to it, uses
Radio-frequency signal generator generates the radio-frequency carrier signal of identical frequency, and multi-tone signal is modulated with treated, is obtained more
Sound shakes composite test signal；
S8, practical through silicon via (TSV) to be measured is connected by contactless structure with the pin of test platform, and multitone is shaken
Composite test signal is applied to the non-contact spy disk of test platform, by envelope detector measurement obtain output end peak value and
Root threshold voltage calculates to obtain peak-to-average force ratio；
S9, actually detected value and the peak-to-average ratio in the relational graph of peak-to-average force ratio-TSV fault signature size are compared, according to peak
Tested through silicon via (TSV) is determined with the presence or absence of failure than difference and there are which kind of failures.
2. according to the method described in claim 1, it is characterized by:
Physical structure failure described in step S1 includes cavity, pin hole, crackle and dislocation fault type.
3. according to the method described in claim 1, it is characterized by:
Foundation described in step S1 includes the following steps: there are the equivalent-circuit model of physics structure failure
S111, with multiple through silicon vias (Through Silicon Vias, TSVs) structure be object, establish multiple through silicon vias
(Through Silicon Vias, TSVs) equivalent electrical model, and extract RLGC(resistance-inductance-conductance-capacitance parameter)
The analytic equation of element；
S112, the formation mechenism for analyzing each physical structure failure simultaneously establish corresponding fault equivalence circuit model；
S113, each fault equivalence electricity is exported according to the physical structure failure with design parameter (such as physical size and material properties)
The formula of mathematical of circuit component parameter；
S114, by multiple through silicon vias (Through Silicon Vias, TSVs) equivalent electrical model and fault equivalence circuit mould
Type combines to obtain that there are multiple through silicon vias of physics structure failure (Through Silicon Vias, TSVs) equivalent circuit moulds
Type.；
4. according to the method described in claim 1, it is characterized by:
The correctness of circuit model is verified described in step S1, comprising the following steps:
S111, S parameter is carried out to multiple through silicon vias (Through Silicon Vias, TSVs) electrical model in ADS software
Simulation analysis；
S112, the relevant more of extraction are verified with all-wave three-dimensional electromagnetic field stimulation device (HFSS or Q3D) simulation modeling result
The correctness of a through silicon via (Through Silicon Vias, TSVs) circuit model compares the S parameter of the two, when its phase
When to error less than 3%, show that verifying is correct.
5. according to the method described in claim 1, it is characterized by:
Composite excitation signal described in step S2 is that design generation one meets the more of testing requirement in simulation Software Platform first
Then and by additive white Gaussian noise sound signal is added on multi-tone signal, then the signal is amplified through low-noise amplifier, then
It is modulated with the radio-frequency carrier signal of a same frequency, generates composite test pumping signal.
6. according to the method described in claim 1, it is characterized by:
Step S3 further include: the difference that disk size is visited by all-wave three-dimensional electromagnetic field stimulation device (HFSS), visits disk and pad pitch
Insertion loss and transfer impedance under higher frequency further determine that visiting dish structure and its optimum signal between pad passes
Defeated distance, then derive the related resistors of non-contact testing structure, inductance, conductance, capacitor (RLCG) lumped parameter it is equivalent
Circuit, and verify through all-wave three-dimensional electromagnetic field stimulation device (HFSS) three-dimensional artificial modeling result the correctness of the model.
7. according to the method described in claim 1, it is characterized by:
Step S4 further include: synthesis test and excitation is applied to trouble-free through silicon via (TSV) etc. by non-contact testing structure
It imitates circuit and carries out emulation testing, then measure the root-mean-square value and crest voltage of output end by envelope detector, record test knot
Fruit calculates peak-to-average force ratio.
8. according to the method described in claim 1, it is characterized by:
Step S6 further includes the changing rule analyzed between the physical damnification factor and peak-to-average force ratio of these failures, continues to optimize compound
Pumping signal simultaneously carries out dependence test, improves the resolution of through silicon via (TSV) fault detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910095503.4A CN110018407A (en) | 2019-01-31 | 2019-01-31 | TSV failure non-contact type test method based on complex incentive |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910095503.4A CN110018407A (en) | 2019-01-31 | 2019-01-31 | TSV failure non-contact type test method based on complex incentive |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110018407A true CN110018407A (en) | 2019-07-16 |
Family
ID=67188962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910095503.4A Pending CN110018407A (en) | 2019-01-31 | 2019-01-31 | TSV failure non-contact type test method based on complex incentive |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110018407A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112001059A (en) * | 2020-07-10 | 2020-11-27 | 中国电力科学研究院有限公司 | Flexible direct current converter valve sub-module broadband model establishing method and device |
| CN113466668A (en) * | 2021-07-09 | 2021-10-01 | 哈尔滨工业大学 | Interlayer dielectric cavity fault test structure and test method based on switched capacitor |
| CN114641826A (en) * | 2019-09-03 | 2022-06-17 | 代尔夫特技术大学 | Device aware testing for memory cells |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645421A (en) * | 2013-12-13 | 2014-03-19 | 桂林电子科技大学 | High-speed interconnection pathway crosstalk fault test method |
| CN108376653A (en) * | 2017-01-31 | 2018-08-07 | 意法半导体股份有限公司 | For silicon hole（TSV）Electric test system and method |
-
2019
- 2019-01-31 CN CN201910095503.4A patent/CN110018407A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645421A (en) * | 2013-12-13 | 2014-03-19 | 桂林电子科技大学 | High-speed interconnection pathway crosstalk fault test method |
| CN108376653A (en) * | 2017-01-31 | 2018-08-07 | 意法半导体股份有限公司 | For silicon hole（TSV）Electric test system and method |
Non-Patent Citations (2)
| Title |
|---|
| IFTEKHAR IBNE BASITH等: "Contactless Test Access Mechanism for TSV-Based", 《IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT》 * |
| JOURNAL OF ADVANCED COMPUTATIONAL INTELLIGENCE AND INTELLIGENT I: "TSV Manufacturing Fault Modeling and Diagnosis Based on Multi-Tone Dither", 《JOURNAL OF ADVANCED COMPUTATIONAL INTELLIGENCE AND INTELLIGENT INFORMATICS》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114641826A (en) * | 2019-09-03 | 2022-06-17 | 代尔夫特技术大学 | Device aware testing for memory cells |
| CN112001059A (en) * | 2020-07-10 | 2020-11-27 | 中国电力科学研究院有限公司 | Flexible direct current converter valve sub-module broadband model establishing method and device |
| CN112001059B (en) * | 2020-07-10 | 2024-04-09 | 中国电力科学研究院有限公司 | Method and device for establishing broadband model of flexible direct current converter valve submodule |
| CN113466668A (en) * | 2021-07-09 | 2021-10-01 | 哈尔滨工业大学 | Interlayer dielectric cavity fault test structure and test method based on switched capacitor |
| CN113466668B (en) * | 2021-07-09 | 2024-05-17 | 哈尔滨工业大学 | Interlayer dielectric cavity fault test structure and test method based on switch capacitor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106920795B (en) | Memory construction and preparation method thereof, the test method of memory | |
| CN110018407A (en) | TSV failure non-contact type test method based on complex incentive | |
| US6822438B2 (en) | Apparatus for measuring parasitic capacitance and inductance of I/O leads on electrical component using a network analyzer | |
| Gong et al. | TSV extracted equivalent circuit model and an on-chip test solution | |
| Kannan et al. | Fault modeling and multi-tone dither scheme for testing 3D TSV defects | |
| CN107345986A (en) | A kind of impedance detecting method of De- embedding mode | |
| CN101501510A (en) | Apparatus and method of testing singulated dies | |
| CN103839921B (en) | The radio frequency test structure of silicon through hole and parasitic extracting method | |
| CN103594453B (en) | Integrated circuit medium punctures test structure and the method for testing thereof of fail-safe analysis | |
| CN104205639B (en) | The semiconductor device that can be reconstructed | |
| Sharma et al. | VLSI interconnects and their testing: prospects and challenges ahead | |
| Yin et al. | Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias | |
| US6781218B1 (en) | Method and apparatus for accessing internal nodes of an integrated circuit using IC package substrate | |
| Basith et al. | Contactless test access mechanism for TSV-based 3-D ICs utilizing capacitive coupling | |
| CN107729581B (en) | Method for designing chip test socket structure based on FEA simulation and application thereof | |
| Pannala et al. | Parameter extraction and electrical characterization of high density connector using time domain measurements | |
| Qian et al. | Electrical analysis of EMIB packages | |
| Park et al. | High-Frequency Electrical Characterization of a New Coaxial Silicone Rubber Socket for High-Bandwidth and High-Density Package Test | |
| Shang et al. | TSV manufacturing fault modeling and diagnosis based on multi-tone dither | |
| Shang et al. | TSV fault contactless testing method based on group delay | |
| Kim et al. | Non-contact wafer-level TSV connectivity test methodology using magnetic coupling | |
| Wang et al. | High bandwidth application with wide I/O memory on 2.5 D-IC silicon interposer | |
| Kim et al. | Signal integrity design and analysis of a multilayer test interposer for LPDDR4 memory test with silicone rubber-based sheet contact | |
| Wang et al. | Modeling optimization of test patterns used in de-embedding method for through silicon via (TSV) measurement in silicon interposer | |
| Kim et al. | Design and analysis of silicone rubber-based TERAPOSER for LPDDR4 memory test |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190716 |
|
| RJ01 | Rejection of invention patent application after publication |