CN110010497B - System-in-package process of side-radiating radio frequency chip - Google Patents
System-in-package process of side-radiating radio frequency chip Download PDFInfo
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- CN110010497B CN110010497B CN201811176820.0A CN201811176820A CN110010497B CN 110010497 B CN110010497 B CN 110010497B CN 201811176820 A CN201811176820 A CN 201811176820A CN 110010497 B CN110010497 B CN 110010497B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a side-radiating radio frequency chip system-in-package process, which comprises the following steps: 101) a base processing step, 102) a cover plate processing step, 103) an intermediate layer processing step, and 104) a packaging step; the invention provides a side-radiating radio frequency chip system-in-package process which does not occupy the area of a substrate or a PCB and can increase the radiating capacity of a system.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a side-radiating radio frequency chip system-in-package process.
Background
The rapid development of electronic products is the main driving force of the evolution of the current packaging technology, and miniaturization, high density, high frequency, high speed, high performance, high reliability and low cost are the mainstream development directions of advanced packaging, wherein system-in-package is one of the most important and most potential technologies for meeting the high-density system integration.
In various system-in-package (SIP) packages, a silicon interposer is used as a substrate technology of the SIP package, which provides the shortest connection distance, the smallest pad size and the smallest center-to-center distance for the chip-to-chip and the chip-to-PCB. Advantages of silicon interposer technology over other interconnect technologies, such as wire bonding, include: better electrical performance, higher bandwidth, higher density, smaller size, lighter weight.
However, for a larger size radio frequency chip, a more rigorous heat dissipation structure is required for the silicon interposer embedding process, and a copper block is generally arranged below the silicon interposer module and is in contact with a copper-inlaid structure on a substrate or a PCB, so that the area on the substrate or the PCB is wasted.
Disclosure of Invention
The invention overcomes the defects of the prior art, and provides the side-radiating radio frequency chip system-in-package process which does not occupy the area of a substrate or a PCB and can increase the radiating capacity of a system.
The technical scheme of the invention is as follows:
a side-radiating radio frequency chip system-in-package process specifically comprises the following steps:
101) a base treatment step: manufacturing a base pit on the upper surface of a base by a dry etching method, wherein the base pit is in a cubic shape, an inverted trapezoid shape, a cylindrical shape or a hemispherical shape, the size range of the base pit is 10um to 10000um, and the size of the base pit comprises the cubic shape, the length, the width and the height of the inverted trapezoid shape or the cylindrical shape, and the diameter or the height of the hemispherical shape;
forming an insulating layer on the upper surface of the base by depositing silicon oxide or silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer ranges from 10nm to 100um, manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be a layer or multiple layers, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is electroplated to fill the pits with copper metal, copper is densified at the temperature of 200-500 ℃, and only the copper filling of the pits of the base is left on the lower surface of the base through a CMP process;
manufacturing TSV holes on the upper surface of the base through photoetching and etching processes, wherein the diameter range of the TSV holes is 1um to 1000um, and the depth of the TSV holes is 10um to 1000 um; forming an insulating layer on the upper surface of the base by depositing silicon oxide or silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness range of the seed layer is 1nm to 100um, the structure of the seed layer can be one layer or multiple layers, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is electroplated to fill the TSV holes with copper metal, the copper is densified at the temperature of 200-500 ℃, and only the copper filled in the TSV holes is left on the upper surface of the base through a CMP process;
cutting along the center line of the pit, and removing the side of the base, which is not provided with the TSV;
manufacturing an RDL on the upper surface of the base, wherein the process comprises the steps of manufacturing an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, the insulating layer is made of silicon oxide or silicon nitride, windowing is performed through photoetching and dry etching processes, the RDL is connected with copper filling of the TSV hole, and the RDL is manufactured on the surface of the base through photoetching and electroplating processes and comprises a bonding pad with wiring and bonding functions and a metal block for adhering a chip; the metal of the wire is one or more of copper, aluminum, nickel, silver, gold and tin, the structure of the wire is one layer or a plurality of layers, and the thickness range of the wire is 10nm to 1000 um;
manufacturing bonding metal on the upper surface of the base through photoetching and electroplating processes to form a bonding pad, wherein the height range of the bonding pad is 10nm to 1000um, the bonding pad adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the structure of the bonding pad is one layer or multiple layers; the bonding pad and the trace are positioned on the same surface; wherein the RDL is interconnected with the exposed end of the pit;
thinning the lower surface of the base, wherein the thinned thickness is 100um to 700 um;
through photoetching and electroplating processes, manufacturing a heat dissipation copper column on the lower surface of the base, wherein the heat dissipation copper column is interconnected with the lower end of the TSV hole, the diameter of the heat dissipation copper column is 10-1000 um, the heat dissipation copper column is made of one or more of copper, aluminum, nickel, silver, gold and tin, the structure of the heat dissipation copper column is one or more layers, and the diameter range of the heat dissipation copper column is 10-1000 um;
arranging a heat dissipation copper block at one end of the heat dissipation copper column far away from the base through a welding process, wherein the thickness of the copper block is between 10um and 1000 um;
102) a cover plate processing step: processing the cover plate by the same processing method as the step 101), generating a cover plate pit, a cover plate TSV hole and a cover plate RDL, thinning the lower surface of the cover plate to expose the tail end of the cover plate TSV hole, arranging a heat dissipation copper column at the tail end of the cover plate TSV hole, and arranging a heat dissipation copper block at the top end of the heat dissipation copper column through a welding process;
103) and (3) intermediate layer treatment: generating an intermediate layer bonding pad and an intermediate layer groove by using the intermediate layer in the same processing method as the step 101), thinning the other surface of the intermediate layer to expose the bottom of the groove, and manufacturing a bonding pad on the other surface of the thinned intermediate layer;
104) and (3) packaging: bonding the middle layer and the base together through a wafer-level process, welding the functional chip on a bonding pad of the base, and interconnecting the functional chip and the base silicon wafer through a bumping interconnection or routing process; and bonding the cover plate and the middle layer through a wafer-level process, interconnecting soldering tin on the functional chip with the cover plate, cutting to obtain a single module, and interconnecting the single module with the substrate through the base pit and the cover plate pit.
Furthermore, the base and the cover plate adopt one of the size specifications of 4, 6, 8 and 12 inches, the thickness range is 200um to 2000um, and silicon chips, glass, quartz, silicon carbide, aluminum oxide, epoxy resin or polyurethane are adopted.
Furthermore, the RDL surfaces of the upper surface and the lower surface of the carrier plate are covered with insulating layers, the bonding pad is exposed by windowing on the insulating layers, and the diameter of the windowing of the bonding pad is 10um to 10000 um.
Furthermore, the thinning method comprises the steps of grinding, wet etching and dry etching, so that the copper column is exposed.
Compared with the prior art, the invention has the advantages that: the side wall of the system-in-package structure is provided with the heat dissipation structure, the heat dissipation structure comprises the copper columns and the heat dissipation copper blocks, heat exchange can be carried out between the heat dissipation structure and air, the area of the substrate or the PCB is not occupied, and the heat dissipation capacity of the system can be improved.
Drawings
FIG. 1 is a view of the base structure of the present invention;
FIG. 2 is a block diagram of the preliminary process of FIG. 1 according to the present invention;
FIG. 3 is a structural diagram of the base of FIG. 2 with heat dissipating copper pillars in accordance with the present invention;
FIG. 4 is a structural diagram of the base heat dissipation copper block of FIG. 3 according to the present invention;
FIG. 5 is a block diagram of the cover plate of the present invention;
FIG. 6 is a structural diagram of an intermediate layer of the present invention;
FIG. 7 is a block diagram of the bonding of an interlayer and a submount of the present invention;
fig. 8 is a structural view of the present invention.
The labels in the figure are: the base plate comprises a base plate 101, a base plate RDL102, a base plate TSV hole 103, a base plate pit 104, a base plate heat dissipation copper column 105, a base plate heat dissipation copper block 106, a cover plate 201, a cover plate heat dissipation copper block 202, a cover plate heat dissipation copper column 203 and a cover plate pit 204.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1 to 8, in the system-in-package process of a side-radiating rf chip, the base 101, the intermediate layer, and the cover plate 201 have the same size specification, all have one size specification of 4, 6, 8, and 12 inches, have a thickness ranging from 200um to 2000um, are generally silicon wafers, and further include inorganic materials such as glass, quartz, silicon carbide, and alumina, or organic materials such as epoxy resin and polyurethane, and have a main function of providing a supporting function. The specific treatment comprises the following steps:
101) the base 101 processing step: a pedestal pit 104, pedestal TSV hole 103 and pedestal RDL102 are fabricated in the surface of pedestal 101. And thinning the back of the silicon chip to expose the tail end of the TSV hole 103 of the base, and continuously manufacturing a base heat dissipation copper column 105 at the tail end of the TSV hole 103 of the base. And a base heat dissipation copper block 106 is arranged at the top end of the base heat dissipation copper column 105 through a welding process.
The base pit 104 is manufactured on the upper surface of the base 101 through a dry etching method, the base pit 104 is cubic, inverted trapezoidal, cylindrical or hemispherical, the size range of the base pit 104 is 10um to 10000um, and the size of the base pit includes the cubic shape, the length, the width and the height of the inverted trapezoidal shape or the cylindrical shape, and the diameter or the height of the hemispherical shape.
An insulating layer is formed on the upper surface of the base 101 through silicon oxide or silicon nitride deposition or direct thermal oxidation, the thickness of the insulating layer ranges from 10nm to 100um, a seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be of one layer or multiple layers, and the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Copper is filled into the pits by electroplating copper, the copper is densified at a temperature of 200 to 500 c, and the lower surface of the base 101 is left filled with copper only in the pits 104 of the base by a CMP process.
The base TSV hole 103 is manufactured on the upper surface of the base 101 through photoetching and etching processes, the diameter range of the base TSV hole 103 is 1um to 1000um, and the depth of the base TSV hole 103 is 10um to 1000 um. An insulating layer is formed on the upper surface of the base 101 by depositing silicon oxide or silicon nitride or direct thermal oxidation, and the thickness of the insulating layer ranges from 10nm to 100 um. The seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be of one layer or multiple layers, and the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Copper is electroplated to fill the TSV hole with copper metal, the copper is densified at a temperature of 200 to 500 ℃, and the copper filling of only the TSV hole remains on the upper surface of the base 101 through a CMP process. The insulating layer on the upper surface of the base 101 can be removed by a dry etching process or a wet etching process. An insulating layer may also remain on the upper surface of the base 101.
And cutting along the central line of the base pit 104, and removing the side of the base 101 not provided with the base TSV hole 103 for welding standby.
The base RDL102 is manufactured on the upper surface of the base 101, the manufacturing process comprises the steps of manufacturing an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, the insulating layer is made of silicon oxide or silicon nitride, windowing is conducted through the photoetching and dry etching processes, the RDL is connected with copper filling of the TSV hole, the base RDL102 is manufactured on the surface of the base 101 through the photoetching and electroplating processes, and the base RDL102 comprises a bonding pad with wiring and bonding functions and a metal block for pasting a chip. The metal of the wire adopts one or more of copper, aluminum, nickel, silver, gold and tin, the structure of the wire is one layer or a plurality of layers, and the thickness range of the wire is 10nm to 1000 um.
An insulating layer may be further covered on the surface of the pedestal RDL102, and a window may be formed in the insulating layer to expose the pad. The pad windowing diameter is 10um to 10000 um.
A bonding metal is manufactured on the upper surface of the base 101 through photoetching and electroplating processes to form a bonding pad, the height range of the bonding pad is 10nm to 1000um, the bonding pad adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the structure of the bonding pad is one layer or multiple layers. Here the pads and traces are on the same side. Wherein the RDL interconnects the exposed ends of the pits.
The thickness of attenuate 101 lower surface, after the attenuate is at 100um to 700 um. The thinning method comprises the steps of grinding, wet etching and dry etching, so that the copper filling of the TSV hole is exposed.
Through photoetching and electroplating process, base heat dissipation copper post 105 is made on the lower surface of base 101, base heat dissipation copper post 105 is interconnected with TSV hole lower extreme, base heat dissipation copper post 105 diameter 10um to 1000um, base heat dissipation copper post 105 adopts one or more in copper, aluminium, nickel, silver, gold, tin, base heat dissipation copper post 105 self structure adopts one deck or multilayer, and its diameter scope is between 10nm to 1000 um.
The base heat dissipation copper block 106 is arranged at one end, far away from the base 101, of the base heat dissipation copper column 105 through a welding process, and can be glued or eutectic bonded. The thickness of the base heat dissipation copper block 106 is between 10um and 1000 um.
102) The cover plate 201 processing step: and processing the cover plate 201 by the same processing method as the step 101), generating a cover plate pit 204, a cover plate TSV hole and a cover plate RDL, thinning the lower surface of the cover plate 201 to expose the tail end of the cover plate TSV hole, arranging a heat dissipation copper column at the tail end of the cover plate TSV hole, and arranging a heat dissipation copper block at the top end of the heat dissipation copper column through a welding process.
Specifically, as shown in fig. 5, a cover plate pit 204 is formed on the silicon wafer surface of the cover plate 201 by a dry etching method, and the cover plate pit 204 may be a cube, an inverted trapezoid, a cylinder, or a hemisphere. The size range is 10um to 10000um, and the size includes the length, width and height of a cube, an inverted trapezoid or the diameter or height of a cylinder, and a hemisphere.
An insulating layer of silicon oxide or silicon nitride is deposited on the upper surface of the cover plate 201, or directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um. A seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation plating, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
Copper is densified by electroplating copper to fill the cap recess 204 with copper and densifying at a temperature of 200 to 500 degrees. The copper CMP process removes the copper from the surface of the cap plate 201, leaving only the copper fill on the surface of the cap plate 201. The insulating layer on the upper surface of the cover plate 201 can be removed by a dry etching or wet etching process. The insulating layer on the upper surface of the cap plate 201 may also remain.
Through photoetching and etching processes, cover plate TSV holes are manufactured in the surface of a silicon wafer, the diameter range of the cover plate TSV holes is 1um to 1000um, and the depth of the cover plate TSV holes is 10um to 1000 um. An insulating layer of silicon oxide or silicon nitride is deposited over the cover plate 201, or is directly thermally oxidized, with a thickness in the range of 10nm to 100 um. A seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation plating, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
Copper is filled in the TSV by electroplating copper, and densification is performed at a temperature of 200 to 500 ℃ to make the copper denser. The copper CMP process removes copper from the surface of the silicon wafer, leaving only copper on the surface of the cover plate 201 to form copper pillars. The insulating layer on the surface of the cover plate can be removed by a dry etching process or a wet etching process. The cover plate surface insulating layer can also be reserved.
And cutting along the center line of the cover plate pit 204, and removing the side of the cover plate 201 where no cover plate TSV hole is arranged for welding standby.
The cover plate RDL is formed on the surface of the cover plate 201, and the process includes forming an insulating layer, the thickness of the insulating layer is in the range of 10nm to 1000um, and the insulating layer may be made of silicon oxide or silicon nitride. And windowing through photoetching and dry etching processes to connect the RDL of the cover plate with one end of the copper column in the TSV hole of the cover plate. And manufacturing a cover plate RDL on the surface of the silicon wafer through photoetching and electroplating processes. The cover plate RDL comprises bonding pads with routing and bonding functions, and further comprises a metal block for adhering the chip.
An insulating layer may be covered on the surface of the cover plate RDL, and a window may be formed in the insulating layer to expose the pad. The metal of the wire can be copper, aluminum, nickel, silver, gold, tin and other materials, can be a layer or a plurality of layers, and the thickness range of the metal can be 10nm to 1000 um. The pad is windowed to 10um to 10000um diameter.
Bonding metal is manufactured on the surface of the cover plate 201 through photoetching and electroplating processes to form a bonding pad, the height range of the bonding pad is 10nm to 1000um, the metal of the bonding pad can be copper, aluminum, nickel, silver, gold, tin and other materials, can be one layer or multiple layers, and the thickness range of the bonding pad is 10nm to 1000 um.
The bonding pad and the trace are one-sided and located at one exposed end of the copper pillar. Where cover RDL interconnects with the exposed ends of cover recess 204.
And thinning the back of the silicon wafer of the base 101, wherein the thinned thickness is 100um to 700um, and the thinning method comprises the steps of grinding, wet etching and dry etching to expose the copper column.
Through photoetching and electroplating processes, a cover plate heat dissipation copper pillar 203 is manufactured on the back surface of the cover plate 201, and the cover plate heat dissipation copper pillar 203 is interconnected with the tail end of the TSV hole of the cover plate. The diameter of the cover plate heat dissipation copper column 203 is 10um to 1000 um. The metal of the cover plate heat dissipation copper column 203 can be copper, aluminum, nickel, silver, gold, tin and other materials, can be one layer or multiple layers, and the thickness range of the cover plate heat dissipation copper column is 10nm to 1000 um.
The cover plate heat dissipation copper block 202 is arranged at the top end of the cover plate heat dissipation copper column 203 through a welding process, and can be glued or eutectic bonded. The thickness of the cover plate heat dissipation copper block 202 is 10um to 1000 um.
103) And (3) intermediate layer treatment: and (4) generating an intermediate layer bonding pad and an intermediate layer groove by using the intermediate layer in the same processing method as the step 101), thinning the other surface of the intermediate layer to expose the bottom of the groove, and manufacturing the bonding pad of the intermediate layer on the other surface of the thinned intermediate layer.
As shown in fig. 6, an insulating layer is deposited on the surface of the intermediate layer, the insulating layer can be an insulating layer such as silicon oxide or silicon nitride, or can be directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um.
The pad of the middle layer is manufactured on the surface of the insulating layer through photoetching and electroplating processes, the height range of the pad of the middle layer is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be one layer or multiple layers, and the thickness range of the metal can be 10nm to 1000 um.
And manufacturing an intermediate layer groove on the surface of the silicon wafer by photoetching and dry etching processes, wherein the intermediate layer groove can be cubic, inverted trapezoidal or cylindrical or hemispherical. The size range is 10um to 10000um, and the size includes the length, width and height of a cube, an inverted trapezoid or the diameter or height of a cylinder, and a hemisphere.
And thinning the back of the middle layer, wherein the thinned thickness is 100um to 700um, and the thinning method comprises the steps of grinding, wet etching and dry etching to expose the bottom of the groove in the middle layer.
And depositing an insulating layer on the newly thinned surface of the intermediate silicon wafer, wherein the insulating layer can be an insulating layer of silicon oxide or silicon nitride and the like, or can be directly thermally oxidized, and the thickness of the insulating layer ranges from 10nm to 100 um.
The bonding pad on the other surface of the middle layer is manufactured on the surface of the insulating layer through photoetching and electroplating processes, the height range of the bonding pad on the other surface of the middle layer is 10nm to 1000um, the metal can be copper, aluminum, nickel, silver, gold, tin and other materials, can be one layer or multiple layers, and the thickness range of the bonding pad is 10nm to 1000 um.
104) And (3) packaging: and bonding the middle layer and the base 101 together through a wafer-level process, welding the functional chip on a bonding pad of the base 101, and interconnecting the functional chip and the silicon wafer of the base 101 through a bumping interconnection or routing process. And bonding the cover plate 201 and the middle layer through a wafer-level process, interconnecting soldering tin on the functional chip with the cover plate 201, cutting to obtain a single module, and interconnecting the single module with the substrate through the base pit 104 and the cover plate pit 204.
As shown in fig. 7, the intermediate layer and the base 101 are bonded together by a wafer-level process, and the bonding temperature is controlled to be 200 to 600 degrees.
The functional chip is bonded to the pad of the base 101 by a process such as gluing or eutectic bonding. The functional chip and the base 101 are interconnected through a bumping interconnection or a wire bonding process.
And bonding the cover plate 201 on the surface of the middle layer by a wafer-level process, and controlling the bonding temperature to be 200-500 ℃ so that the soldering tin on the functional chip is interconnected with the TSV hole exposure head of the cover plate.
And cutting the stacked wafer into a single module, wherein the cutting position is positioned in the middle of the copper filling position of the pit, the cutting mode can be laser cutting or cutter cutting, the aim is to cut the copper in the pit into two parts, and the side surfaces of the exposed parts are used as welding pads. This cutting may replace the step of cutting the base 101 and cover 201 along the pits.
And interconnecting the side surfaces of the pits on the single module with the substrate through a surface mounting process to obtain the side surface heat dissipation type radio frequency chip system-in-package structure.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (3)
1. A side-radiating radio frequency chip system-in-package process is characterized by comprising the following steps:
101) a base treatment step: manufacturing a base pit on the upper surface of a base by a dry etching method, wherein the base pit is in a cubic shape, an inverted trapezoid shape, a cylindrical shape or a hemispherical shape, the size range of the base pit is 10um to 10000um, and the size of the base pit comprises the cubic shape, the length, the width and the height of the inverted trapezoid shape or the cylindrical shape, and the diameter or the height of the hemispherical shape;
forming an insulating layer on the upper surface of the base by depositing silicon oxide or silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer ranges from 10nm to 100um, manufacturing a seed layer above the insulating layer by a magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be a layer or multiple layers, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is electroplated to fill the base pits with copper metal, the copper is densified at the temperature of 200-500 ℃, and only the copper filled in the base pits is left on the upper surface of the base through a CMP process;
manufacturing a base TSV hole on the upper surface of a base through photoetching and etching processes, wherein the diameter range of the base TSV hole is 1um to 1000um, and the depth of the base TSV hole is 10um to 1000 um; forming an insulating layer on the upper surface of the base by depositing silicon oxide or silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer ranges from 10nm to 100 um; a seed layer is manufactured above the insulating layer through a magnetron sputtering or evaporation process, the thickness range of the seed layer is 1nm to 100um, the seed layer can be a layer or a plurality of layers, and the seed layer adopts one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel;
copper is electroplated to fill the TSV hole of the base with copper metal, the copper is densified at the temperature of 200-500 ℃, and only the copper filled in the TSV hole of the base is left on the upper surface of the base through a CMP process;
cutting along the center line of the pit, and removing the side of the base, which is not provided with the TSV hole of the base;
manufacturing a base RDL on the upper surface of a base, wherein the thickness range of the insulating layer is 10nm to 1000um, the insulating layer is made of silicon oxide or silicon nitride, windowing is performed through photoetching and dry etching processes to enable the RDL to be connected with copper filling of the TSV hole, and the RDL is manufactured on the surface of the base through photoetching and electroplating processes and comprises a wire, a bonding pad with bonding function and a metal block for sticking a chip; the metal of the wire is one or more of copper, aluminum, nickel, silver, gold and tin, the structure of the wire is one layer or a plurality of layers, and the thickness range of the wire is 10nm to 1000 um;
manufacturing bonding metal on the upper surface of the base through photoetching and electroplating processes to form a bonding pad, wherein the height range of the bonding pad is 10nm to 1000um, the bonding pad adopts one or more of copper, aluminum, nickel, silver, gold and tin, and the structure of the bonding pad is one layer or multiple layers; the bonding pad and the trace are positioned on the same surface; wherein the RDL is interconnected with the exposed end of the pit;
thinning the lower surface of the base, wherein the thinned thickness is 100um to 700 um;
through photoetching and electroplating processes, a base heat dissipation copper column is manufactured on the lower surface of the base, the base heat dissipation copper column is interconnected with the lower end of the TSV hole, the diameter of the base heat dissipation copper column is 10-1000 microns, and the base heat dissipation copper column adopts one or more layers;
arranging a base heat dissipation copper block at one end of the heat dissipation copper column far away from the base through a welding process, wherein the thickness of the base heat dissipation copper block is between 10um and 1000 um;
102) a cover plate processing step: processing the cover plate by the same processing method as the step 101), generating a cover plate pit, a cover plate TSV hole and a cover plate RDL, thinning the lower surface of the cover plate to expose the tail end of the cover plate TSV hole, arranging a heat dissipation copper column at the tail end of the cover plate TSV hole, and arranging a heat dissipation copper block at the top end of the heat dissipation copper column through a welding process;
103) and (3) intermediate layer treatment: generating an intermediate layer bonding pad and an intermediate layer groove by the same processing method as the step 101), thinning the other surface of the intermediate layer to expose the bottom of the groove, and manufacturing a bonding pad on the other surface of the thinned intermediate layer;
104) and (3) packaging: bonding the middle layer and the base together through a wafer-level process, welding the functional chip on a bonding pad of the base, and interconnecting the functional chip and the base silicon wafer through a bumping interconnection or routing process; and bonding the cover plate and the middle layer through a wafer-level process, interconnecting soldering tin on the functional chip with the cover plate, cutting to obtain a single module, and interconnecting the single module with the substrate through the base pit and the cover plate pit.
2. The side-cooling radio frequency chip system-in-package process according to claim 1, wherein: the base and the cover plate adopt one size specification of 4, 6, 8 and 12 inches, and the thickness range is 200um to 2000 um.
3. The side-cooling radio frequency chip system-in-package process according to claim 1, wherein: the thinning method comprises the steps of grinding, wet etching and dry etching, so that the copper pillar is exposed.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856296A (en) * | 2012-09-24 | 2013-01-02 | 日月光半导体制造股份有限公司 | Stacked semiconductor package element |
| CN106252241A (en) * | 2016-09-08 | 2016-12-21 | 华进半导体封装先导技术研发中心有限公司 | Chip package sidewall pad or the processing technology of salient point |
| JP2016219641A (en) * | 2015-05-22 | 2016-12-22 | 昭和電工株式会社 | Heat sink and housing for base station |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2004221372A (en) * | 2003-01-16 | 2004-08-05 | Seiko Epson Corp | Semiconductor device, semiconductor module, method of manufacturing both the same and electronic apparatus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856296A (en) * | 2012-09-24 | 2013-01-02 | 日月光半导体制造股份有限公司 | Stacked semiconductor package element |
| JP2016219641A (en) * | 2015-05-22 | 2016-12-22 | 昭和電工株式会社 | Heat sink and housing for base station |
| CN106252241A (en) * | 2016-09-08 | 2016-12-21 | 华进半导体封装先导技术研发中心有限公司 | Chip package sidewall pad or the processing technology of salient point |
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