CN110010497A - A kind of side heat radiating type radio frequency chip system in package technique - Google Patents
A kind of side heat radiating type radio frequency chip system in package technique Download PDFInfo
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- CN110010497A CN110010497A CN201811176820.0A CN201811176820A CN110010497A CN 110010497 A CN110010497 A CN 110010497A CN 201811176820 A CN201811176820 A CN 201811176820A CN 110010497 A CN110010497 A CN 110010497A
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- 238000000034 method Methods 0.000 title claims abstract description 78
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005538 encapsulation Methods 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 113
- 229910052802 copper Inorganic materials 0.000 claims description 113
- 239000010949 copper Substances 0.000 claims description 113
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 44
- 230000017525 heat dissipation Effects 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 28
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 26
- 229910052718 tin Inorganic materials 0.000 claims description 26
- 239000011135 tin Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 23
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 22
- 239000004411 aluminium Substances 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052759 nickel Inorganic materials 0.000 claims description 22
- 229910052709 silver Inorganic materials 0.000 claims description 22
- 239000004332 silver Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 19
- 229910052737 gold Inorganic materials 0.000 claims description 19
- 239000010931 gold Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 238000009713 electroplating Methods 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000000280 densification Methods 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 8
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- 229910052763 palladium Inorganic materials 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 229910052716 thallium Inorganic materials 0.000 claims description 8
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000003672 processing method Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000004814 polyurethane Substances 0.000 claims description 3
- 229920002635 polyurethane Polymers 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 113
- 239000000463 material Substances 0.000 description 7
- 238000004026 adhesive bonding Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of side heat radiating type radio frequency chip system in package technique, include the following steps: 101) pedestal processing step, 102) cover board processing step, 103) intermediate layer handles step, 104) encapsulation step；The present invention provides the area for being both not take up substrate or pcb board, moreover it is possible to increase a kind of side heat radiating type radio frequency chip system in package technique of system radiating ability.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, it is related to a kind of side heat radiating type radio frequency chip system
Grade packaging technology.
Background technique
The fast development of electronic product is the main drive that current encapsulation technology is evolved, and miniaturization, high density, high frequency are high
Speed, high-performance, high reliability and low cost are the mainstream development directions of Advanced Packaging, and wherein system in package, which is most important, is also
It is most potential to meet integrated one of the technology of this high-density systems.
In various system in package, using silicon pinboard as the matrix technique of system in package, for chip to chip
Shortest connection distance, the smallest pad size and center spacing are provided with chip to pcb board.Such as draw with other interconnection techniques
The advantages of line bonding technology is compared, silicon switching plate technique includes: better electric property, higher bandwidth, higher density, more
Small size, lighter weight.
But for the radio frequency chip of larger size, the embedding process requirement of silicon pinboard uses more harsh heat dissipation
Copper billet is usually arranged in structure below silicon switching plate module, and copper billet is with the edge steel structure on substrate or pcb board, waste
Area on substrate or pcb board.
Summary of the invention
The present invention overcomes the deficiencies in the prior art, the area for being both not take up substrate or pcb board is provided, moreover it is possible to increase system
A kind of side heat radiating type radio frequency chip system in package technique for heat-sinking capability of uniting.
Technical scheme is as follows:
A kind of side heat radiating type radio frequency chip system in package technique, specific processing include the following steps:
101) pedestal processing step: pedestal pit is produced by the method for dry etching in base upper surface, pedestal pit is adopted
With cube, inverted trapezoidal, cylinder or hemispherical, pedestal dimple size range is between 10um to 10000um, size herein
Including cube, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height；
Insulating layer, thickness of insulating layer are formed by cvd silicon oxide or silicon nitride or directly thermal oxidation on base upper surface
Range just makes seed between 10nm to 100um, through physical sputtering, magnetron sputtering or evaporation process on the insulating layer
Layer, in 1nm to 100um, this body structure of seed layer is one layer and is also possible to multilayer seed layer thickness range, seed layer use titanium,
One of copper, aluminium, silver, palladium, gold, thallium, tin, nickel are a variety of；
By electro-coppering, make copper metal full of pit, densification copper at a temperature of 200 to 500 degree is made under pedestal by CMP process
Only it is left pedestal pit and fills out copper in surface；
The hole TSV is made in base upper surface by photoetching, etching technics, TSV bore dia range exists in 1um to 1000um, depth
10um to 1000um；Insulating layer is formed by cvd silicon oxide or silicon nitride or directly thermal oxidation in base upper surface, absolutely
Edge layer thickness range is between 10nm to 100um；It is just made on the insulating layer by physical sputtering, magnetron sputtering or evaporation process
Make seed layer, seed layer thickness range is in 1nm to 100um, this body structure of seed layer is one layer and is also possible to multilayer, and seed layer is adopted
With one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or a variety of；
By electro-coppering, make copper metal full of the hole TSV, densification copper at a temperature of 200 to 500 degree is made on pedestal by CMP process
Only it is left TSV hole and fills out copper in surface；
Middle line along pit is cut, and the side in the not set hole TSV of pedestal is removed；
RDL is made in base upper surface, process includes production insulating layer, and thickness of insulating layer range is in 10nm to 1000um, absolutely
Edge layer uses silica or silicon nitride, then is opened a window by photoetching, dry etch process, connects the copper of filling out in the hole RDL with TSV,
RDL is made in susceptor surface by photoetching, electroplating technology again, RDL includes the pad and adhering chip of cabling, key function
Metal block；The metal of cabling uses one of copper, aluminium, nickel, silver, gold, tin or a variety of, this body structure of cabling is one layer or more
Layer, thickness range is between 10nm to 1000um；
Bond wire is made in base upper surface by photoetching, electroplating technology and forms pad, and pad height range is arrived in 10nm
1000um, pad use one of copper, aluminium, nickel, silver, gold, tin or a variety of, this body structure of pad is one or more layers；Herein
Pad and cabling are located at the same face；Wherein RDL is interconnected with pit bared end；
Base lower surface is thinned, the thickness after being thinned is in 100um to 700um；
By photoetching and electroplating technology, in the lower surface of pedestal production heat dissipation copper post, heat dissipation copper post is interconnected with the hole TSV lower end, is dissipated
Hot copper post diameter 10um to 1000um, heat dissipation copper post use one of copper, aluminium, nickel, silver, gold, tin or a variety of, and radiate copper post sheet
Body structure uses one or more layers, and diameter range is between 10nm to 1000um；
By welding procedure heat dissipation copper post far from pedestal one end setting heat dissipation copper billet, copper billet thickness 10um to 1000um it
Between；
102) cover board processing step: cover board is handled by the identical processing method of same step 101), generates cover board pit, cover board
Cover board lower surface is thinned in the hole TSV and cover board RDL, exposes cover board TSV bore end, and radiating copper is arranged in cover board TSV bore end
Column, and heat dissipation copper billet is arranged in radiating copper top end by welding procedure；
103) intermediate layer handles step: by the identical processing method middle layer of same step 101), middle layer pad is generated in
Interbed groove, middle layer another side, which is thinned, exposes bottom portion of groove, makes pad on the another side of the middle layer after being thinned；
104) encapsulation step: middle layer and pedestal are bonded together by wafer scale technique, functional chip is welded on pedestal
Pad on, and by bumping interconnection or routing technique make functional chip with pedestal silicon wafer interconnect；Pass through wafer scale technique
Cover board and Intermediate Layer Bonding, and interconnect the scolding tin on functional chip with cover board, cutting obtains single mould group, by single mould group
It completes to interconnect by pedestal pit and cover board pit and substrate.
Further, pedestal, cover board are arrived using one of 4,6,8,12 cun dimensions, thickness ranges for 200um
2000um, using silicon wafer, glass, quartz, silicon carbide, aluminium oxide, epoxy resin or polyurethane.
Further, the surface RDL of support plate upper and lower surfaces covers insulating layer again, and weldering is exposed in windowing on the insulating layer
Disk, the diameter of pad windowing herein is 10um to 10000um.
Further, thining method includes first then using wet etching with grinding, then with dry etch process, make copper post
Expose.
Advantage is the present invention compared with prior art: the present invention does radiator structure in the side wall of system-in-package structure, should
Radiator structure includes copper post and heat dissipation copper billet, can carry out heat exchange with air, both be not take up the area of substrate or pcb board,
It also can increase system radiating ability.
Detailed description of the invention
Fig. 1 is understructure figure of the invention；
Fig. 2 is Fig. 1 preliminary treatment structure chart of the invention；
Fig. 3 is the structure chart that pedestal heat dissipation copper post is arranged in Fig. 2 of the invention；
Fig. 4 is the structure chart that pedestal heat dissipation copper billet is arranged in Fig. 3 of the invention；
Fig. 5 is the structure chart of cover board of the invention；
Fig. 6 is the structure chart of middle layer of the invention；
Fig. 7 is middle layer of the invention and the structure chart that pedestal is bonded；
Fig. 8 is structure chart of the invention.
Identified in figure: pedestal 101, pedestal RDL102, the hole pedestal TSV 103, pedestal pit 104, pedestal heat dissipation copper post 105,
Pedestal heat dissipation copper billet 106, cover board 201, cover board heat dissipation copper billet 202, cover board heat dissipation copper post 203, cover board pit 204.
Specific embodiment
Embodiments of the present invention are described below in detail, in which the same or similar labels are throughly indicated identical or classes
As element or the element of similar functions.It is exemplary below with reference to the embodiment of attached drawing description, is only used for explaining
The present invention and cannot function as limitation of the present invention.
Those skilled in the art can understand that unless otherwise defined, all terms used herein (including skill
Art term and scientific and technical terminology) there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless definition as here, will not be explained in an idealized or overly formal meaning.
The label about step mentioned in each embodiment, it is only for the convenience of description, without substantial
The connection of sequencing.Different step in each specific embodiment can carry out the combination of different sequencings, realize this hair
Bright goal of the invention.
The present invention is further described with reference to the accompanying drawings and detailed description.
As shown in Figures 1 to 8, a kind of side heat radiating type radio frequency chip system in package technique, pedestal 101, middle layer, lid
Plate 201 uses same dimensions, is all arrived using one of 4,6,8,12 cun dimensions, thickness ranges for 200um
2000um generally uses silicon wafer, further includes using glass, quartz, silicon carbide, the inorganic material such as aluminium oxide are also possible to epoxy
Resin, the organic materials such as polyurethane, major function are to provide supporting role.Specific processing includes the following steps:
101) pedestal pit 104, the hole pedestal TSV 103 and pedestal 101 processing step of pedestal: are made on 101 surface of pedestal
RDL102.Silicon chip back side is thinned, exposes 103 end of the hole pedestal TSV, continues to do pedestal radiating copper in 103 end of the hole pedestal TSV
Column 105.Pedestal heat dissipation copper billet 106 is set on pedestal heat dissipation 105 top of copper post by welding procedure.
Pedestal pit 104 is produced by the method for dry etching in 101 upper surface of pedestal, pedestal pit 104 is using vertical
Rectangular, inverted trapezoidal, cylinder or hemispherical, 104 size range of pedestal pit is between 10um to 10000um, size herein
Including cube, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height.
Insulating layer is formed by cvd silicon oxide or silicon nitride or directly thermal oxidation on 101 upper surface of pedestal, absolutely
Edge layer thickness range is just made on the insulating layer between 10nm to 100um, through physical sputtering, magnetron sputtering or evaporation process
Make seed layer, seed layer thickness range is in 1nm to 100um, this body structure of seed layer is one layer and is also possible to multilayer, and seed layer is adopted
With one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or a variety of.
By electro-coppering, make copper metal full of pit, densification copper at a temperature of 200 to 500 degree makes bottom by CMP process
Only it is left pedestal pit 104 and fills out copper in 101 lower surface of seat.
The hole pedestal TSV 103,103 diameter range of the hole pedestal TSV are made in 101 upper surface of pedestal by photoetching, etching technics
In 1um to 1000um, depth is in 10um to 1000um.101 upper surface of pedestal by cvd silicon oxide or silicon nitride or
Directly thermal oxidation forms insulating layer, and thickness of insulating layer range is between 10nm to 100um.By physical sputtering, magnetron sputtering or
Person's evaporation process just makes seed layer on the insulating layer, and seed layer thickness range is in 1nm to 100um, this body structure of seed layer
One layer is also possible to multilayer, and seed layer uses one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or a variety of.
By electro-coppering, make copper metal full of the hole TSV, densification copper at a temperature of 200 to 500 degree makes bottom by CMP process
Only it is left TSV hole and fills out copper in 101 upper surface of seat.101 upper surface insulating layer of pedestal can use dry etching or wet etching work
Skill removal.101 upper surface insulating layer of pedestal can also retain.
Middle line along pedestal pit 104 is cut, and is removed the side in 101 hole not set pedestal TSV 103 of pedestal, is used for
It welds spare.
Pedestal RDL102 is made in 101 upper surface of pedestal, process includes production insulating layer, and thickness of insulating layer range exists
10nm to 1000um, insulating layer use silica or silicon nitride, then by photoetching, dry etch process open a window, make RDL and
Copper connection is filled out in the hole TSV, then makes pedestal RDL102 on 101 surface of pedestal by photoetching, electroplating technology, and pedestal RDL102 includes
The metal block of cabling, the pad of key function and adhering chip.The metal of cabling is using one in copper, aluminium, nickel, silver, gold, tin
Kind is a variety of, this body structure of cabling is one or more layers, and thickness range is between 10nm to 1000um.
Insulating layer can also be covered again on the surface pedestal RDL102, open a window exposed pad on the insulating layer.Pad windowing is straight
Diameter is 10um to 10000um.
Bond wire is made in 101 upper surface of pedestal by photoetching, electroplating technology and forms pad, and pad height range exists
10nm to 1000um, pad use one of copper, aluminium, nickel, silver, gold, tin or a variety of, this body structure of pad is one layer or more
Layer.Pad and cabling are located at the same face herein.Wherein RDL is interconnected with pit bared end.
101 lower surface of pedestal is thinned, the thickness after being thinned is in 100um to 700um.Thining method includes first with grinding, so
Wet etching is used afterwards, then uses dry etching, and make the hole TSV fills out copper exposing.
By photoetching and electroplating technology, in the lower surface of pedestal 101 production pedestal heat dissipation copper post 105, pedestal heat dissipation copper post
105 with the hole TSV lower end interconnect, pedestal radiate 105 diameter 10um to 1000um of copper post, pedestal radiate copper post 105 use copper, aluminium,
One of nickel, silver, gold, tin are a variety of, and pedestal radiates 105 body structures of copper post using one or more layers, and diameter range is
Between 10nm to 1000um.
Pedestal heat dissipation copper billet 106 is set far from one end of pedestal 101 in pedestal heat dissipation copper post 105 by welding procedure, it can
To be gluing or eutectic bonding.Pedestal radiates 106 thickness of copper billet between 10um to 1000um.
102) 201 processing step of cover board: cover board 201 is handled by the identical processing method of same step 101), generates cover board
201 lower surface of cover board is thinned in pit 204, the hole cover board TSV and cover board RDL, exposes cover board TSV bore end, in the hole cover board TSV
End setting heat dissipation copper post, and heat dissipation copper billet is arranged in radiating copper top end by welding procedure.
Specifically as shown in figure 5, producing cover board pit 204 by the method for dry etching in 201 silicon chip surface of cover board, cover
Plate pit 204 can be cube, and inverted trapezoidal is also possible to cylindrical or hemispherical.Its size range is arrived in 10um
Between 10000um, size includes cube, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height herein.
Pass through the cvd silicon oxide perhaps insulating layers such as silicon nitride or directly thermal oxidation, insulating layer in 201 upper surface of cover board
Thickness range is between 10nm to 100um.By physical sputtering, magnetron sputtering or evaporation process just production kind on the insulating layer
Sublayer, seed layer thickness range can be one layer and are also possible to multilayer in 1nm to 100um, metal material can be titanium, copper,
Aluminium, silver, palladium, gold, thallium, tin, nickel etc..
By electro-coppering, densification keeps copper finer and close at a temperature of spending copper metal full of cover board pit 204,200 to 500.Copper
CMP process removes 201 surface copper of cover board, and 201 surface of cover board is made only to be left to fill out copper.201 upper surface insulating layer of cover board can be used
Dry etching or wet corrosion technique removal.201 upper surface insulating layer of cover board can also retain.
By photoetching, etching technics makes the hole cover board TSV in silicon chip surface, and cover board TSV bore dia range is arrived in 1um
1000um, depth is in 10um to 1000um.In the insulating layers such as the disposed thereon silica of cover board 201 or silicon nitride, Huo Zhezhi
Thermal oxide is connect, thickness of insulating layer range is between 10nm to 100um.By physical sputtering, magnetron sputtering or evaporation process exist
Seed layer is made above insulating layer, seed layer thickness range can be one layer and be also possible to multilayer, metal in 1nm to 100um
Material can be titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel etc..
By electro-coppering, copper metal is set to be full of TSV, densification keeps copper finer and close at a temperature of 200 to 500 degree.Copper CMP technique makes
The removal of silicon chip surface copper makes 201 surface of cover board only be left to fill out copper formation copper post.Lid surface insulating layer can with dry etching or
The removal of person's wet corrosion technique.Lid surface insulating layer can also retain.
Middle line along cover board pit 204 is cut, and the side in 201 hole not set cover board TSV of cover board is removed, for welding
It is spare.
Cover board RDL is made on the surface of cover board 201, process includes production insulating layer, and thickness of insulating layer range is in 10nm
To 1000um, material can be silica or silicon nitride.By photoetching, dry etch process windowing makes cover board RDL and lid
Copper post one end connection in the hole plate TSV.By photoetching, electroplating technology makes cover board RDL in silicon chip surface.Cover board RDL includes walking
The pad of line and key function, RDL further include the metal block of adhering chip.
Insulating layer can also be covered on the surface cover board RDL, open a window exposed pad on the insulating layer.The metal of cabling can herein
To be copper, aluminium, nickel, silver is golden, the materials such as tin, can be one layer and is also possible to multilayer, thickness range is 10nm to 1000um.
Pad windowing 10um to 10000um diameter.
By photoetching, electroplating technology forms pad in 201 surface of cover board production bond wire, and pad height range is in 10nm
To 1000um, pad metal can be copper, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer and be also possible to multilayer, thickness
Range is 10nm to 1000um.
Pad and cabling are one sides herein, positioned at one end that copper post is exposed.Cover board RDL reveals with cover board pit 204 herein
Outlet interconnection.
101 silicon chip back side of pedestal is thinned, for the thickness after being thinned in 100um to 700um, thining method includes first using grinding,
Then wet etching is used, dry etching is then used, exposes copper post.
By photoetching and electroplating technology, in the back side of cover board 201 production cover board heat dissipation copper post 203, cover board heat dissipation copper post 203
It is interconnected with cover board TSV bore end.Cover board heat dissipation 203 diameter 10um to 1000um of copper post.Cover board heat dissipation 203 metal of copper post can be
Copper, aluminium, nickel, silver, gold, the materials such as tin can be one layer and are also possible to multilayer, and thickness range is 10nm to 1000um.
Cover board heat dissipation copper billet 202 is set on cover board heat dissipation 203 top of copper post by welding procedure, can be gluing or total
Crystalline substance bonding.Cover board radiates 202 thickness of copper billet in 10um to 1000um.
103) intermediate layer handles step: by the identical processing method middle layer of same step 101), middle layer pad is generated
With middle layer groove, middle layer another side, which is thinned, exposes bottom portion of groove, on the another side of the middle layer after being thinned in production
The pad of interbed.
As shown in fig. 6, insulating layer can be the insulation such as silica or silicon nitride in interlayer surfaces depositing insulating layer
Layer or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um.
The pad of middle layer, the pad height range of middle layer are made in surface of insulating layer by photoetching and electroplating technique
In 10nm to 1000um, metal can be copper, and aluminium, nickel, silver, gold, the materials such as tin can be one layer and be also possible to multilayer, thick
Degree range is 10nm to 1000um.
Middle layer groove is made in silicon chip surface by photoetching and dry etch process, and middle layer groove can be cube
Shape, inverted trapezoidal are also possible to cylindrical or hemispherical.Its size range is between 10um to 10000um, and size includes herein
Cube, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height.
The middle layer back side is thinned, for the thickness after being thinned in 100um to 700um, thining method includes first then being used with grinding
Then wet etching uses dry etching, expose middle layer bottom portion of groove.
Surface depositing insulating layer after intermediate silicon wafer is newly thinned, insulating layer can be the insulation such as silica or silicon nitride
Layer or directly thermal oxidation, thickness of insulating layer range is between 10nm to 100um.
Make the pad of the another side of middle layer in surface of insulating layer by photoetching and electroplating technique, middle layer it is another
The pad height range in face is in 10nm to 1000um, and metal can be copper, and aluminium, nickel, silver is golden, and the materials such as tin can be one layer
It can be multilayer, thickness range is 10nm to 1000um.
104) encapsulation step: middle layer and pedestal 101 are bonded together by wafer scale technique, functional chip is welded
Functional chip is interconnected with 101 silicon wafer of pedestal on the pad of pedestal 101, and through bumping interconnection or routing technique.It is logical
Wafer scale technique is crossed cover board 201 and Intermediate Layer Bonding, and interconnects the scolding tin on functional chip with cover board 201, cutting obtains
Single mould group is completed to interconnect by single mould group by pedestal pit 104 and cover board pit 204 and substrate.
As shown in fig. 7, middle layer and pedestal 101 are bonded together by wafer scale technique, bonding temperature is controlled 200
It spends to 600 degree.
Functional chip is welded on the pad of pedestal 101, can be the technique welding of gluing or eutectic weldering.Pass through
Bumping interconnection or routing technique interconnect functional chip with pedestal 101.
Cover board 201 is bonded in interlayer surfaces by wafer scale technique, bonding temperature controls at 200 degree to 500 degree, makes
Scolding tin on functional chip is appeared interconnection with the hole cover board TSV.
Cutting stacks wafer into single module, and cutting position is located at the centre that pit fills out copper position, and cutting mode can be
Laser cutting is also possible to cutter cutting, and the purpose is to which the copper in pit is cut into two parts, the side for the part exposed is made
For solder pad.This cutting can replace the step of pedestal 101 and cover board 201 are along pit excision.
The side of the pit in single module is interconnected with substrate by surface mount process, the side heat radiating type is obtained and penetrates
Frequency chip system class encapsulation structure.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, without departing from the inventive concept of the premise, can also make several improvements and modifications, these improvements and modifications also should be regarded as
In the scope of the present invention.
Claims (4)
1. a kind of side heat radiating type radio frequency chip system in package technique, which is characterized in that specific processing includes the following steps:
101) pedestal processing step: pedestal pit is produced by the method for dry etching in base upper surface, pedestal pit is adopted
With cube, inverted trapezoidal, cylinder or hemispherical, pedestal dimple size range is between 10um to 10000um, size herein
Including cube, the length, width and height or cylinder of inverted trapezoidal, hemispheric diameter or height；
Insulating layer, thickness of insulating layer are formed by cvd silicon oxide or silicon nitride or directly thermal oxidation on base upper surface
Range just makes seed between 10nm to 100um, through physical sputtering, magnetron sputtering or evaporation process on the insulating layer
Layer, in 1nm to 100um, this body structure of seed layer is one layer and is also possible to multilayer seed layer thickness range, seed layer use titanium,
One of copper, aluminium, silver, palladium, gold, thallium, tin, nickel are a variety of；
By electro-coppering, make copper metal full of pedestal pit, densification copper at a temperature of 200 to 500 degree makes bottom by CMP process
Only it is left pedestal pit and fills out copper in seat lower surface；
The hole pedestal TSV is made in base upper surface by photoetching, etching technics, pedestal TSV bore dia range is arrived in 1um
1000um, depth is in 10um to 1000um；Pass through cvd silicon oxide or silicon nitride or directly thermal oxidation in base upper surface
Insulating layer is formed, thickness of insulating layer range is between 10nm to 100um；Pass through physical sputtering, magnetron sputtering or evaporation process
Side's production seed layer on the insulating layer, for seed layer thickness range in 1nm to 100um, this body structure of seed layer can also be with for one layer
It is multilayer, seed layer uses one of titanium, copper, aluminium, silver, palladium, gold, thallium, tin, nickel or a variety of；
By electro-coppering, make copper metal full of the hole pedestal TSV, densification copper at a temperature of 200 to 500 degree makes bottom by CMP process
Only it is left pedestal TSV hole and fills out copper in seat upper surface；
Middle line along pit is cut, and the side in the hole pedestal not set pedestal TSV is removed；
Pedestal RDL is made in base upper surface, process includes production insulating layer, and thickness of insulating layer range is arrived in 10nm
1000um, insulating layer uses silica or silicon nitride, then is opened a window by photoetching, dry etch process, makes the hole RDL and TSV
It fills out copper connection, then RDL is made in susceptor surface by photoetching, electroplating technology, RDL includes cabling, the pad of key function and viscous
Paste the metal block of chip；The metal of cabling uses one of copper, aluminium, nickel, silver, gold, tin or a variety of, this body structure of cabling is
One or more layers, thickness range is between 10nm to 1000um；
Bond wire is made in base upper surface by photoetching, electroplating technology and forms pad, and pad height range is arrived in 10nm
1000um, pad use one of copper, aluminium, nickel, silver, gold, tin or a variety of, this body structure of pad is one or more layers；Herein
Pad and cabling are located at the same face；Wherein RDL is interconnected with pit bared end；
Base lower surface is thinned, the thickness after being thinned is in 100um to 700um；
By photoetching and electroplating technology, in the lower surface of pedestal production pedestal heat dissipation copper post, pedestal radiates copper post with the hole TSV lower end
Interconnection, pedestal radiating copper column diameter 10um to 1000um, pedestal radiate copper post use one of copper, aluminium, nickel, silver, gold, tin or
A variety of, pedestal radiates copper post structure itself using one or more layers, and diameter range is between 10nm to 1000um；
Pedestal heat dissipation copper billet is set far from one end of pedestal in heat dissipation copper post by welding procedure, pedestal heat dissipation copper billet thickness exists
Between 10um to 1000um；
102) cover board processing step: cover board is handled by the identical processing method of same step 101), generates cover board pit, cover board
Cover board lower surface is thinned in the hole TSV and cover board RDL, exposes cover board TSV bore end, and radiating copper is arranged in cover board TSV bore end
Column, and heat dissipation copper billet is arranged in radiating copper top end by welding procedure；
103) intermediate layer handles step: by the identical processing method middle layer of same step 101), middle layer pad is generated in
Interbed groove, middle layer another side, which is thinned, exposes bottom portion of groove, makes pad on the another side of the middle layer after being thinned；
104) encapsulation step: middle layer and pedestal are bonded together by wafer scale technique, functional chip is welded on pedestal
Pad on, and by bumping interconnection or routing technique make functional chip with pedestal silicon wafer interconnect；Pass through wafer scale technique
Cover board and Intermediate Layer Bonding, and interconnect the scolding tin on functional chip with cover board, cutting obtains single mould group, by single mould group
It completes to interconnect by pedestal pit and cover board pit and substrate.
2. a kind of side heat radiating type radio frequency chip system in package technique according to claim 1, it is characterised in that: bottom
Seat, cover board use one of 4,6,8,12 cun dimensions, thickness range be 200um to 2000um, using silicon wafer, glass,
Quartz, silicon carbide, aluminium oxide, epoxy resin or polyurethane.
3. a kind of side heat radiating type radio frequency chip system in package technique according to claim 1, it is characterised in that: support plate
The surface RDL of upper and lower surfaces covers insulating layer again, and open a window exposed pad on the insulating layer, and the diameter of pad windowing herein is
10um to 10000um.
4. a kind of side heat radiating type radio frequency chip system in package technique according to claim 1, it is characterised in that: be thinned
Method includes first then using wet etching with grinding, then with dry etch process, expose copper post.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040157410A1 (en) * | 2003-01-16 | 2004-08-12 | Seiko Epson Corporation | Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module |
| CN102856296A (en) * | 2012-09-24 | 2013-01-02 | 日月光半导体制造股份有限公司 | Stacked semiconductor package element |
| CN106252241A (en) * | 2016-09-08 | 2016-12-21 | 华进半导体封装先导技术研发中心有限公司 | Chip package sidewall pad or the processing technology of salient point |
| JP2016219641A (en) * | 2015-05-22 | 2016-12-22 | 昭和電工株式会社 | Heat sink and housing for base station |
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2018
- 2018-10-10 CN CN201811176820.0A patent/CN110010497B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040157410A1 (en) * | 2003-01-16 | 2004-08-12 | Seiko Epson Corporation | Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module |
| CN102856296A (en) * | 2012-09-24 | 2013-01-02 | 日月光半导体制造股份有限公司 | Stacked semiconductor package element |
| JP2016219641A (en) * | 2015-05-22 | 2016-12-22 | 昭和電工株式会社 | Heat sink and housing for base station |
| CN106252241A (en) * | 2016-09-08 | 2016-12-21 | 华进半导体封装先导技术研发中心有限公司 | Chip package sidewall pad or the processing technology of salient point |
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