CN109994472B - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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Publication number
CN109994472B
CN109994472B CN201810004058.1A CN201810004058A CN109994472B CN 109994472 B CN109994472 B CN 109994472B CN 201810004058 A CN201810004058 A CN 201810004058A CN 109994472 B CN109994472 B CN 109994472B
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metal layer
layer
bottom barrier
barrier metal
active region
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CN109994472A (en
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许智凯
傅思逸
邱淳雅
陈金宏
吴骐廷
林毓翔
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/866,489 priority patent/US10249488B1/en
Priority to US16/273,003 priority patent/US10755919B2/en
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Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor device has three transistors of the same conductor type but different threshold voltages, wherein the first transistor comprises a high dielectric constant layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer, and a low resistance metal. The second transistor comprises the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer, and the low-resistance metal. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low-resistance metal layer.

Description

Semiconductor device and method for fabricating the same
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having the same conductor type but different threshold voltages and a method for manufacturing the same.
Background
The semiconductor industry today is widely using polysilicon as an interstitial material in the gate fabrication of metal oxide semiconductor transistors (MOS). However, the conventional polysilicon gate has been faced with the problem of insufficient performance due to the effects of increasing the equivalent thickness of the gate dielectric layer, decreasing the gate capacitance, and deteriorating the driving force of the device due to boron penetration and gate depletion. In order to replace the conventional polysilicon gate, the industry has developed a design of high-k layer with work function metal as the control gate.
In a Complementary Metal Oxide Semiconductor (CMOS) device, different types of work function metal layers are used for an NMOS device and a PMOS device, respectively. It is known in the art that the dual work function metal fabrication process is more complex in terms of control and compatibility of the fabrication process compared to conventional semiconductor fabrication processes. The need to precisely control the thickness and composition of materials in dual work function gates is becoming more critical as the gate Critical Dimension (CD) of modern transistors shrinks below 20 nm. Component parts of metal gate transistors, including high dielectric constantsSeveral layers, a bottom barrier metal layer, a p-type work function metal, an n-type work function metal, a top barrier metal layer, and a gate fill metal, etc., become difficult to fill into the gate trench at such a fine scale. Such trench space deficiency limits the thickness of the work function metal layer that can be provided in the gate and its tuning threshold voltage (V)th) The ability of the cell to perform.
In addition to the lack of space for disposing the gate device, in current electronic product applications, transistors with multiple threshold voltages are becoming more and more necessary to optimize the delay and power consumption of the device during operation. The threshold voltage of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the voltage that can form an inversion layer at the interface between the gate dielectric layer of the transistor and the substrate. Low threshold voltage devices are used in switching speed-critical logic circuit applications, and high threshold voltage devices are connected to power lines or virtual power lines that are open-circuited in an active mode and open-circuited in a sleep mode, such that the high threshold voltage devices are suitable for use as sleep transistors to reduce the static power consumption of the devices. The material used for the metal layer in the NMOS or PMOS gate mostly affects its work function, and ultimately affects the performance of the whole product. Therefore, semiconductor manufacturers are looking for better manufacturing methods to provide MOS devices with good work function performance and multiple threshold voltage characteristics while keeping up with the current advance of the semiconductor technology blueprint.
Disclosure of Invention
The following paragraphs will provide a summary of the invention to give the reader a basic understanding of the various aspects of the invention. This summary is not an extensive overview and is intended to neither identify key or critical elements nor delineate the scope of the invention, but is merely intended to be a prelude to the more detailed description that is presented later to present some concepts of the invention in a simplified form.
In order to solve the aforementioned problem of insufficient space for filling metal gate features and to meet the requirements of transistor devices with multiple threshold voltage characteristics, the present invention proposes an innovative transistor design with the same conductor type but different layer composition structures. The transistors with multiple threshold voltages are fabricated in the same semiconductor fabrication process, but each of the transistors has additional fabrication process steps to form different layer structures for adjusting work functions, thereby achieving the effect of tuning out multiple different threshold voltages.
In a structural aspect, the present invention provides a semiconductor device, which comprises a substrate, a first transistor disposed on the substrate, wherein the first transistor comprises a high-k layer, a first bottom barrier metal layer disposed on the high-k layer, a second bottom barrier metal layer disposed on the first bottom barrier metal layer, a work function metal layer disposed on the second bottom barrier metal layer, and a low-resistance metal layer disposed on the work function metal layer. The device further includes a second transistor on the substrate, wherein the second transistor includes the high-k dielectric layer, the first bottom barrier metal layer on the high-k dielectric layer, the second bottom barrier metal layer on the first bottom barrier metal layer, and the low-resistance metal layer on the second bottom barrier metal layer. The device further includes a third transistor located on the substrate, wherein the third transistor includes the high dielectric constant layer, the first bottom barrier metal layer located on the high dielectric constant layer, and the low resistance metal layer located on the first bottom barrier metal layer. The first transistor, the second transistor, and the third transistor have the same conductor type but different threshold voltages.
In a method aspect, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a substrate, wherein the substrate is provided with a first active region, a second active region and a third active region, a virtual grid electrode is respectively formed on the three active regions, the virtual grid electrodes are removed to form a grid electrode groove on the three active regions, a high dielectric constant layer, a first bottom barrier metal layer, a second bottom barrier metal layer and a first work function metal layer are sequentially formed in the grid electrode groove, the first work function metal layer on the second active region and the third active region is removed, the second bottom barrier metal layer on the third active region is removed, and each groove is filled with low-resistance metal.
These and other objects of the present invention will become more readily apparent to those skilled in the art after reviewing the following detailed description of the preferred embodiments, which are illustrated in the various figures and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate some embodiments of the invention and together with the description serve to explain its principles. In these figures:
fig. 1 to 7 are schematic cross-sectional views illustrating exemplary processes for manufacturing semiconductor devices having the same conductivity type but different threshold voltages according to preferred embodiments of the present invention.
It should be noted that all the figures in this specification are schematic in nature, and that for the sake of clarity and convenience, various features may be shown exaggerated or reduced in size or in proportion, where generally the same reference signs are used to indicate corresponding or similar features in modified or different embodiments.
Description of the main elements
100 substrate
102 shallow trench isolation structure
103 contact etch stop layer
104 interlevel dielectric layer
106 high dielectric constant layer
108 first bottom barrier metal layer
110 second bottom barrier metal layer
112 p type work function metal layer
114 mask
116 n type workfunction metal layer
118 low resistance metal layer
200 first active (active) region
200a groove
202 virtual gate
204 interface layer
206 first sacrificial gate
208 first cap layer
210 first spacer wall
212 first lightly doped drain
214 first source/drain
216 transistor
300 second active region
300a groove
302 dummy gate
304 interface layer
306 second sacrificial gate
308 second cap layer
310 second partition wall
312 second lightly doped drain
314 second source/drain
316 transistor
400 third active region
400a trench
402 dummy gate
404 interface layer
406 third sacrificial gate
408 third cap layer
410 third partition wall
412 third lightly doped drain
414 third source/drain
416 transistor
Detailed Description
In the following detailed description of the present invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. Such embodiments will be described in sufficient detail to enable those skilled in the art to practice them. The thickness of some of the elements in the figures may be exaggerated for clarity. It is to be understood that other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the described embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the embodiments included therein are defined by the appended claims.
Before explaining the preferred embodiment, certain terms are used throughout the specification to describe the same. For example, as used herein, the term "etching" is generally used to describe a process for patterning a material such that at least a portion of the material remains after the process is completed. It is understood that the process of etching silicon material involves the steps of patterning a photoresist layer on the silicon material and then removing the areas of the silicon not protected by the photoresist layer. Thus, the silicon regions protected by the photoresist layer remain after the etching process is completed. However, in other examples, the etching may refer to a process that does not use a photoresist layer, but still leaves at least a portion of the target material layer after the etching process is completed. The above description is intended to distinguish between the terms "etching" and "removing". When etching a material, at least a portion of the material remains after the fabrication process is completed. In contrast, when a material is removed, substantially all of the material is removed during the fabrication process. However, in some embodiments, the term "removing" may also be interpreted broadly, including etching connotations.
The description herein may refer to various/multiple regions on a substrate for fabricating a field effect transistor device, it being understood that such regions may be present anywhere on the substrate. Furthermore, the regions are not independent of each other, meaning that in some embodiments one or more of the regions may overlap. Although only up to three different regions are illustrated, it should be understood that any number of regions may be present on the substrate, and that it is possible to define a region as having a particular device type or material. These regions are generally provided to facilitate illustration of regions on the substrate having similar device types and are not intended to limit the spirit and scope of the described embodiments.
As used herein, the terms "forming," "depositing," or "disposing" are used to describe the act of covering a substrate with a layer of material. Such terminology is intended to describe any possible technique for forming a layer structure including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like. The act of depositing may be performed in any known suitable manner, depending on the various embodiments. For example, the depositing act may include any fabrication process that grows, coats, or transfers material onto a substrate. Some known such techniques include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), electrochemical deposition (ECD), Molecular Beam Epitaxy (MBE), Atomic Layer Deposition (ALD), and Plasma Enhanced Chemical Vapor Deposition (PECVD), among others.
The term "substrate" as used throughout this specification is generally considered to be a silicon substrate. However, any other suitable substrate may be widely used for the base, such as germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and the like. In other embodiments, the substrate may also be non-conductive, such as a glass substrate or a sapphire substrate.
The name fin-field-effect transistor (FinFET) comes from the fact that the entirety of the FinFET used therein looks like a group of fins, and its main characteristic is that the channel for conduction is surrounded by a thin silicon fin structure, hence the name. The thickness of the fin structure determines the effective channel length of its element. Finfet structures typically have a vertical fin structure between source and drain regions on a substrate. These structures that protrude perpendicularly from the substrate are referred to as fins. This type of gate structure can improve control over channel conduction and reduce the degree of leakage current for overcoming short channel effects.
Please refer to fig. 1 to 7. Fig. 1-7 are schematic cross-sectional views sequentially illustrating exemplary fabrication processes for fabricating semiconductor devices (e.g., finfet devices) having the same conductivity type but different threshold voltages in accordance with a preferred embodiment of the present invention. It is noted that even though the following preferred embodiment pertains to finfet fabrication, it may also be used in planar mosfet fabrication, which is also included in the scope of the present invention.
As shown in fig. 1, a substrate 100, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, is provided. For FinFET fabrication, the substrate 100 may be a fin (strip) structure, which is preferably formed by a conventional Sidewall Image Transfer (SIT) fabrication process. A plurality of Shallow Trench Isolation (STI) structures 102 made of silicon oxide are disposed on the substrate 100. Depending on the regions included in the shallow trench isolation structures 102, the substrate 100 defines a first active region 200, a second active region 300, and a third active region 400 isolated from each other by the shallow trench isolation structures 102, on which semiconductor devices having the same conductivity type but different threshold voltages, such as p-type field effect transistors (hereinafter referred to as pfets) having a standard threshold voltage (SVT), a low threshold voltage (LVT), and an ultra-low threshold voltage (uLVT), respectively, are to be formed. Because in the current semiconductor fabrication, the pFET requires a larger gate trench space for the thickness adjustment of the work function metal layer filled therein to achieve the effect of adjusting the threshold voltages of the n-type field effect transistor (hereinafter referred to as nFET) and the pFET, the pFET is more prone to have insufficient gate trench space compared to the nFET. Accordingly, the transistors described in this embodiment are based on pFETs to show the advantages and appeal of the present invention.
In conjunction with Replacement Metal Gate (RMG) fabrication processes, a dummy transistor 202,302,402 is formed over each defined active region. It is noted that the three active regions defined in the preferred embodiment all have the same conductivity type, such as PMOS regions, and are intended to have gate structures with different threshold voltages fabricated thereon in subsequent fabrication processes. As such, it is expected that structures such as Bottom Barrier Metal (BBM) and/or Work Function Metal (WFM) layers may be formed in different thicknesses or different numbers in these regions during the process of converting the dummy gate into a metal gate. Optical Proximity Correction (OPC) may be performed to adjust or predefine the size or width of the gate trench, so that the gate trench for disposing the gate may be wider than a conventional gate trench for disposing a thicker and/or more bottom barrier metal layer or work function metal layer.
In the embodiment shown in fig. 1, the first dummy transistor 202 includes a first interface layer 204, a first sacrificial gate 206, a first cap layer 208, first spacers 210, first Lightly Doped Drains (LDDs) 212, and first source/drains 214. In a preferred embodiment of the present invention, the first interface layer 204 may be a silicon dioxide layer. An etch stop layer (not shown), such as a titanium nitride layer, may optionally be disposed between the first interface layer 204 and the first sacrificial gate 206. The first sacrificial gate 206 is a polysilicon gate. In another embodiment, the first sacrificial gate 206 is a multi-layer gate structure, such as comprising a polysilicon layer, an amorphous silicon layer, or a germanium layer. The first cap layer 208 may be a silicon nitride layer. The first barrier ribs 210 may have a multi-layered structure, for example, including High Temperature Oxide (HTO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), and the like. The first lightly doped drain 212 and the first source/drain 214 may be formed by a suitable impurity doping process. In some embodiments, the first interface layer 204 and the first etch stop layer may be omitted.
Similarly, the second dummy transistor 302 may include a second interface layer 304, a second sacrificial gate 306, a second cap layer 308, second spacers 310, a second lightly doped drain 312, and second source/drain 214. The elements of the second transistor 302 in this embodiment are similar to those of the first transistor 202, and thus will not be described again. The third dummy transistor 402 may include a third interface layer 404, a third sacrificial gate 406, a third cap layer 408, third spacers 410, third lightly doped drain 412, and third source/drain 414. The elements of the third transistor 402 in this embodiment are similar to those of the first transistor 202 and the second transistor 302, and thus, the description thereof will not be repeated. It is noted that some of these transistors may differ because the first active region 200, the second active region 300, and the third active region 400 are defined to form semiconductor devices having different threshold voltages thereon. For example, the first source/drain 214, the second source/drain 314, and the third source/drain 414 may have dopants of the same conductivity type, but may have different implantation energies and doping doses. In addition, the first dummy transistor 202, the second dummy transistor 302, and the third dummy transistor 402 may also include other semiconductor structures not specifically shown in fig. 1, such as a silicide layer, an epitaxial layer formed by a Selective Epitaxial Growth (SEG) process, such as silicon germanium (SiGe), silicon carbide (SiC), silicon phosphide (SiP), or other passivation layer.
After the first dummy transistor 202, the second dummy transistor 302, and the third dummy transistor 402 are formed, a Contact Etch Stop Layer (CESL) 103 and an inter-layer dielectric (ILD) 104 are formed on the substrate 300 to cover the first dummy transistor 202, the second dummy transistor 302, and the third dummy transistor 402. In one embodiment, the contact etch stop layer 103 may create different stresses in the first active region 200, the second active region 300, and the third active region 400 to achieve a selective strain effect on the first dummy transistor 202, the second dummy transistor 302, and the third dummy transistor 402, respectively.
Please refer to fig. 2. A planarization process, such as a chemical mechanical polishing process, an etch back process, or a combination thereof, is performed to remove a portion of the ild layer 104, the contact etch stop layer 103, the first spacer 210, the second spacer 310, and the third spacer 410, and completely remove the first cap layer 208, the second cap layer 308, the third cap layer 408, etc., until the first sacrificial gate 206, the second sacrificial gate 306, and the third sacrificial gate 406 made of polysilicon are exposed.
Please refer to fig. 3. After the first sacrificial gate 206, the second sacrificial gate 306, and the third sacrificial gate 406 are exposed, a replacement metal gate fabrication process is performed to replace the dummy gate with a metal gate. For example, a selective dry etching process or a wet etching process using ammonia (NH) may be performed first4OH) or tetramethylammonium hydroxide (TMAH) as an etchant to remove the first sacrificial gate 206, the second sacrificial gate 306, and the third sacrificial gate 406 until reaching the first sacrificial gateThe interface layer 204, the second interface layer 304 and the third interface layer 404 are exposed, so that gate trenches 200a,300a and 400a are formed on the first active region 200, the second active region 300 and the third active region 400, respectively, and are used as filling spaces for metal gates. It is also possible that the etching step that removes the sacrificial gate in some embodiments is directly removed along with the interface layer 204,304,404. It is noted that since the dummy gates on the substrate may have different sizes, the gate trenches 200a,300a,400a formed after removing the dummy gates may also have different sizes.
Refer back to fig. 3. After the gate trench is formed, a conformal high-k layer 106 is formed on the surface of the substrate and the gate trench. The high-k layer 106 has a dielectric constant greater than 4 and may comprise a rare earth oxide or a lanthanide oxide, such as HfO2,HfSiO4,HfSiON,Al2O3,La2O3,LaAlO,Ta2O5,ZrO2,ZrSiO4,HfZrO,Yb2O3,YbSiO,ZrAlO,HfAlO,AlN,TiO2,ZrON,HfON,ZrSiON,HfSiON,SrBi2Ta2O9(SBT),PbZrxTi1-xO3(PZT) or BaxSr1-xTiO3(BST), but is not limited thereto.
Still referring to fig. 3. After the formation of the high-k layer 106, a conformal first bottom barrier metal layer 108 and a second bottom barrier metal layer 110 are sequentially formed on the surface of the high-k layer 106 in each active region. The bottom barrier metal layers 108 and 110 may act as a barrier to protect the adjacent metals from degradation due to cross thermal diffusion or electromigration. The material of the two bottom barrier metal layers may comprise Ti, TiN, Ta, TaN or WN. In the preferred embodiment where the transistor is intended to be p-type, the material of the first bottom barrier metal layer 108 is tin and the material of the second bottom barrier metal layer 110 is tan. The first bottom barrier metal layer 108 and the second bottom barrier metal layer 110 may have different thicknesses.
Please refer now to fig. 4. After forming the high-k dielectric layer 106, the first bottom barrier metal layer 108 and the second bottom barrier metal layer 110, the method is used to form a first metal layerA work function metal layer (hereinafter, referred to as a p-type work function metal layer) 112 for adjusting the threshold voltage of the pFET is conformally formed on the surface of the second bottom barrier metal layer 110. The thickness of the p-type workfunction metal layer 112 may be between about
Figure GDA0003276890050000091
In the meantime. For pFET devices, the work function of the work function metal layer is required to be between 4.8eV and 5.2eV, and suitable materials in this interval may include, but are not limited to TiN, Ru, Ir, Pt, WN, Mo2N, TaN, TaC.
For semiconductor transistors with today's gate feature sizes scaled below 20 nm, the p-type workfunction metal layer 112, together with its high-k layer 106 and bottom barrier metal layers 108,110, etc., occupy a large portion of the otherwise narrow gate trench, making it more difficult for other gate features in subsequent fabrication processes to fill the trench. In order to make more space for the gate features, a pull-down operation is performed on the p-type work function metal layer 112 during the fabrication process to make space by removing a portion of the p-type work function metal layer above a predetermined height. The pull-down process may include the step of forming a mask 114 over the p-type workfunction metal layer 112 of the gate trench. The surface of the mask 114 is controlled to a predetermined height level. After the mask 114 is filled, an etching process is performed to remove the p-type workfunction metal layer 112. In this etching process, the portion of the p-type work function metal layer 112 above the predetermined height of the mask 114 is removed, so that only the ㄩ -shaped portion of the p-type work function metal layer 112 remains in the gate trench. The pull-down of the p-type workfunction metal layer 112 may be achieved by a selective directional etching process, such as a reactive-ion etching (RIE) process, tuned to react to the material of the p-type workfunction metal layer 112. As a result of the selective etching process, only the undesired portion of the p-type workfunction metal layer 112 is removed during the process, and the underlying bottom barrier metal layer 110 remains substantially unchanged. The removal of the p-type work function metal layer 112 at a predetermined height can increase the opening size of the trench, so that other gate features in the subsequent fabrication process, such as n-type work function metal and low-resistance metal, can be more easily filled into the trench.
Please refer to fig. 5. After the ㄩ -shaped p-type workfunction metal layer 112 is formed, the mask 114 is removed to expose the surface of the p-type workfunction metal layer 112. A conformal n-type workfunction metal layer 116 for adjusting nFET threshold voltage is then formed on the surface of the ㄩ -shaped p-type workfunction metal layer 112 and the second bottom barrier metal layer 110. The opening of the gate trench is enlarged by removing a portion of the p-type work function metal layer 112 above, allowing the n-type work function metal layer 116 to be more easily formed in the gate trench. Note that the present invention is specifically directed to addressing the problem of insufficient fill space for pFET gate features and to highlighting pFET characteristics with different threshold voltages, and therefore, for the sake of brevity of the present disclosure, nFET elements will not be shown in the figures. The n-type workfunction metal layer 116 formed at this step is only intended to emphasize that the fabrication process of the present invention can fabricate both pFET and nFET devices simultaneously. In some embodiments, n-type workfunction metal layer 116 may have a thickness of between about
Figure GDA0003276890050000101
In the meantime. For nFET devices, the work function of the work function metal layer is required to be between 3.9eV and 4.3eV, and suitable materials in this interval may include, but are not limited to TiAl, ZrAl, WAl, TaAl, HfAl or TiAl.
Refer now to FIG. 6. After the ㄩ -shaped p-type workfunction metal layer 112 and the n-type workfunction metal layer 116 are formed, each of the predetermined active regions 200,300,400 is subjected to a respective different step to alter the gate members that are predetermined to be disposed in those regions, thereby imparting different threshold voltage characteristics thereto. In a preferred embodiment, the active regions 200,300,400 are defined as SVT, LVT and uLVT regions, respectively. First, the n-type work function metal layer 116 is removed from over the active regions 200,300,400, since only the nFET region (not shown) needs to have the n-type work function metal layer 116. This step may include applying a photoresist as an etch mask over all nFET active areas and then performing a selective etch process to remove the n-type workfunction metal layer 116 over the pFET active areas. After the n-type workfunction metal layer 116 is removed, the ㄩ -shaped p-type workfunction metal layer 112 is exposed in the active regions 200,300, 400.
In the preferred embodiment of the present invention, since the active region is defined as the pFET region with a standard threshold voltage, the ㄩ -shaped p-type workfunction metal layer 112 is required to adjust the voltage to the standard voltage, and the active regions 300 and 400 are defined as the pFET regions with low and ultra-low threshold voltages, which require a little more trench space to adjust the voltage to the low voltage. To achieve this, the ㄩ -shaped p-type workfunction metal layer 112 in active regions 300 and 400 is removed. The process steps include coating a photoresist as an etch mask on the active region 200, followed by a selective etch process to remove the p-type workfunction metal layer 112 in the active regions 300 and 400. After the p-type workfunction metal layer 112 is removed, the second (top) bottom barrier metal layer 110 in active regions 300 and 400 is fully exposed, while the ㄩ -shaped p-type workfunction metal layer 112 in active region 200 remains.
Although the p-type workfunction metal layer 112 in the active regions 300 and 400 has been removed, the active region 400 still requires more trench space to tune the voltage to an ultra-low threshold voltage compared to the active region 300. In order to meet the above requirements, other fabrication processes are performed to remove the second (upper) bottom barrier gold layer 110 in the gate trench 400a in the active region 400. The process steps may include coating a photoresist layer on the active regions 200 and 300 as an etching mask, and then performing a selective etching process to remove the second bottom barrier metal layer 110 in the gate trench 400a on the active region 400. The second bottom barrier metal layer 110 outside the gate trench 400a in the active region 400 may not be removed. The emphasis is on making more space in the gate trench to adjust the voltage.
In the case of the LVT active regions 300 and uLVT active regions, it is noted that the second bottom barrier metal layer 110 and the first bottom barrier metal layer 108 are preferably formed by tungsten nitride (WN), but not limited thereto. In the present embodiment, the tungsten nitride based bottom barrier metal layers 108 and 110 can be used as work function metal layers at the same time, with a work function of about 5eV, which is a good value for low threshold voltage devices. This is why the ㄩ -shaped p-type work function metal layer 112 is not required in the active region 300 or 400 of the present invention, since such bottom barrier metal layers can achieve the effects of diffusion barrier and work function adjustment simultaneously. For active region 400 with more trench space, the formation of a thicker, tungsten nitride-based first (lower) bottom barrier metal layer 108 may lower its work function to a level of uLVT. In the embodiment of the present invention, the wider trench space allows more voltage-adjusting space in the active region 400.
Please refer to fig. 7. After the gate features for adjusting the work function in each region are prepared, the low-resistance metal 118 is formed and filled in each gate trench, and a planarization process, such as CMP, is performed to remove the low-resistance metal 118, the second bottom barrier metal layer 110, the first bottom barrier metal layer 108, and the high-k dielectric layer 106 outside the gate trenches, thereby completing the fabrication of the transistors 216,316,416 in the active regions 200,300, 400. The low-resistance metal 118 material may include Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or Ti/TiN, etc., but is not limited thereto.
In the prior art, a top barrier metal (TBM, not shown) is also formed between the low-resistance metal and the underlying work function metal layer to prevent diffusion deterioration therebetween. However, the metal gates 302 and 402 may not have a top barrier metal layer because the metal gates 302 and 402 do not have a conventional work function metal layer, but instead have a bottom barrier metal layer based on tungsten nitride as the work function metal layer.
Since the transistors 216,316,416 have different structural compositions, they may have different electrical behavior. Specifically, the threshold voltage (SVT) of transistor 216 is the largest, the threshold voltage (LVT) of transistor 316 is the next largest, and the threshold voltage (uLVT) of transistor 416 is the smallest. In one embodiment, the threshold voltage of the transistor 216 is between about 0.3V and about 0.6V, the threshold voltage of the transistor 316 is between about 0.2V and about 0.3V, and the threshold voltage of the transistor 416 is between about 0.1V and about 0.2V.
In summary, the present invention provides a semiconductor structure having multiple transistors and a method for fabricating the same, wherein the transistors are formed with the same conductivity type but different gate members. For example, in the preferred embodiment, the semiconductor device includes a first transistor 216, a second transistor 316, and a third transistor 416, wherein the first transistor 216 includes a high-k layer 106, a first bottom barrier metal layer 108 on the high-k layer 106, a second bottom barrier metal layer 110 on the first bottom barrier metal layer 108, a work function metal layer 112 on the second bottom barrier metal layer 110, and a low-resistance metal 118 on the work function metal layer 112. The second transistor 316 includes the high-k layer 106, the first bottom barrier metal layer 108 on the high-k layer 106, the second bottom barrier metal layer 110 on the first bottom barrier metal layer 108, and the low-resistance metal 118 on the second bottom barrier metal layer 110. The third transistor 416 includes the high-k dielectric layer 106, the first bottom barrier metal layer 108 on the high-k dielectric layer 106, and the low-resistance metal 118 on the first bottom barrier metal layer 108. With such different gate compositions, it is possible to adjust the respective electrical behavior of the transistors and provide them with different threshold voltages.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (13)

1. A semiconductor device, comprising:
a substrate;
a first transistor located on the substrate, wherein the first transistor comprises a high-k layer, a first bottom barrier metal layer located on the high-k layer, a second bottom barrier metal layer located on the first bottom barrier metal layer, a work function metal layer located on the second bottom barrier metal layer, and a low-resistance metal located on and in direct contact with the work function metal layer;
a second transistor located on the substrate, wherein the second transistor comprises the high-k layer, the first bottom barrier metal layer located over the high-k layer, the second bottom barrier metal layer located over the first bottom barrier metal layer, and the low-resistance metal located over and in direct contact with the second bottom barrier metal layer; and
a third transistor located on the substrate, wherein the third transistor includes the high dielectric constant layer, the first bottom barrier metal layer is located on the high dielectric constant layer, and the low resistance metal is located on and in direct contact with the first bottom barrier metal layer, wherein the first transistor, the second transistor, and the third transistor have the same conductor type but different threshold voltages.
2. The semiconductor device according to claim 1, wherein the first transistor, the second transistor, and the third transistor are p-type transistors.
3. The semiconductor device as claimed in claim 1, wherein the material of the first bottom barrier metal layer is tungsten nitride.
4. The semiconductor device as claimed in claim 1, wherein the material of the second bottom barrier metal layer is tungsten nitride.
5. The semiconductor device as defined in claim 1, wherein the first bottom barrier metal layer and the second bottom barrier metal layer are made of titanium nitride and tantalum nitride, respectively.
6. The semiconductor device as defined in claim 1, wherein the work function metal layer is shaped like ㄩ and has a top surface lower than a top surface of the low resistance metal.
7. The semiconductor device as claimed in claim 1, further comprising a top barrier metal layer between said work function metal layer and said low resistance metal.
8. The semiconductor device as claimed in claim 1, further comprising an interface layer between the substrate and the high-k layer.
9. A method of fabricating a semiconductor device, comprising:
providing a substrate having a first active region, a second active region and a third active region;
forming dummy gates in the first active region, the second active region and the third active region, respectively;
removing the dummy gates to form trenches in the first active region, the second active region, and the third active region, respectively;
forming a high-k layer in the trench, a first bottom barrier metal layer over the high-k layer, a second bottom barrier metal layer over the first bottom barrier metal layer, and a first work function metal layer over the second bottom barrier metal layer;
removing the first work function metal layer on the second active region and the third active region;
removing the second bottom barrier metal layer on the third active region; and
the trench is filled with a low-resistance metal in direct contact with the first work function metal layer on the first active region, the second bottom barrier metal layer on the second active region, and the first bottom barrier metal layer on the third active region, respectively.
10. The method as claimed in claim 9, further comprising performing an etching process to remove the first work-function metal layer at a predetermined height such that the first work-function metal layer is shaped like ㄩ.
11. The method as claimed in claim 10, further comprising forming a second work function metal layer on the ㄩ -shaped first work function metal layer, wherein the second work function metal layer and the first work function metal layer are respectively used in transistors with different conductor types.
12. The method of claim 11, further comprising removing the second workfunction metal layer from the first, second, and third active regions.
13. The method of claim 9, further comprising performing a chemical mechanical polishing process to remove the high-k layer, the first bottom barrier metal layer, and the second bottom barrier metal layer outside the trench.
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