CN109991541A - The chip architecture that lead-acid accumulator parameter calculates - Google Patents
The chip architecture that lead-acid accumulator parameter calculates Download PDFInfo
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- 230000036541 health Effects 0.000 claims description 20
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/3644—Constructional arrangements
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Abstract
The present invention provides a kind of chip architecture that lead-acid accumulator parameter calculates, for calculating the monomer lead acid storage battery parameter that voltage rating is 2V, include: voltage transformation module, connect the positive and negative grade of the lead-acid accumulator, for the voltage of the lead-acid accumulator to be converted to normal voltage power supply；Clock unit, for clock signal needed for providing work for chip；Data processing unit embeds remaining capacity computation model and health status prediction model；For operating parameter being read using universal serial bus, according to remaining capacity computation model described in the parameters revision and health status prediction model when receiving the clock signal.Chip architecture of the invention reads operating parameter according to external timing signal automatic trigger, according to remaining capacity computation model described in the parameters revision and health status prediction model, the remaining capacity computation model and health status prediction model use the operation mode of iteration convergence to calculate static SOC value, SOH value.
Description
Technical Field
The invention relates to the technical field of information processing, in particular to a chip architecture for calculating parameters of a lead-acid storage battery.
Background
In the field of lead-acid storage batteries, multiple instruments are often used for measuring parameters of a single lead-acid storage battery respectively, and the parameters (such as parameters of electric quantity, voltage, health state and the like) of the lead-acid storage battery can be obtained finally through combination and measurement of the multiple instruments.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a chip architecture for calculating parameters of a lead-acid battery, which is used to solve the problem of low efficiency and low accuracy of calculating parameters of a lead-acid battery in the prior art.
In order to achieve the above and other related objects, the present invention provides a chip architecture for calculating parameters of a lead-acid battery, which is used for calculating parameters of a single lead-acid battery with a rated voltage of 2V, and comprises:
the voltage conversion unit is connected with the positive and negative stages of the lead-acid storage battery and is used for converting the voltage of the lead-acid storage battery into standard voltage for power supply;
the clock unit is used for providing clock signals required by work for the chip;
the data processing unit is internally embedded with a residual electric quantity calculation model and a health state estimation model; the system comprises a clock signal acquisition module, a serial bus, a residual electric quantity calculation module, a health state estimation module and a power consumption module, wherein the clock signal acquisition module is used for acquiring a clock signal of the power consumption module and a health state estimation module; wherein,
the residual electric quantity calculation model is used for obtaining an approximate approximation iteration method according to a dichotomy theory, and obtaining a static state SOC value estimated by the lead-acid storage battery through the comparison processing of a reduced interval and a middle value;
the health state estimation model is used for obtaining an approximate approximation iteration method according to a dichotomy theory, and obtaining an SOH value based on the actual capacity and the initial capacity of the battery through the reduction of an interval and the comparison processing of an intermediate value.
In an embodiment of the present invention, the serial communication unit is utilized to communicate and exchange data with an external device.
In an embodiment of the present invention, the method includes: and a reset unit for initializing the register when receiving an external reset signal.
In an embodiment of the present invention, the method includes: and the test unit is used for comparing the read operation parameters with preset values, testing whether each parameter is normal one by one, and sending a test result to the data processing unit.
In an embodiment of the present invention, the method includes: and the temperature monitoring unit is used for monitoring the temperature of the current working environment, and when the temperature exceeds a preset value, the data processing unit stops working and transmits the temperature to external equipment.
As described above, the chip architecture for calculating the parameters of the lead-acid storage battery has the following beneficial effects:
the chip architecture automatically triggers and reads operation parameters according to an external clock signal, the residual electric quantity calculation model and the health state estimation model are corrected according to the parameters, and the residual electric quantity calculation model and the health state estimation model calculate a static SOC value and an SOH value in an iterative convergence operation mode.
Drawings
FIG. 1 shows a block diagram of a chip architecture for calculating parameters of a lead-acid battery according to the present invention;
FIG. 2 is a block diagram showing a complete chip architecture for calculating parameters of a lead-acid battery according to the present invention.
Element number description:
1 Voltage conversion Unit
2 clock unit
3 data processing unit
31 residual capacity calculation model
32 state of health prediction model
4 serial communication unit
5 reset unit
6 test unit
7 temperature monitoring unit
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, a chip architecture block diagram for calculating parameters of a lead-acid battery is provided, and is used for calculating parameters of a single lead-acid battery with a rated voltage of 2V, and the chip architecture block diagram includes:
the voltage conversion unit 1 is connected with the positive and negative levels of the lead-acid storage battery and used for converting the voltage of the lead-acid storage battery into standard voltage for power supply;
the power wire is connected with the anode and the cathode of the lead-acid storage battery, the power wire is connected with the signal wire at the periphery of the chip, and the signal wire comprises a serial communication unit 4 of which the external serial bus is connected with the chip; the external reset signal is connected with the reset unit 5 in the chip, the external clock signal is connected with the clock unit 2, the external clock signal is controllable, and the external test signal is connected with the test unit 6.
The clock unit 2 is used for providing clock signals required by work for the chip;
the chip operates according to a received external clock signal, when the clock signal is received, the chip reads an operating parameter from the serial bus, calls a corresponding model according to the operating parameter for calculation, and returns a calculation result to the serial bus to be sent to the outside; when the clock signal is not received, the chip does not operate.
A data processing unit 3 in which a remaining power calculation model (SOC model algorithm) and a health state estimation model (SOH model algorithm) are embedded; the system comprises a clock signal acquisition module, a serial bus, a residual electric quantity calculation module, a health state estimation module and a power consumption module, wherein the clock signal acquisition module is used for acquiring a clock signal of the power consumption module and a health state estimation module;
the residual electric quantity calculation model 31 is used for obtaining an approximate approximation iteration method according to a dichotomy theory, and obtaining an estimated static SOC value of the lead-acid storage battery through the reduced interval, taking a middle value and carrying out comparison processing;
the health state estimation model 32 is used for obtaining an SOH value based on the actual capacity and the initial capacity of the battery by carrying out comparison processing on an intermediate value obtained by narrowing the interval according to an approximate approximation iteration method obtained by a dichotomy theory.
In this embodiment, the data Processing Unit may include a Microprocessor (MCU), and the MCU may include a Central Processing Unit (CPU), a read-only memory (ROM), a Random Access Memory (RAM), a timing module, an analog-to-digital conversion (a/D converter), and a plurality of inputs/outputs. Of course, the chip architecture may also take other forms of integrated circuits, such as: application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs).
Specifically, when the whole system is powered on, the external clock signal is valid, the chip receives the external clock signal, meanwhile, the reset signal on the serial bus is valid, and the chip reset unit 5 initializes the register when receiving the external reset signal; the chip testing unit 6 is used for comparing the read operation parameters with preset values, testing whether the parameters are normal one by one and sending a test result to the data processing unit; when the serial bus is effective, the data processing unit receives an external detection signal and feeds back a state signal of the chip to external equipment by using the serial communication interface; the data processing unit monitors the serial bus in real time, when the external serial bus receives a chip standby instruction, the data processing unit feeds back a signal, the wire number of the external bus is closed, and the chip enters a standby state; when an operation instruction of an external serial bus is monitored, the serial communication unit 4 starts to receive operation parameters on the serial bus, the data processing unit 3 respectively iteratively calculates a static state of charge (SOC) value and a state of health (SOH) value by using a residual power calculation model and a health state estimation model according to the operation parameters, and feeds back an iterative calculation result and result validity to external equipment by using the serial bus.
The working state of a voltage conversion unit in the chip is controlled by a serial bus command, and is in a low-power consumption working state under the default condition, and the voltage conversion unit can run at full speed with power of about 10W only after the chip receives an operation command to complete iterative operation.
In the above embodiment, the serial communication unit 4 is used to perform communication and data exchange with an external device, and reception of an external signal and transmission of a feedback signal (a state signal, an operation parameter, and a calculation result of the parameter) of a chip are completed.
In the above embodiment, the chip architecture includes: and the temperature monitoring unit 7 is used for monitoring the temperature of the current working environment, and when the temperature exceeds a preset value, the data processing unit stops working and transmits the temperature to external equipment.
Specifically, the working temperature of the chip can be monitored in real time through the temperature monitoring unit, the normal work of each unit in the chip is ensured, and the phenomenon that the performance is reduced or the unit is damaged due to overhigh working temperature is prevented.
In summary, the chip architecture of the present invention automatically triggers and reads the operating parameters according to the external clock signal, and corrects the remaining power calculation model and the health state estimation model according to the parameters, wherein the remaining power calculation model and the health state estimation model calculate the static SOC value and the SOH value by using an iterative convergence operation method. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. A chip architecture for calculating parameters of a lead-acid storage battery is used for calculating parameters of a single lead-acid storage battery with a rated voltage of 2V, and comprises the following steps:
the voltage conversion unit is connected with the positive and negative stages of the lead-acid storage battery and is used for converting the voltage of the lead-acid storage battery into standard voltage for power supply;
the clock unit is used for providing clock signals required by work for the chip;
the data processing unit is internally embedded with a residual electric quantity calculation model and a health state estimation model; the system comprises a clock signal acquisition module, a serial bus, a residual electric quantity calculation module, a health state estimation module and a power consumption module, wherein the clock signal acquisition module is used for acquiring a clock signal of the power consumption module and a health state estimation module; wherein,
the residual electric quantity calculation model is used for obtaining an approximate approximation iteration method according to a dichotomy theory, and obtaining a static state SOC value estimated by the lead-acid storage battery through the comparison processing of a reduced interval and a middle value;
the health state estimation model is used for obtaining an approximate approximation iteration method according to a dichotomy theory, and obtaining an SOH value based on the actual capacity and the initial capacity of the battery through the reduction of an interval and the comparison processing of an intermediate value.
2. The chip architecture for lead-acid battery parameter calculation of claim 1, wherein a serial communication unit is utilized for communication and data exchange with external devices.
3. The chip architecture for lead-acid battery parameter calculation of claim 1, comprising: and a reset unit for initializing the register when receiving an external reset signal.
4. The chip architecture for lead-acid battery parameter calculation of claim 1, comprising: and the test unit is used for comparing the read operation parameters with preset values, testing whether each parameter is normal one by one, and sending a test result to the data processing unit.
5. The chip architecture for lead-acid battery parameter calculation of claim 1, comprising: and the temperature monitoring unit is used for monitoring the temperature of the current working environment, and when the temperature exceeds a preset value, the data processing unit stops working and transmits the temperature to external equipment.
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| CN114460472A (en) * | 2022-04-13 | 2022-05-10 | 深圳市思远半导体有限公司 | Electric meter chip, control method thereof, electronic device and online simulation system |
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Application publication date: 20190709 |