CN109981517B - QPSK neural network demodulator based on FPGA and control method thereof - Google Patents
QPSK neural network demodulator based on FPGA and control method thereof Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/3405—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power
- H04L27/3444—Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power by applying a certain rotation to regular constellations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
- H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
- H04L27/3863—Compensation for quadrature error in the received signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
- H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
- H04L27/3872—Compensation for phase rotation in the demodulated signal
Abstract
The invention relates to a QPSK neural network demodulator based on FPGA, comprising: the clock and reset module is used for sending a clock signal and a reset signal; the AD sampling module is used for sampling a signal to be demodulated to acquire sampling data; the input buffer module is used for receiving and buffering the sampling data and performing clock domain conversion on the sampling data; the phase mutation detection module is used for detecting the relative phase change in the sampling data after clock domain conversion and outputting phase mutation information; the constellation rotation and data turnover module is used for receiving and processing the phase mutation information to form baseband data; and the synchronous output module is used for synchronously judging the baseband data and generating and outputting the demodulation data. The demodulator provided by the invention has low parameter complexity and high structural stability, can improve the adaptability of the demodulator to a special environment through targeted training, and performs one-dimensional convolution operation by using a time delay network, thereby reducing the calculation complexity and improving the use efficiency of hardware resources.
Description
Technical Field
The invention belongs to the technical field of digital communication, and particularly relates to a QPSK neural network demodulator based on an FPGA and a control method thereof.
Background
The modulation and demodulation link is a crucial process in a digital communication system, the modulation is a process of loading a baseband signal onto an electromagnetic wave signal with a higher frequency in order to facilitate signal transmission, and the demodulation is a reverse process of the modulation and is a process of moving the signal from the higher frequency to a low frequency. Generally, the input signal of the demodulator introduces many non-ideal factors in transmission and reception, including environmental noise, multipath effect, electromagnetic interference of receiving equipment, and the like. The existence of these factors puts higher demands on the performance of the demodulator, and it can be said that the performance of the demodulator greatly affects the performance of the entire communication system.
The convolutional neural network is a typical feedforward multilayer neural network, can automatically extract complex features from a large amount of data to perform autonomous learning, has low requirement on an input image, and does not need to perform complicated early-stage preprocessing on the input image. Because of the specific network structure of the convolutional neural network, the recognition capability of the convolutional neural network is not easily influenced by figure distortion or simple geometric transformation in an image, and the convolutional neural network also has a good recognition effect on recognition objects with slight changes. Among them, the one-dimensional convolutional neural network is particularly suitable for processing discrete time sequences due to the structural characteristics of one-dimensional input. If the high-speed AD sampling data of the modulation signal is just a group of sequences, if the high-speed AD sampling data of the modulation signal is input into a one-dimensional convolutional neural network, the information carried in the modulation signal can be analyzed through detecting some characteristics of the high-speed AD sampling data. The method has the specific advantages compared with the traditional demodulation method, firstly, a stable network structure can be constructed through experiments, so that the method is insensitive to parameter disturbance of input signals, and the robustness of the method is improved. Secondly, because the identification capability of the one-dimensional convolutional neural network to the information is obtained through training, when the one-dimensional convolutional neural network is used for a special channel environment, the adaptability of the one-dimensional convolutional neural network can be improved through designing a large amount of characteristic training data, so that the one-dimensional convolutional neural network can better adapt to special conditions such as frequency offset and the like.
With the progress of microelectronic manufacturing process and integrated circuit design, hardware implementation schemes of convolutional neural networks are more and more diversified, wherein a Field Programmable Gate Array (FPGA) becomes the best choice for hardware implementation of convolutional neural networks due to the advantages of stability, reliability, rich resources, repeatable programming, low power consumption and high speed. In recent years, the development difficulty of FPGA design is greatly reduced due to the development of high-level comprehensive tools based on FPGA, so that the FPGA can realize complex algorithms more conveniently and quickly.
In a conventional demodulator, two methods, coherent demodulation and noncoherent demodulation, are generally adopted. Among them, coherent demodulation is more widely used due to its good anti-noise performance. Coherent demodulation is mainly aimed at demodulation of linear modulation signals, and the implementation method is that a coherent carrier strictly synchronous with a modulation carrier is recovered at a receiving end, and then frequency mixing and judgment are carried out. The quality of the coherent carrier is directly related to the performance of the demodulator. In this method, there are a large number of configurable parameters, including filter parameters, digitally controlled oscillator parameters, phase detection parameters, loop parameters, etc., each of which may affect the demodulation performance, which results in poor robustness of the demodulator and inability to perform targeted upgrade and improvement for a specific environment, such as frequency offset.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a QPSK neural network demodulator based on an FPGA and a control method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a QPSK neural network demodulator based on FPGA, which comprises:
the clock and reset module is used for sending a clock signal and a reset signal;
the AD sampling module is used for sampling a signal to be demodulated to acquire sampling data;
the input buffer module is used for receiving and buffering the sampling data and performing clock domain conversion on the sampling data;
the phase mutation detection module is used for detecting the relative phase change in the sampling data after clock domain conversion and outputting phase mutation information;
the constellation rotation and data turnover module is used for receiving and processing the phase mutation information to form baseband data;
and the synchronous output module is used for synchronously judging the baseband data and generating and outputting demodulation data.
In one embodiment of the present invention, further comprising: and the PCIe interaction module is used for inputting the network parameters into the FPGA.
In one embodiment of the present invention, further comprising: and the parameter storage module is used for receiving, storing and forwarding the network parameters.
In one embodiment of the present invention, the phase jump detection module includes: a plurality of one-dimensional convolutional neural networks implemented within the FPGA.
In one embodiment of the present invention, the one-dimensional convolutional neural network comprises: an input layer, a convolutional layer, an implicit layer and an output layer, and auxiliary input buffer, output buffer and control module.
Another embodiment of the present invention provides a method for controlling a QPSK neural network demodulator based on an FPGA, including:
sending a clock signal and a reset signal;
sampling a signal to be demodulated to obtain sampling data;
receiving and buffering the sampling data, and performing clock domain conversion on the sampling data;
detecting relative phase change in the sampling data after clock domain conversion, and outputting phase mutation information;
receiving and processing the phase mutation information to form baseband data;
and synchronously judging the baseband data, and generating and outputting demodulation data.
In one embodiment of the present invention, before the clock signal and the reset signal are transmitted, the method further includes: and storing the network parameters to a parameter storage module.
In an embodiment of the present invention, before sampling the signal to be demodulated to obtain the sample data, the method further includes: the network parameters are input to the FPGA.
Compared with the prior art, the invention has the beneficial effects that:
1. the demodulator provided by the invention takes the relative phase jump in the QPSK modulation signal as a characteristic, utilizes the phase jump detection module realized in the FPGA to detect the characteristic of the QPSK modulation signal, respectively detects three relative phase changes in the QPSK modulation signal, and utilizes the constellation rotation and data inversion module realized in the FPGA to output a demodulation data waveform according to the type and the opportunity of the phase jump so as to complete demodulation.
2. The demodulator provided by the invention has low parameter complexity and high structural stability, can improve the adaptability of the demodulator to a special environment through targeted training, and performs one-dimensional convolution operation by using a time delay network, thereby reducing the calculation complexity and improving the use efficiency of hardware resources.
Drawings
Fig. 1 is a schematic structural diagram of a QPSK neural network demodulator based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic waveform diagram of a signal to be demodulated in a QPSK neural network demodulator based on an FPGA according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an operating process of a QPSK neural network demodulator based on an FPGA according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a one-dimensional convolutional neural network in another QPSK neural network demodulator based on an FPGA according to an embodiment of the present invention;
fig. 5 is a schematic diagram of one-dimensional Same convolution operation in a QPSK neural network demodulator according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a time delay network structure in another QPSK neural network demodulator based on FPGA according to an embodiment of the present invention;
fig. 7 is a schematic flowchart of a control method of a QPSK neural network demodulator based on an FPGA according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a QPSK neural network demodulator based on an FPGA according to an embodiment of the present invention.
The embodiment of the invention provides a QPSK neural network demodulator based on FPGA, which comprises:
the clock and reset module is used for sending a clock signal and a reset signal;
the AD sampling module is used for sampling a signal to be demodulated to acquire sampling data;
the input buffer module is used for receiving and buffering the sampling data and performing clock domain conversion on the sampling data;
the phase mutation detection module is used for detecting the relative phase change in the sampling data after clock domain conversion and outputting phase mutation information;
the constellation rotation and data turnover module is used for receiving and processing the phase mutation information to form baseband data;
and the synchronous output module is used for synchronously judging the baseband data and generating and outputting the demodulation data.
Specifically, the clock and reset module sends two signals, namely a clock signal and a reset signal, wherein the clock signal exists all the time when the system works, and the reset signal exists only when the reset signal is sent. The input buffer module is positioned at the forefront end of the demodulator and is used for finishing the function of inputting and buffering the sampling data. The front stage of the demodulator is an AD sampling module, when the front stage and the back stage transmit data, the input buffer module receives the data according to a sampling synchronous clock given by the AD sampling module, and the sampling synchronous clock is unstable compared with an FPGA internal clock and cannot be directly used by the back stage, so that the input buffer module is provided with an FIFO (first in first out) for clock domain crossing processing of a signal line, the width of output data is equal to that of the input signal, and the clock on the FPGA is used as a synchronous output clock of the data.
The clock of the demodulator is generated by an external crystal oscillator after being phase-locked by an FPGA internal PLL, and is provided for each module through a global clock network, so that the delay of the clock reaching each module is ensured to be the same.
The clock and reset module is also used for generating a reset signal for the operation of the demodulator, the reset signal comprises two stages, the first stage is clock reset, namely after the demodulator is electrified, the PLL starts to work from reset; the second-stage reset is program reset, and after the PLL enters a locking state, all modules enter a working state from a reset state.
Particularly, in the specific embodiment of the present invention, the method further includes: and the PCIe interaction module is used for inputting the network parameters into the FPGA.
The PCIe interaction module is used for completing information interaction between the general computer and the FPGA, mainly inputting the trained network parameters into the FPGA, and outputting the demodulated data to the computer for further analysis and processing.
Particularly, in the specific embodiment of the present invention, the method further includes: and the parameter storage module is used for receiving, storing and forwarding the network parameters.
The parameter storage module mainly utilizes BRAM resources in the FPGA to form a block storage array so as to store network parameters, the network parameters are stored into the parameter storage module by the upper computer before the FPGA is reset, the network parameters are input into the FPGA after the FPGA is reset, and the network parameters are only used in the FPGA and are not modified. The module reads in network parameters through a PCIe interface after being electrified and provides the network parameters to the phase jump detection module when needed.
In particular, in an embodiment of the present invention, the phase jump detecting module includes: a plurality of one-dimensional convolutional neural networks implemented within the FPGA.
Specifically, the phase jump detection module is a core of the demodulator, and comprises: three one-dimensional convolution neural networks realized in FPGA respectively detect three relative phase changes of pi/2 type, pi/2 type and pi type in QPSK to-be-demodulated signals and output phase mutation information.
Specifically, referring to fig. 2 and 3, the waveform of the signal to be demodulated is as shown in fig. 2, and it is easy to know that the relative phase change in the QPSK signal includes three types of pi/2 type, -pi/2 type, and pi type. The working process of the demodulator is shown in fig. 3, after the demodulator is powered on, the clock and reset module sequentially provides a clock signal and a reset signal, then AD sampling is performed on a signal to be demodulated to form a discrete time sequence, and the sequence is input to the input buffer module for data buffering and clock domain conversion. Then, the data after clock domain conversion is input into a phase mutation detection module in a sliding window mode, meanwhile, a parameter storage module gives out corresponding network parameters, and a constellation rotation and data inversion module initializes IQ two-way data lines; in the phase jump detection, a phase jump detection module calculates according to a network parameter trained in advance, and the rule of the calculation result output is as follows: if the phase jump detection module detects a certain phase jump in the current input, 1 is output, otherwise 0 is output. The output of the phase jump detection module is a row of discrete sequences with the same rate as the AD sampling rate, and the shape of the discrete sequences shows that a pulse appears when a certain phase jump occurs; the constellation rotation and data inversion module performs pulse detection on an output sequence of the phase mutation detection module, inverts a constellation diagram according to the type of the phase mutation, takes a constellation position corresponding to the above code element as a starting point, rotates according to the type of the phase change, rotates 90 degrees clockwise when the pi/2 type phase mutation occurs, rotates 90 degrees anticlockwise when the-pi/2 type phase mutation occurs, rotates 180 degrees when the pi type phase mutation occurs, and inverts the IQ two-path data line according to the constellation position corresponding to the current code element to obtain IQ two-path data waveforms; and then, the synchronous output module samples and outputs the IQ two-path data waveform according to the code rate, so that final demodulation data are obtained.
In particular, in an embodiment of the present invention, the one-dimensional convolutional neural network includes: an input layer, a convolutional layer, an implicit layer and an output layer, and auxiliary input buffer, output buffer and control module.
Specifically, referring to fig. 4, the one-dimensional convolutional neural network implemented in the FPGA in the phase jump detection module includes: input layer, convolutional layer, hidden layer, output layer, and auxiliary input buffer, output buffer and control module. In the input layer, registers are cascaded to form a sliding window, the convolutional layer comprises two one-dimensional convolutional kernels with the same structure and physically independent from each other, main constituent elements in the hidden layer and the output layer are neurons, the neuron models of the two layers are similar, only synapses are different in number, and the activation function of the neurons adopts a sigmoid function. The input/output buffer is used for buffering input data and performing clock domain conversion, and the control module is used for controlling effective signals and coordinating the parameter storage module to give corresponding parameters timely.
Specifically, referring to fig. 5 and 6, the convolutional layer in the one-dimensional convolutional neural network implemented in the FPGA needs to complete one-dimensional same convolution operation, where same means that the length of the output vector is equal to that of the input vector, assuming that the length σ of the input vector is M +1 and the length of the convolution kernel is M +1, according to the convolution theory, if an output vector with length M +1 is obtained, the input vector needs to be extended with length M, generally 0 is used for extension, and the extended input vector with length 2M +1 and the convolution kernel with length M +1 are subjected to convolution operation, and the result is shown in fig. 5. The convolution operation comprises (M +1)2 times of multiplication operations, wherein one part of the multiplication operations is the case that the multiplier is 0, the calculation result of the part of data in the wire frame of FIG. 5 is once appeared in the previous operation or the future operation, and a plurality of repeated calculations can be avoided by adding some multiplication results into the time delay network formed by different delay queues. The structure of the time delay network is shown in fig. 6. In the figure [ x ]1x2...xM+1]Is the current input vector, [ w ]1w2...wM+1]Is the current convolution kernel output by the parameter storage module, D is the delay unit, and the convolution operation result corresponding to the current input is [ y1y2...yM+1]. Under the control of an FPGA clock, data can be accurately delayed in a beat mode with small resource occupation, and by matching with results on a delay line, each input vector on average only needs to be subjected to multiplication operation for M +1 times to obtain a convolution result.
As shown in fig. 7, the present invention provides a method for controlling a QPSK neural network demodulator based on an FPGA on the basis of the above embodiments, including:
sending a clock signal and a reset signal;
sampling a signal to be demodulated to obtain sampling data;
receiving and caching the sampling data, and performing clock domain conversion on the sampling data;
detecting relative phase change in the sampling data after clock domain conversion, and outputting phase mutation information;
receiving and processing the phase mutation information to form baseband data;
and synchronously judging baseband data, and generating and outputting demodulation data.
In particular, in an embodiment of the present invention, before sending the clock signal and the reset signal, the method further includes: and storing the network parameters to a parameter storage module.
In particular, in an embodiment of the present invention, before sampling a signal to be demodulated to obtain sample data, the method further includes: the network parameters are input to the FPGA.
The demodulator provided by the invention takes the relative phase jump in the QPSK modulation signal as a characteristic, utilizes the phase jump detection module realized in the FPGA to detect the characteristic of the QPSK modulation signal, respectively detects three relative phase changes in the QPSK modulation signal, and utilizes the constellation rotation and data inversion module realized in the FPGA to output a demodulation data waveform according to the type and the opportunity of the phase jump so as to complete demodulation. The demodulator provided by the invention has low parameter complexity and high structural stability, can improve the adaptability of the demodulator to a special environment through targeted training, and performs one-dimensional convolution operation by using a time delay network, thereby reducing the calculation complexity and improving the use efficiency of hardware resources.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. An FPGA-based QPSK neural network demodulator, comprising:
the clock and reset module is used for sending a clock signal and a reset signal;
the AD sampling module is used for sampling a signal to be demodulated to acquire sampling data;
the input buffer module is used for receiving and buffering the sampling data and performing clock domain conversion on the sampling data;
the phase mutation detection module is used for detecting the relative phase change in the sampling data after clock domain conversion and outputting phase mutation information; the phase mutation detection module comprises three one-dimensional convolutional neural networks which are realized in an FPGA (field programmable gate array), the three one-dimensional convolutional neural networks are used for respectively detecting three relative phase changes of pi/2 type, pi/2 type and pi type in a QPSK (quadrature phase shift keying) signal to be demodulated and outputting phase mutation information, and the phase mutation information is a discrete sequence with the same rate as the sampling rate of the AD sampling module and has the shape of a pulse when the phase mutation occurs;
the constellation rotation and data inversion module is used for carrying out pulse detection on the output sequence, rotating a constellation diagram according to the type of phase mutation in the pulse detection to obtain a constellation position corresponding to a current code element, and inverting the IQ two-way data line according to the constellation position corresponding to the current code element to obtain an IQ two-way data waveform;
and the synchronous output module is used for sampling the IQ two-path data waveform according to the code rate, and generating and outputting demodulation data.
2. The demodulator of claim 1, further comprising: and the PCIe interaction module is used for inputting the network parameters into the FPGA.
3. The demodulator of claim 2, further comprising: and the parameter storage module is used for receiving, storing and forwarding the network parameters.
4. The demodulator according to claim 1, wherein the one-dimensional convolutional neural network comprises: an input layer, a convolutional layer, an implicit layer and an output layer, and auxiliary input buffer, output buffer and control module.
5. A control method of a QPSK neural network demodulator based on FPGA is characterized by comprising the following steps:
sending a clock signal and a reset signal;
sampling a signal to be demodulated to obtain sampling data;
receiving and buffering the sampling data, and performing clock domain conversion on the sampling data;
detecting three relative phase changes of pi/2 type, -pi/2 type and pi type in the sampling data after clock domain conversion, and outputting phase mutation information, wherein the phase mutation information is a discrete sequence with the same rate as the sampling rate of the AD sampling module, and has the shape of a pulse when the phase mutation occurs;
performing pulse detection on the output sequence, rotating a constellation diagram according to the type of phase mutation in the pulse detection to obtain a constellation position corresponding to a current code element, and turning the IQ two-way data line according to the constellation position corresponding to the current code element to obtain an IQ two-way data waveform;
and sampling the IQ two-path data waveform according to the code rate, and generating and outputting demodulation data.
6. The method of claim 5, further comprising, prior to sending the clock signal and the reset signal: and storing the network parameters to a parameter storage module.
7. The method of claim 5, prior to acquiring sample data for the signal samples to be demodulated, further comprising: the network parameters are input to the FPGA.
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