CN109979991A - A kind of photoetching process, T shape grid and transistor based on I-line and EBL production T shape grid - Google Patents
A kind of photoetching process, T shape grid and transistor based on I-line and EBL production T shape grid Download PDFInfo
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- CN109979991A CN109979991A CN201910305250.9A CN201910305250A CN109979991A CN 109979991 A CN109979991 A CN 109979991A CN 201910305250 A CN201910305250 A CN 201910305250A CN 109979991 A CN109979991 A CN 109979991A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000001259 photo etching Methods 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000003153 chemical reaction reagent Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000000926 separation method Methods 0.000 claims abstract description 9
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 238000011161 development Methods 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 239000004568 cement Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 abstract description 18
- 239000002904 solvent Substances 0.000 abstract description 12
- 238000000609 electron-beam lithography Methods 0.000 description 11
- 239000003292 glue Substances 0.000 description 8
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002893 slag Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a kind of photoetching process, T shape grid and transistor based on I-line and EBL production T shape grid, technique the following steps are included: be coated that E-beam photoresist is toasted, EBL photoetching, development, cleaning form lower layer's root cavity on a semiconductor substrate；Baking thermal deformation is carried out to lower layer's root cavity photoresist layer, forms lower layer's root cavity with circular arc corner；Use O2Remove the bottom residues of lower layer root cavity；Separation layer is formed in lower layer's root cavity and semiconductor substrate surface coating isolation reagent；Lower layer's root housing surface be coated upper layer photoresist and toasted, I-line photo-etching machine exposal, development, cleaning form upper layer head cavity；Use O2The bottom residues for removing lower layer root cavity and the separation layer above semiconductor substrate.The present invention saves the time required for the photoetching of electron beam scanning exposure machine, and a large amount of influence of the solvent to lower layer is isolated in the photoresist of upper layer head.
Description
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of photoetching works based on I-line and EBL production T shape grid
Skill, T shape grid and transistor.
Background technique
In the semiconductor technology for influencing PHEMT device performance, the production of grid is the most difficult.In order to improve the work of device
Working frequency, it is necessary to constantly reduce grid length.Grid length size has reached deep-submicron even nanometer level at present, but grid length subtracts
Some other problem, the mainly increase of gate resistance can be brought while small, need to make T shape grid thus to reduce since grid are posted
Transistor noise caused by raw resistance.
There are two ways to making T shape grid with electron beam scanning exposure machine technique at present: one is make on semiconductor substrate
It is all exposed by electronics beam scanning with two layers of E-beam photoresist, that is, lower layer's root cavity and two layer pattern of upper layer head cavity
Ray machine technique is completed.Electron beam scanning exposure machine needs to complete third photo etching to manufacture T shape grid in the method, and lower layer is primary, on
Layer is twice (for upper layer pattern on the both sides of lower layer pattern, one side photoetching is primary).Compared to the litho machines such as I-line and DUV, electronics
The beam scanning exposure machine photoetching time is long, and electron beam scanning exposure machine is sufficiently expensive, and low efficiency cost is big in this way for institute.It is another
Kind of method is: lower layer is E-beam glue, upper layer DUV glue, as shown in Figure 1.Namely head cavity figure in upper layer gives DUV photoetching
Machine technique is completed, and electron beam scanning exposure machine technique only needs to do the cavity figure of one layer of lower layer root.This method can solve
A kind of problem that the method bring photoetching time is long, but a large amount of solvent can be to lower layer's root cavity figure in the DUV glue on upper layer
It impacts, characteristic size can be made to deform.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of based on I-line and EBL production T shape grid
Photoetching process, T shape grid and high electron mobility transistor.
The purpose of the present invention is achieved through the following technical solutions:
According to a first aspect of the present application, a kind of photoetching process based on I-line and EBL production T shape grid is provided, including
Following steps:
It is coated that E-beam photoresist is toasted, EBL photoetching, development, cleaning form lower layer on a semiconductor substrate
Root cavity；
Baking thermal deformation is carried out to lower layer's root cavity photoresist layer, forms lower layer's root cavity with circular arc corner；
Use O2Remove the bottom residues of lower layer root cavity；
Separation layer is formed in lower layer's root cavity and semiconductor substrate surface coating isolation reagent；
Lower layer's root housing surface be coated upper layer photoresist and toasted, I-line photo-etching machine exposal, development,
Cleaning forms upper layer head cavity；
Use O2The bottom residues for removing lower layer root cavity and the separation layer above semiconductor substrate；
The semiconductor substrate under layer root cavity is fallen down with acid etch, under the at T-shaped grid of semiconductor substrate surface shape
Layer root figure；
Deposit gate metal layer；
T shape grid are obtained with all optical cements of reagent removal semiconductor substrate surface.
Further, the isolation reagent is peace intelligence electronics SH114.
Further, narrower than the estimated T shape grid formed when forming lower layer's root cavity with circular arc corner；Make
Use O2When removing the bottom residues of lower layer root cavity, checkout time is controlled, a part of lower layer root cavity is disposed.
Further, the characteristic size of the lower layer root for obtaining T shape grid is 0.15um, has circular arc corner being formed
Lower layer's root cavity when, the relative size of bottom is 0.13um；Using O2When removing the bottom residues of lower layer root cavity,
Checkout time is controlled, a part of lower layer root cavity is disposed, so that the relative size of bottom reaches 0.15um.
Further, the technique further include:
The different checkout times under special parameter are obtained, lower layer's root cavity widens distance；
Distance is widened according to actually required, obtains narrow space lower layer root cavity to width lower layer root cavity in special parameter
Under checkout time.
Further, different checkout times of the acquisition under special parameter, lower layer's root cavity widen distance, also
Include:
It is widened according to multiple as a result, establishing linear model, the linear model is used in input special parameter and practical institute
Need to widen apart from when export checkout time.
Further, the deposition gate metal layer is realized using vacuum vapour deposition.
Further, described to obtain the reagent in T shape grid with all optical cement of reagent removal semiconductor substrate surface and be
NMP。
According to a second aspect of the present application, a kind of T shape grid are provided, are manufactured using the photoetching process.
According to the third aspect of the application, a kind of high electron mobility transistor is provided, including the T shape grid.
The beneficial effects of the present invention are:
(1) present invention forms lower layer root cavity figure using electron beam scanning exposure machine technique on a semiconductor substrate,
Upper layer head cavity figure is formed using I-line technique, to save the time required for electron beam scanning exposure machine photoetching；
It is that can first do a step isolation processing before doing I-line technique simultaneously, to be isolated in the photoresist of upper layer head a large amount of molten
Influence of the agent to lower layer.
(2) present invention completes lower layer root cavity and when the head cavity of upper layer, is all made of ion and removes photoresist that remove bottom residual
Slag enables subsequent technique that figure perfection is made to approach ideal form, rather than it is scarce to cause figure to have because of the influence of residue
Mouthful, to influence the characteristic size and pattern of product, and then influence electrical property.
(3) since ion step of removing photoresist can destroy a part of lower layer root cavity, there is circular arc corner being formed
Narrower than the estimated T shape grid formed when lower layer's root cavity, so that subsequent ion removes photoresist, it is residual can not only to remove bottom for step
Slag can also make lower layer's root cavity after the completion of removing photoresist meet size characteristic requirement.
(4) ion of the application step of removing photoresist is located at before isolation step, and prior art step of removing photoresist is avoided to walk in isolation
The problem for making isolation effect bad after rapid.
Detailed description of the invention
Fig. 1 is the schematic diagram of prior art one of which way；
Fig. 2 is process flow chart of the invention；
Fig. 3 is the corresponding operation chart of process flow；
Fig. 4 is T shape grid schematic diagram.
Specific embodiment
Technical solution of the present invention is clearly and completely described with reference to the accompanying drawing, it is clear that described embodiment
It is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.This
Outside, technical characteristic involved in invention described below different embodiments as long as they do not conflict with each other can
To be combined with each other.
There are two ways to making T shape grid with electron beam scanning exposure machine technique at present: one is make on semiconductor substrate
It is all exposed by electronics beam scanning with two layers of E-beam photoresist, that is, lower layer's root cavity and two layer pattern of upper layer head cavity
Ray machine technique is completed.Electron beam scanning exposure machine needs to complete third photo etching to manufacture T shape grid in the method, and lower layer is primary, on
Layer is twice (for upper layer pattern on the both sides of lower layer pattern, one side photoetching is primary).Compared to the litho machines such as I-line and DUV, electronics
The beam scanning exposure machine photoetching time is long, and electron beam scanning exposure machine is sufficiently expensive, and low efficiency cost is big in this way for institute.It is another
Kind of method is: lower layer is E-beam glue, upper layer DUV glue, as shown in Figure 1.Namely head cavity figure in upper layer gives DUV photoetching
Machine technique is completed, and electron beam scanning exposure machine technique only needs to do the cavity figure of one layer of lower layer root.This method can solve
A kind of problem that the method bring photoetching time is long, but a large amount of solvent can be to lower layer's root cavity figure in the DUV glue on upper layer
It impacts, characteristic size can be made to deform.
In view of this, the application be intended to provide it is a kind of based on the I-line and EBL production photoetching process of T shape grid, T shape grid and
Transistor forms lower layer root cavity using electron beam scanning exposure machine technique on a semiconductor substrate, uses I-line technique
Upper layer head cavity is formed, to save the time required for electron beam scanning exposure machine photoetching；It is simultaneously to do I-line work
Before skill, a step isolation processing first is done with reagent, so that a large amount of influence of the solvent to lower layer be isolated in the photoresist of upper layer head.
Wherein, the full name of EBL is electronbeam lithography, that is, electron beam exposure, refers to and utilizes certain macromolecules
Polymer forms exposure figure to electron sensitive, is the extension of photoetching technique.Electron beam exposure can be write on resist
Nanoscale figure out.And I-line
Referring to fig. 2, Fig. 2 is a kind of based on I-line and EBL production T shape grid shown in one exemplary embodiment of the application
The flow chart of photoetching process, this method are applied to the low cost and high quality production of T shape grid.Referring also to Fig. 3, Fig. 3 are technique
The corresponding operation chart of process.The photoetching process the following steps are included:
S1: it electron beam scanning exposure machine (EBL) technique: is coated E-beam photoresist (electronics on a semiconductor substrate
Beam photoresist) toasted, EBL photoetching, development, cleaning form lower layer's root cavity, as shown in Fig. 3 (a) and Fig. 3 (b).
S2: thermal deformation: baking thermal deformation is carried out to lower layer's root cavity photoresist layer, forms the lower layer with circular arc corner
Root cavity, as shown in Fig. 3 (c).
S3: ion removes photoresist: using O2The bottom residues for removing lower layer root cavity, as shown in Fig. 3 (d).
S4: isolation: separation layer is formed in lower layer's root cavity and semiconductor substrate surface coating isolation reagent, such as Fig. 3 (e)
It is shown.
Wherein, reagent is used to that a large amount of influences of the solvent to lower layer to be isolated in photoresist used in subsequent I-line technique,
Solvent composition accounts for 90% or more in upper layer photoresist, and when being coated with glue, solvent can impact lower layer, can make lower layer's root cavity
Pattern character size deformation, so needing to be isolated.
In addition, the isolation reagent is peace intelligence electronics SH114 in the preferred embodiment of the present embodiment.
S5:I-line technique: upper layer photoresist is coated in lower layer's root housing surface and is toasted, I-line light
The exposure of quarter machine, development, cleaning form upper layer head cavity, as shown in Fig. 3 (f).
S6: ion removes photoresist: using O2The bottom residues for removing lower layer root cavity and the separation layer above semiconductor substrate,
As shown in Fig. 3 (g).
S7: lower layer's root figure is formed: the semiconductor substrate under layer root cavity is fallen down with acid etch, semiconductor-based
Lower layer's root figure of the at T-shaped grid of plate surface shape, as shown in Fig. 3 (h).
S8: deposition gate metal layer, as shown in Fig. 3 (i).
Wherein, in the preferred embodiment of the present embodiment, the deposition gate metal layer is steamed using vacuum in this step
Plating method is realized.
S9: T shape grid are obtained with all optical cements of reagent removal semiconductor substrate surface, as shown in Figure 4.
Wherein, in this step, the optical cement all with reagent removal semiconductor substrate surface obtains the examination in T shape grid
Agent is NMP.
The present embodiment forms lower layer root cavity figure using electron beam scanning exposure machine technique on a semiconductor substrate first
Shape forms upper layer head cavity figure using I-line technique, thus when saving required for electron beam scanning exposure machine photoetching
Between.
But a large amount of influences of the solvent to lower layer in photoresist used in I-line technique, solvent composition in upper layer photoresist
90% or more is accounted for, when being coated with glue, solvent can impact lower layer, and lower layer's root cavity pattern character size can be made to deform；Cause
This can first be a step isolation processing S4 before doing I-line technique, so that a large amount of solvent in the photoresist of upper layer head be isolated
Influence to lower layer
Wherein, the definition of characteristic size refer to opposite lower layer's root cavity and semiconductor substrate contact position away from
From.
Wherein, the ion of the present embodiment step S3 that removes photoresist is located at before isolation step S4, can remove photoresist to avoid the prior art
The problem that step makes isolation effect bad after isolation steps.
Ion step of removing photoresist enables subsequent technique to make the perfect ideal form approached in Fig. 4 of figure, rather than because
Cause figure jagged for the influence of residue, to influence the characteristic size and pattern of product, and then influences electrical property.
Wherein, the ion of step S3 removes photoresist the bottom residues for lower layer's root cavity that step is removed, i.e., on semiconductor substrate
Bottom residues execute ion and remove photoresist and (use O but at this time due to just completing thermal deformation field2Remove lower layer root cavity
Bottom residues) meeting is so that lower layer's root cavity (i.e. the part of E-beam photoresist) is also removed a part, therefore at this time excellent
Select in embodiment, in step S2 when forming lower layer's root cavity with circular arc corner, it is narrower than the estimated T shape grid formed；
And O is used in step s32When removing the bottom residues of lower layer root cavity, checkout time is controlled, a part of lower layer is disposed
Root cavity.And remove photoresist step for the ion of step S6, lower layer root cavity and upper layer head cavity are solid-state at this time, and
And solvent also toasts the similar of volatilization, ion, which removes photoresist, at this time can destroy separation layer, will not cause to appoint the two contact
What is influenced.
That is, remained to reduce bottom in production (it is inevitable, it is that actual production and theory have difference, to product
Performance is unfavorable), so just using O2It goes to beat, but characteristic size can be widened, therefore characteristic size does dot at the very start.
For example, in the present embodiment, the characteristic size of the lower layer root for obtaining T shape grid is 0.15um, have being formed
When having lower layer's root cavity of circular arc corner, the relative size of bottom is 0.13um；Using O2Remove lower layer root cavity
When bottom residues, checkout time is controlled, a part of lower layer root cavity is disposed, so that the relative size of bottom reaches
0.15um。
In addition, the realization based on above preferred embodiment, the technique further include:
S0: obtaining the different checkout times under special parameter, and lower layer's root cavity widens distance；
Distance is widened according to actually required, obtains narrow space lower layer root cavity to width lower layer root cavity in special parameter
Under checkout time.
The step can be operated in advance, thus the acquisition in advance of the accomplished checkout time for expansion.
In addition, the realization based on above preferred embodiment, different checkout times of the acquisition under special parameter, lower layer
Root cavity widens distance, further includes:
It is widened according to multiple as a result, establishing linear model, the linear model is used in input special parameter and practical institute
Need to widen apart from when export checkout time.
Wherein, linear model can be multiple, respectively represent the linear model under different special parameters.
The another exemplary embodiment of the application provides a kind of T shape grid, is manufactured using the photoetching process.
The another exemplary embodiment of the application provides a kind of high electron mobility transistor, including the T shape
Grid.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments, right
For those of ordinary skill in the art, can also make on the basis of the above description other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And thus amplify out it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of photoetching process based on I-line and EBL production T shape grid, it is characterised in that: the following steps are included:
It is coated that E-beam photoresist is toasted, EBL photoetching, development, cleaning form lower layer root on a semiconductor substrate
Cavity；
Baking thermal deformation is carried out to lower layer's root cavity photoresist layer, forms lower layer's root cavity with circular arc corner；
Use O2Remove the bottom residues of lower layer root cavity；
Separation layer is formed in lower layer's root cavity and semiconductor substrate surface coating isolation reagent；
Upper layer photoresist is coated in lower layer's root housing surface and is toasted, I-line photo-etching machine exposal, development, cleaning
Form upper layer head cavity；
Use O2The bottom residues for removing lower layer root cavity and the separation layer above semiconductor substrate；
The semiconductor substrate under layer root cavity is fallen down with acid etch, in lower layer's root of the at T-shaped grid of semiconductor substrate surface shape
Portion's figure；
Deposit gate metal layer；
T shape grid are obtained with all optical cements of reagent removal semiconductor substrate surface.
2. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 1, it is characterised in that: institute
The isolation reagent stated is peace intelligence electronics SH114.
3. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 1, it is characterised in that:
It is narrower than the estimated T shape grid formed when forming lower layer's root cavity with circular arc corner；Using O2Remove lower layer root cavity
Bottom residues when, control checkout time, dispose a part of lower layer root cavity.
4. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 3, it is characterised in that: institute
The characteristic size for stating to obtain the lower layer root of T shape grid is 0.15um, when forming lower layer's root cavity with circular arc corner, bottom
The relative size in portion is 0.13um；Using O2When removing the bottom residues of lower layer root cavity, checkout time is controlled, is disposed
A part of lower layer root cavity, so that the relative size of bottom reaches 0.15um.
5. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 3 or 4, feature exist
In: the technique further include:
The different checkout times under special parameter are obtained, lower layer's root cavity widens distance；
Distance is widened according to actually required, obtains narrow space lower layer root cavity to width lower layer root cavity under special parameter
Checkout time.
6. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 5, it is characterised in that: institute
The different checkout times obtained under special parameter are stated, lower layer's root cavity widens distance, further includes:
It is widened according to multiple as a result, establish linear model, the linear model is used in input special parameter and actually required opens up
Width from when export checkout time.
7. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 1, it is characterised in that: institute
Deposition gate metal layer is stated to realize using vacuum vapour deposition.
8. a kind of photoetching process based on I-line and EBL production T shape grid according to claim 1, it is characterised in that: institute
Stating and obtaining the reagent in T shape grid with all optical cements of reagent removal semiconductor substrate surface is NMP.
9. a kind of T shape grid, it is characterised in that: manufactured using the photoetching process as described in any one of claim 1~8.
10. a kind of high electron mobility transistor, it is characterised in that: including T shape grid as claimed in claim 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110718456A (en) * | 2019-10-22 | 2020-01-21 | 成都海威华芯科技有限公司 | High-reliability T-shaped gate manufacturing method, T-shaped gate and high-electron-mobility transistor |
| CN110729181A (en) * | 2019-10-22 | 2020-01-24 | 成都海威华芯科技有限公司 | Manufacturing method of high-electron-mobility transistor T-shaped gate, T-shaped gate and transistor |
| CN112864004A (en) * | 2021-01-04 | 2021-05-28 | 湘潭大学 | Method for solving burrs and photoresist removal residues in film coating process of photoetching process |
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| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
| CN109103245A (en) * | 2018-07-26 | 2018-12-28 | 厦门市三安集成电路有限公司 | A kind of double-T shaped grid and production method and application |
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| CN110718456A (en) * | 2019-10-22 | 2020-01-21 | 成都海威华芯科技有限公司 | High-reliability T-shaped gate manufacturing method, T-shaped gate and high-electron-mobility transistor |
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