CN109979939B - Semiconductor memory device structure and manufacturing method thereof - Google Patents
Semiconductor memory device structure and manufacturing method thereof Download PDFInfo
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- CN109979939B CN109979939B CN201711439945.3A CN201711439945A CN109979939B CN 109979939 B CN109979939 B CN 109979939B CN 201711439945 A CN201711439945 A CN 201711439945A CN 109979939 B CN109979939 B CN 109979939B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Abstract
The invention provides a semiconductor memory device structure and a manufacturing method thereof, wherein the structure comprises: the semiconductor substrate is provided with a plurality of groove isolation structures extending in a wave shape, and a plurality of active regions extending in the wave shape are isolated by the groove isolation structures; the word line intersects the active region, the word line can include the virtual word line and plans to put the word line, have source region and drain region in the active region of both sides edge of the virtual word line; bit line contacts are formed on the drain regions; bit lines are formed on the bit line contacts and intersect the word lines. The invention forms a wave-shaped active area and a word line crossed with the active area, and the word line to be arranged can be used as an isolation groove after voltage is introduced, so that the active area is divided into a plurality of active area units. Compared with the traditional shallow trench isolation structure, the word line to be arranged can greatly reduce the space between two virtual word lines adjacent to the word line to be arranged.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor memory device structure and a manufacturing method thereof.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor 10 and a transistor 11; the gate of transistor 11 is connected to word line 13, the drain/source of transistor 11 is connected to bit line 12, the source/drain of transistor 11 is connected to capacitor 10; the voltage signal on the word line 13 can control the transistor 11 to be turned on or off, so as to read the data information stored in the capacitor 10 through the bit line 12, or write the data information into the capacitor 10 through the bit line 12 for storage, as shown in fig. 1.
Three features need to be defined on pitch under the array pattern level: two word lines over the field and a grounded gate. Generally, the maximum density of the grounded gate parallel pattern on the field is required to ensure that a linear self-aligned contact etch can be performed to form cavities for the plug conductive storage and contact active area, in which case conventional pitch doubling is not effective because the correct gap for word line to word line and grounded gate cannot be defined with respect to each patterned pitch doubled feature. More importantly, the conventional formation of isolation trenches between word lines requires separate etching of isolation trenches in the substrate and filling of the isolation trenches with insulating material to prevent leakage of the word lines, which requires a significant increase in process cost and is detrimental to process efficiency.
Based on the above, it is necessary to provide a semiconductor memory device structure and a method for manufacturing the same, in which the word lines with the same pitch can be doubled and the manufacturing cost of the isolation trenches can be effectively reduced.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor memory device structure and a method for fabricating the same, which can realize the pitch doubling of the equally spaced word lines and can effectively reduce the fabrication cost of the isolation trenches.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor memory device structure, the method comprising: 1) providing a semiconductor substrate, forming a plurality of groove isolation structures extending in a wave shape in the semiconductor substrate, and isolating a plurality of active regions extending in the wave shape in the semiconductor substrate by the groove isolation structures; 2) forming a word line in the semiconductor substrate, the word line intersecting the active region, the word line including a virtual word line and a dummy word line; 3) respectively forming a source region and a drain region in the active regions at two side edges of the virtual word line; 4) forming a bit line contact on the drain region; and 5) forming a bit line on the bit line contact, the bit line intersecting the word line.
Preferably, in step 2), the word line to be placed includes an isolation word line, the isolation word line is supplied with voltage to serve as a short-side isolation trench for spacing the active region, and both side edges of the isolation word line are not provided with bit line contacts.
Furthermore, every two adjacent isolation word lines separate an active area unit from the active area, each active area unit intersects with two spaced virtual word lines, and the two spaced virtual word lines share one drain region; in the step 1), the trench isolation structure is used as a long-edge isolation trench for spacing the active area unit; in step 2), the isolation word line is used as a short side isolation trench for spacing the active area unit.
Preferably, any one of peaks and any one of valleys of the active region extending in a wave shape crosses the isolation word line.
Preferably, in step 1), the trench isolation structures are arranged at equal intervals, so that the active regions extending in a wave shape are arranged at equal intervals.
Preferably, the word lines are arranged at equal intervals, the bit lines are arranged at equal intervals, and the bit lines include a distribution vertically crossing the word lines, so as to reduce the length of the bit lines and reduce the parasitic capacitance.
Preferably, step 2) comprises: 2-1) forming a word line trench in the semiconductor substrate, the word line trench intersecting the active region; 2-2) forming a first dielectric layer at the bottom and the side wall of the word line groove; 2-3) filling a conductive material layer in the word line groove, and etching the conductive material layer to enable the top surface of the conductive material layer to be lower than the top surface of the semiconductor substrate to form a groove; and 2-4) filling a second dielectric layer in the groove to bury the conductive material layer.
Preferably, the dummy word line is used to achieve a pitch doubling of two substantial word lines adjacent to the dummy word line.
The present invention also provides a semiconductor memory device structure comprising: the semiconductor substrate is provided with a plurality of groove isolation structures extending in a wave shape, and a plurality of active regions extending in the wave shape are isolated in the semiconductor substrate through the groove isolation structures; the word line is formed in the semiconductor substrate and is intersected with the active region, the word line comprises a virtual word line and a virtual word line, and the active region on two side edges of the virtual word line is provided with a source region and a drain region; bit line contacts formed on the drain regions; and bit lines formed on the bit line contacts and crossing the word lines.
Preferably, the word line to be placed comprises an isolation word line, the isolation word line is electrified with voltage to serve as an isolation groove for separating the active regions, and two side edges of the isolation word line are not provided with bit line contacts.
Preferably, every two adjacent isolation word lines separate an active area unit from the active area, each active area unit intersects with two spaced virtual word lines, and the two spaced virtual word lines share one drain region; the groove isolation structure is used as a long-edge isolation groove for isolating the active area unit; the isolation word lines serve as short side isolation trenches that space the active area cells.
Preferably, any one of peaks and any one of valleys of the active region extending in a wave shape crosses the isolation word line.
Preferably, the trench isolation structures are arranged at equal intervals, so that the active regions extending in a wave shape are arranged at equal intervals.
Preferably, the word lines are arranged at equal intervals, the bit lines are arranged at equal intervals, and the bit lines include a distribution vertically crossing the word lines, so as to reduce the length of the bit lines and reduce the parasitic capacitance.
Preferably, a word line trench is formed in the semiconductor substrate, the word line trench intersecting the active region; the word line includes: the first dielectric layer is formed at the bottom and the side wall of the word line groove; the conductive material layer is filled in the word line groove, and the top surface of the conductive material layer is lower than the top surface of the semiconductor substrate so as to form a groove; and the second dielectric layer is filled in the groove to bury the conductive material layer.
Preferably, the dummy word line is used to achieve a pitch doubling of two substantial word lines adjacent to the dummy word line.
As described above, the semiconductor memory device structure and the manufacturing method thereof of the present invention have the following advantages:
the invention can form a plurality of wave-shaped extended active regions and word lines with equal intervals crossed with the active regions, wherein the word lines comprise substantial word lines and quasi word lines, and the quasi word lines can be used as isolation grooves to separate the active regions into a plurality of active region units after voltage is applied to the quasi word lines.
Compared with the traditional Shallow Trench Isolation (STI), the quasi word line can greatly reduce the space between two virtual word lines adjacent to the quasi word line, and the space between two virtual word lines adjacent to the quasi word line is doubled.
Drawings
Fig. 1 is a schematic circuit diagram of a semiconductor memory according to the prior art.
Fig. 2 to 10 are schematic structural diagrams showing steps of a method for manufacturing a semiconductor memory device structure according to a first embodiment of the present invention, in which fig. 3 corresponds to fig. 2, and fig. 7 corresponds to fig. 6.
Fig. 11 is a diagram showing an equivalent circuit structure of the semiconductor memory device structure of fig. 10 according to an embodiment of the present invention.
Fig. 12 to 13 are schematic structural diagrams illustrating 2 times of pitch doubling of equally spaced word lines in a semiconductor memory device structure according to a second embodiment of the present invention, wherein fig. 13 is a schematic structural diagram illustrating a cross-section of fig. 12 at a-a' in the semiconductor substrate.
Fig. 14 is a diagram showing an equivalent circuit structure of the semiconductor memory device structure in fig. 12 according to the second embodiment of the present invention.
Fig. 15 is a schematic structural diagram showing 3 times of pitch doubling of equally spaced word lines in the semiconductor memory device structure according to the third embodiment of the present invention.
Description of the element reference numerals
10 capacitors;
11 a transistor;
12 bit lines;
13 word lines;
101 a semiconductor substrate;
102 a trench isolation structure;
103 an active region;
104 placing a word line;
105 a virtual word line;
106 source region;
107 drain regions;
108 bit line contacts;
109 bit lines;
110 active area cells;
201 peak;
202 wave trough;
301 a word line trench;
302 a first dielectric layer;
303 a layer of conductive material;
304 grooves;
305 a second dielectric layer;
a. b, c active area;
A. b, C circuit.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2-15. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 2 to 15, the present embodiment provides a method for fabricating a semiconductor memory device structure, the method comprising:
as shown in fig. 2 to fig. 3, wherein fig. 3 is a schematic cross-sectional view taken along a-a' in fig. 2, step 1) is first performed to provide a semiconductor substrate 101, form a plurality of trenches extending in a wave shape in the semiconductor substrate 101, fill the trenches with an insulating layer to form a trench isolation structure 102, and isolate a plurality of active regions 103 extending in a wave shape in the semiconductor substrate 101 by the trench isolation structure 102.
The semiconductor substrate 101 includes a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, and the like, and in this embodiment, the semiconductor substrate 101 may include a silicon substrate.
Forming a plurality of wavelike extending grooves in the semiconductor substrate 101 by adopting a photoetching process and a plasma dry etching process, then forming a silicon dioxide layer at the bottom and on the surface of the groove by adopting a thermal oxidation process, then filling an insulating layer in the groove by adopting plasma enhanced chemical vapor deposition, wherein the material of the insulating layer can comprise silicon dioxide or silicon nitride and the like, and finally carrying out planarization treatment by adopting a chemical mechanical planarization or etching process until the top surface of the insulating layer is flush with the top surface of the semiconductor substrate 101 so as to form a groove isolation structure 102.
A plurality of active regions 103 extending in a wave shape are isolated in the semiconductor substrate 101 by the trench isolation structure 102. Preferably, the trench isolation structures 102 are arranged at equal intervals, so that the active regions 103 extending in a wave shape are arranged at equal intervals.
As shown in fig. 4 to 7, fig. 7 is a schematic cross-sectional view taken along line a-a' in fig. 6, and then step 2) is performed to form word lines in the semiconductor substrate 101, where the word lines intersect with the active regions 103, and the word lines include the virtual word lines 105 and the dummy word lines 104.
Specifically, the word line includes a transistor word line, and the step 2) includes:
as shown in fig. 4, step 2-1) is performed first, a word line trench 301 is formed in the semiconductor substrate 101 by using a photolithography process and a plasma dry etching process, where the word line trench 301 intersects with the active region 103 and the trench isolation structure 102.
As shown in fig. 5, steps 2-2) and 2-3) are performed, a first dielectric layer 302 is formed on the bottom and the sidewall of the word line trench 301, a conductive material layer 303 is filled in the word line trench 301, and the conductive material layer 303 is etched to make the top surface thereof lower than the top surface of the semiconductor substrate 101, so as to form a recess 304.
For example, a thermal oxidation process is used to form a silicon dioxide layer on the bottom and the sidewall of the word line trench 301 as the first dielectric layer 302, the first dielectric layer 302 is used as a gate dielectric layer of the transistor word line, then a titanium nitride adhesion layer and a tungsten wire layer are filled in the word line trench 301 as the conductive material layer 303, the conductive material layer 303 is planarized, and an etching process is used to etch the top surface of the conductive material layer 303 to be lower than the top surface of the semiconductor substrate 101, so as to form a groove 304.
As shown in fig. 6 and 7, step 2-4) is finally performed to fill the recess 304 with a second dielectric layer 305 to bury the conductive material layer 303.
For example, silicon dioxide is filled in the groove 304 by a chemical vapor deposition method to serve as the second dielectric layer 305, so as to bury the conductive material layer 303.
As shown in fig. 6 and 7, the word line 104 includes an isolation word line, a voltage is applied to the isolation word line to serve as a short-side isolation trench for separating the active region 103, and the isolation word line does not have a bit line contact 108 on both edges thereof. In the present embodiment, the voltage includes a negative voltage.
As shown in fig. 6 and fig. 7, every two adjacent isolation word lines isolate an active area unit 110 in the active area 103, each active area unit 110 crosses two spaced apart virtual word lines 105, the two spaced apart virtual word lines 105 share one drain region 107, and in step 1), the trench isolation structure 102 serves as a long-side isolation trench that separates the active area units 110; in step 2), the isolation word line is used as a short side isolation trench that separates the active area units 110.
Any peak 201 and any valley 202 of the active region 103 extending in a wave shape cross the isolation word line.
Preferably, the word lines are arranged at equal intervals, and the dummy word line 104 can double the interval between two virtual word lines 105 adjacent to the dummy word line 104.
The invention forms word lines with equal intervals and crossed with the active area 103, the word lines comprise virtual word lines 105 and dummy word lines 104, and after voltage is applied to the dummy word lines 104, the dummy word lines can be used as isolation trenches to divide the active area 103 into a plurality of active area units 110. Compared with the conventional shallow trench isolation structure 102(STI) which needs to occupy a larger area, the isolation word line of the present invention can greatly reduce the space between two virtual word lines 105 adjacent to the isolation word line, thereby achieving the double space between two virtual word lines 105 adjacent to the dummy word line 104.
As shown in fig. 8, step 3) is performed to form a source region 106 and a drain region 107 in the active regions 103 on both side edges of the real word line 105, respectively.
In this embodiment, the word line is used as a self-aligned mask, and an ion implantation process is performed to form a source region 106 and a drain region 107 in the active region 103 on both side edges of the substantial word line 105.
As shown in fig. 9, step 4) is then performed to form bit line contacts 108 on the drain regions 107.
As an example, an isolation layer is formed on the surface of the semiconductor substrate 101, a through hole exposing the drain region 107 is formed in the isolation layer by using a photolithography-etching process, then a conductive layer is filled in the through hole, and the bit line contact 108 is formed after the conductive layer is planarized.
As shown in fig. 10 to 11, wherein fig. 11 is a diagram showing an equivalent circuit structure of the semiconductor memory device structure in fig. 10 (active regions a, B, and C in fig. 10 correspond to circuits a, B, and C in the circuit of fig. 11), step 5) is finally performed to form bit lines 109 on the bit line contacts 108, and the bit lines 109 cross the word lines.
As an example, the bit lines 109 are arranged at equal intervals, the word lines and the bit lines 109 may extend in a straight line, and the bit lines 109 and the word lines intersect perpendicularly. The invention realizes the reduction of the length of the bit line 109 by the arrangement of the wave-shaped active region 103 and the arrangement of the vertically crossed word line and the bit line 109, so as to greatly improve the integration density of the semiconductor memory structure.
As shown in fig. 12 to 15, wherein fig. 13 is a schematic diagram showing a cross-sectional structure in the semiconductor substrate 101 at a-a' in fig. 12, and fig. 14 is a schematic diagram showing an equivalent circuit structure of the semiconductor memory device structure in fig. 12 (active regions a, B, and C in fig. 12 correspond to circuits a, B, and C in the circuit of fig. 14), it is indicated that the equally spaced word lines of the present invention can be pitch-doubled a plurality of times, the number of times of doubling can be 2 or more; any peak 201 and any valley 202 of the active region 103 extending in a wave shape cross the isolation word line. Fig. 12 to 14 are schematic structural diagrams illustrating that the word lines with equal pitch can be pitch-doubled for multiple times, where the doubling time is equal to 2 times, and fig. 15 is a schematic structural diagram illustrating that the word lines with equal pitch can be pitch-doubled for multiple times, where the doubling time is equal to 3 times.
As shown in fig. 12 to 15, fig. 13 is a schematic cross-sectional structure diagram of the semiconductor substrate 101 at a-a' in fig. 12, and fig. 14 is a schematic equivalent circuit structure diagram of the semiconductor memory device structure in fig. 12, in which active region units 110 are separated by the isolation word line 104 between adjacent peaks 201 and troughs 202 of the active region 103 extending in a wave shape in the present embodiment. Any peak 201 and any valley 202 of the active region 103 extending in a wave shape cross the isolation word line 104. Fig. 12 to 14 show that the number of active region cells 110 separated by the isolation word line varies by one between adjacent peaks 201 and troughs 202 of the active region 103 extending in a wave shape, and fig. 15 shows that the number of active region cells 110 separated by the isolation word line varies by two between adjacent peaks 201 and troughs 202 of the active region 103 extending in a wave shape. As shown in fig. 2 to 15, the present embodiment also provides a semiconductor memory device structure including: a semiconductor substrate 101, word lines (combination of a virtual word line 105 and a dummy word line 104), bit line contacts 108, and bit lines 109.
The semiconductor substrate 101 has a plurality of trench isolation structures 102 extending in a wave shape, and a plurality of active regions 103 extending in a wave shape are isolated in the semiconductor substrate 101 by the trench isolation structures 102.
The semiconductor substrate 101 may include any one of a silicon substrate, a germanium substrate, a silicon carbide substrate, and the like, and in this embodiment, the semiconductor substrate 101 may include a silicon substrate.
Corresponding to the position of the trench isolation structure 102, a plurality of trenches extending in a wave shape are formed in the semiconductor substrate 101, the trench isolation structure 102 may include a silicon dioxide layer formed at the bottom and surface of the trench and an insulating layer filled in the trench, and the material of the insulating layer may include silicon dioxide or silicon nitride.
A plurality of active regions 103 extending in a wave shape are isolated in the semiconductor substrate 101 by the trench isolation structure 102. Preferably, the trench isolation structures 102 are arranged at equal intervals, so that the active regions 103 extending in a wave shape are arranged at equal intervals.
The word line is formed in the semiconductor substrate 101, the word line intersects the active region 103, the word line may include a virtual word line 105 and a dummy word line 104, and the active region 103 at both side edges of the virtual word line 105 has a source region 106 and a drain region 107.
As shown in fig. 7, as an example, the word line includes: a word line trench 301 formed in the semiconductor substrate 101, the word line trench 301 intersecting the active region 103; a first dielectric layer 302 formed on the bottom and sidewalls of the word line trench 301; a conductive material layer 303 filled in the word line trench 301, wherein a top surface of the conductive material layer 303 is lower than a top surface of the semiconductor substrate 101 to form a groove 304; and a second dielectric layer 305 filled in the groove 304 to bury the conductive material layer 303.
As shown in fig. 6 and 7, the word line 104 may include an isolation word line, which is applied with a voltage as an isolation trench separating the active region 103, and both edges of the isolation word line are not provided with bit line contacts 108, specifically, the voltage includes one of the group consisting of a negative voltage and a positive voltage, which can be selected according to different device types. In the present embodiment, the voltage includes a negative voltage.
As shown in fig. 6 and fig. 7, every two adjacent isolation word lines isolate an active area unit 110 in the active area 103, each active area unit 110 crosses two spaced apart virtual word lines 105, the two spaced apart virtual word lines 105 share one drain region 107, and the trench isolation structure 102 serves as a long-side isolation trench that separates the active area units 110; the isolation word line serves as a short side isolation trench that spaces the active area cells 110.
Any peak 201 and any valley 202 of the active region 103 extending in a wave shape cross the isolation word line.
Preferably, the word lines are arranged at equal intervals, and the dummy word line 104 can double the interval between two virtual word lines 105 adjacent to the dummy word line 104.
The invention forms word lines with equal space crossing the active area 103, the word lines can include a virtual word line 105 and a quasi word line 104, after the quasi word line 104 is electrified with voltage, the quasi word line can be used as an isolation groove to divide the active area 103 into a plurality of active area units 110. Compared with the conventional shallow trench isolation structure 102(STI) which needs to occupy a larger area, the isolation word line of the present invention can greatly reduce the space between two virtual word lines 105 adjacent to the isolation word line, thereby achieving the double space between two virtual word lines 105 adjacent to the dummy word line 104.
The present invention provides for forming equally spaced word lines intersecting the active region 103, which may include a virtual word line 105 and a dummy word line 104, which may be formed simultaneously by a single process.
The present invention provides for forming equally spaced word lines intersecting the active region 103, which may include a virtual word line 105 and a dummy word line 104, which may be pitch doubled a number of times, the number of times being greater than or equal to 2.
The bit line contact 108 is formed on the drain region 107.
Isolation layers are formed on the surface of the semiconductor substrate 101 on the virtual word lines 105, through holes are formed between adjacent isolation layers to expose the drain regions 107, and the bit line contacts 108 may include conductive layers in the through holes and on the drain regions 107.
The bit lines 109 are formed on the bit line contacts 108 and intersect the word lines.
As an example, the bit lines 109 are arranged at equal intervals, the word lines and the bit lines 109 may extend in a straight line, and the bit lines 109 and the word lines intersect perpendicularly. The invention can greatly improve the integration density of the semiconductor memory structure by arranging the wave-shaped active region 103 and arranging the vertically crossed word lines and bit lines 109.
As shown in fig. 12 to 15, wherein fig. 13 is a schematic diagram showing a cross-sectional structure in the semiconductor substrate 101 at a-a' of fig. 12, and fig. 14 is a schematic diagram showing an equivalent circuit structure of the semiconductor memory device structure of fig. 12, it is indicated that the equally spaced word lines of the present invention can be pitch-doubled a plurality of times, the number of times of doubling can be greater than or equal to 2; any peak 201 and any valley 202 of the active region 103 extending in a wave shape cross the isolation word line. Fig. 12 to 14 are schematic structural diagrams illustrating that the word lines with equal pitch can be pitch-doubled for multiple times, where the doubling time is equal to 2 times, and fig. 15 is a schematic structural diagram illustrating that the word lines with equal pitch can be pitch-doubled for multiple times, where the doubling time is equal to 3 times.
As described above, the semiconductor memory device structure and the manufacturing method thereof of the present invention have the following advantages:
the present invention can form a plurality of active regions 103 extending in a wave shape, and form word lines crossing the active regions 103 at equal intervals, where the word lines may include a substantial word line 105 and a dummy word line 104, and the dummy word line 104 may be used as an isolation trench after being applied with a voltage to partition the active regions 103 into a plurality of active region units 110.
Compared with the conventional shallow trench isolation structure 102(STI), the dummy word line 104 of the present invention can greatly reduce the space between two real word lines 105 adjacent to the dummy word line 104, and double the space between two real word lines 105 adjacent to the dummy word line 104.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for fabricating a semiconductor memory device structure, the method comprising:
1) providing a semiconductor substrate, forming a plurality of groove isolation structures extending in a wave shape in the semiconductor substrate, and isolating a plurality of active regions extending in the wave shape in the semiconductor substrate by the groove isolation structures;
2) forming a word line in the semiconductor substrate, the word line intersecting the active region, the word line including a virtual word line and a dummy word line;
3) respectively forming a source region and a drain region in the active regions at two side edges of the virtual word line;
4) forming a bit line contact on the drain region; and
5) forming a bit line on the bit line contact, the bit line crossing the word line;
the groove isolation structures are arranged at equal intervals, so that the active regions extending in a wave shape are arranged at equal intervals; the word lines are arranged at equal intervals, the bit lines are arranged at equal intervals, the word lines and the bit lines extend in a straight line, the bit lines are distributed in a mode of being vertically crossed with the word lines, and the active area between any adjacent wave crest and any adjacent wave trough at least comprises a virtual word line so as to divide the active area between any adjacent wave crest and any adjacent wave trough into at least two active units.
2. The method of fabricating a semiconductor memory device structure of claim 1, wherein: in the step 2), the word line to be arranged comprises an isolation word line, voltage is introduced into the isolation word line to serve as a short-side isolation groove for separating the active region, and bit line contact points are not arranged on two side edges of the isolation word line.
3. The method of fabricating a semiconductor memory device structure according to claim 2, wherein: every two adjacent isolation word lines separate an active area unit from the active area, each active area unit is crossed with two virtual word lines which are arranged at intervals, and the two virtual word lines which are arranged at intervals share one drain region; in the step 1), the trench isolation structure is used as a long-edge isolation trench for spacing the active area unit; in step 2), the isolation word line is used as a short side isolation trench for spacing the active area unit.
4. The method of fabricating a semiconductor memory device structure according to claim 2, wherein: any wave crest and any wave trough of the active region extending in a wave shape are crossed with the isolation word line.
5. The method of fabricating a semiconductor memory device structure of claim 1, wherein: the step 2) comprises the following steps:
2-1) forming a word line trench in the semiconductor substrate, the word line trench intersecting the active region;
2-2) forming a first dielectric layer at the bottom and the side wall of the word line groove;
2-3) filling a conductive material layer in the word line groove, and etching the conductive material layer to enable the top surface of the conductive material layer to be lower than the top surface of the semiconductor substrate to form a groove; and
2-4) filling a second dielectric layer in the groove to bury the conductive material layer.
6. A semiconductor memory device structure, comprising:
the semiconductor substrate is provided with a plurality of groove isolation structures extending in a wave shape, and a plurality of active regions extending in the wave shape are isolated in the semiconductor substrate through the groove isolation structures;
the word line is formed in the semiconductor substrate and is intersected with the active region, the word line comprises a virtual word line and a virtual word line, and the active region on two side edges of the virtual word line is provided with a source region and a drain region;
bit line contacts formed on the drain regions; and
bit lines formed on the bit line contacts and crossing the word lines;
the groove isolation structures are arranged at equal intervals, so that the active regions extending in a wave shape are arranged at equal intervals, the word lines are arranged at equal intervals, the bit lines are arranged at equal intervals, the word lines and the bit lines extend in a straight line, the bit lines are distributed in a manner of being vertically crossed with the word lines, and the active regions between any adjacent wave crests and any adjacent wave troughs at least comprise a virtual word line so as to divide the active regions between any adjacent wave crests and any adjacent wave troughs into at least two active units.
7. The semiconductor memory device structure of claim 6, wherein: the word lines to be arranged comprise isolation word lines, voltage is introduced into the isolation word lines to serve as short-side isolation grooves for separating the active regions, and bit line contact points are not arranged on two side edges of the isolation word lines.
8. The semiconductor memory device structure of claim 7, wherein: every two adjacent isolation word lines separate an active area unit from the active area, each active area unit is crossed with two virtual word lines which are arranged at intervals, and the two virtual word lines which are arranged at intervals share one drain region; the groove isolation structure is used as a long-edge isolation groove for isolating the active area unit; the isolation word lines serve as short side isolation trenches that space the active area cells.
9. The semiconductor memory device structure of claim 7, wherein: any wave crest and any wave trough of the active region extending in a wave shape are crossed with the isolation word line.
10. The semiconductor memory device structure of claim 6, wherein a word line trench is formed in the semiconductor substrate, the word line trench intersecting the active region, the word line comprising:
the first dielectric layer is formed at the bottom and the side wall of the word line groove;
the conductive material layer is filled in the word line groove, and the top surface of the conductive material layer is lower than the top surface of the semiconductor substrate so as to form a groove; and
and the second dielectric layer is filled in the groove to bury the conductive material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711439945.3A CN109979939B (en) | 2017-12-27 | 2017-12-27 | Semiconductor memory device structure and manufacturing method thereof |
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| US11792973B2 (en) | 2020-07-28 | 2023-10-17 | Changxin Memory Technologies, Inc. | Storage device and forming method having a strip-shaped bitline contact structure |
| CN114005791A (en) * | 2020-07-28 | 2022-02-01 | 长鑫存储技术有限公司 | Memory device and method of forming the same |
| CN114078779A (en) * | 2020-08-20 | 2022-02-22 | 长鑫存储技术有限公司 | Integrated circuit memory, manufacturing method thereof and semiconductor integrated circuit device |
| EP4068345A4 (en) | 2020-08-20 | 2023-08-02 | Changxin Memory Technologies, Inc. | Integrated circuit memory and preparation method therefor, and semiconductor integrated circuit device |
| CN115602607A (en) * | 2021-07-07 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Method for manufacturing semiconductor structure and semiconductor structure |
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