CN109979890A - Electronic packing piece and its preparation method - Google Patents
Electronic packing piece and its preparation method Download PDFInfo
- Publication number
- CN109979890A CN109979890A CN201711460307.XA CN201711460307A CN109979890A CN 109979890 A CN109979890 A CN 109979890A CN 201711460307 A CN201711460307 A CN 201711460307A CN 109979890 A CN109979890 A CN 109979890A
- Authority
- CN
- China
- Prior art keywords
- clad
- packing piece
- electronic packing
- piece according
- preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012856 packing Methods 0.000 title claims abstract description 58
- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 47
- 238000010276 construction Methods 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 14
- 230000005540 biological transmission Effects 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 7
- 238000005266 casting Methods 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 11
- 239000000084 colloidal system Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 238000006467 substitution reaction Methods 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000013043 chemical agent Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 241000713154 Toscana virus Species 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Abstract
A kind of electronic packing piece and its preparation method, the electronic packing piece includes: clad, is embedded into the clad and the electronic component with sensing area, multiple electric conductors for being arranged in the clad and on the clad and is electrically connected the line layer of the electric conductor, therefore it is set in the clad by by the electric conductor, to reduce process difficulty, and cost of manufacture can be saved.
Description
Technical field
The present invention relates to a kind of sensing device, in particular to a kind of electronic packing piece and its preparation method for having sensor chip.
Background technique
All develop towards toward light, thin, short, small contour aggregation degree direction in high-order electronic product, and as consumer is for hidden
Private emphasis degree is promoted, and many high-order electronic products have all loaded user's identification system, to increase data in electronic product
Safety, therefore the research and development of identification system and design be with consumer demand, and becomes one of electronic industry the main direction of development.
In existing biological identification device, such as finger scan inductor (Finger Print Sensor) or complementary metal
Oxide semiconductor (Complementary Metal-Oxide-Semiconductor, abbreviation CMOS) image sensor
(Image Sensor) is divided into the optical identification device of scan pattern according to scanning mode and detects the silicon wafer identification of trace quantity electric charge
Device.
Figure 1A is the diagrammatic cross-section for noting optical identification type encapsulating structure 1a.As shown in Figure 1A, encapsulating structure 1a is noted
Package substrate 10, one including one with multiple electric connection pads 100 be set on the package substrate 10 and have a sensing area A with
The sensor chip 11 of multiple electrode pads 110, the packing colloid 13 for coating the sensor chip 11 and one are set on sensing area A
The transmission element 14 of side.Specifically, it can be connect by soldered ball (not shown) on the downside of the package substrate 10 and set a circuit board (not shown), and
The electric connection pad 100 of 10 upside of package substrate and the electronic pads of the sensor chip 11 are electrically connected with multiple bonding wires 12
110, and the packing colloid 13 is formed on the package substrate 10 and coats those bonding wires 12, and the transmission element 14 has a groove
140 to accommodate the packing colloid 13 and the package substrate 10.
However, noting in encapsulating structure 1a, which is electrically connected the package substrate 10 using routing mode, because
And the arc height of those bonding wires 12 need to be considered, cause the height of the packing colloid 13 to be difficult to decrease, so that the packing colloid
13 can not be effectively reduced with the height L of the package substrate 10, cause the depth H of the groove 140 of the transmission element 14 that can not also reduce,
And then the electronic product of follow-up process is made to be difficult to meet light, thin, short, small demand.
Furthermore though the etchable sensor chip 11 configure the electronic pads 110 fringe region material to form recess portion B,
To reduce the arc height of those bonding wires 12, but the limited height dropped, and it the sensor chip 11 need to be etched could form recess portion
B causes cost of manufacture to greatly improve.
Therefore, the optical identification device exempted from routing mode is developed then.As shown in Figure 1B, encapsulating structure 1b use is noted
Silicon perforation (Through-silicon via, abbreviation TSV) processing procedure, forms more in the region of the electronic pads 110 of the sensor chip 11
A conductive column 111 through the sensor chip 11, to be electrically connected the electric connection of the package substrate 10 by the conductive column 111
The electronic pads 110 of pad 100 and the sensor chip 11, thus the packing colloid 13 is without coating bonding wire 12, therefore the packing colloid 13
It can be reduced with the height of the package substrate 10, and the depth of the groove 140 of the transmission element 14 can also reduce, thus the envelope can be reduced
The whole height of assembling structure 1b, and then the electronic product of follow-up process is made to meet light, thin, short, small demand.
However, noting in encapsulating structure 1b, which makes the conductive column 111 using TSV processing procedure, because of the conduction
Column 111 need to have the control of certain depth-to-width ratio, can just produce applicable conductive column 111, therefore process difficulty is high, often needs to consume
Take the cost of a large amount of processing times and chemical agent, thus is difficult to decrease cost of manufacture.
Furthermore the conductive column 111 is made so that mode of the copper material in perforation is electroplated, but the conductive column 111 need to have centainly
Depth-to-width ratio, therefore be difficult to maintain electroplating quality, for example, copper material recess or gas chamber (void) often occur in the perforation, cause
Keep the reliability of the conductive column 111 bad.
Therefore, how to overcome the above-mentioned variety of problems for noting technology, have become the project for wanting to solve at present in fact.
Summary of the invention
In view of the above-mentioned disadvantages for noting technology, the present invention provides a kind of electronic packing piece and its preparation method, can reduce system
Journey difficulty, and cost of manufacture can be saved.
Electronic packing piece of the invention, comprising: clad, with opposite first surface and second surface；Electronics member
Part is embedded on the inside of the first surface of the clad, and has the sensing area for exposing to the first surface；Line layer, shape
At on the clad；And electric conductor, it is formed in the clad and is connected to the first surface and second surface and electrical property
Connect the line layer, wherein the electric conductor includes filling material and the conduction material for surrounding the filling material.
The present invention also provides a kind of preparation methods of electronic packing piece, comprising: providing one has opposite first surface and second
The clad on surface, and an at least electronic component is embedded on the inside of the first surface of the clad, wherein the electronic component has
Expose to the sensing area of the first surface；And the electric conductor for being connected to the first surface and second surface is formed in the clad
In, and line layer is formed on the clad, so that the electric conductor is electrically connected the line layer, wherein the electric conductor includes filling
Material and the conduction material for surrounding the filling material.
In electronic packing piece above-mentioned and its preparation method, the material for forming the clad includes that casting die compound or bottom apply
Material.
In electronic packing piece above-mentioned and its preparation method, the first surface of the clad is flushed with the electronic component.
In electronic packing piece above-mentioned and its preparation method, the second surface of the clad can flush or uneven with the electronic component
It is flat.
In electronic packing piece above-mentioned and its preparation method, which is electrically connected the line layer.
In electronic packing piece above-mentioned and its preparation method, the processing procedure of the electric conductor includes: that multiple companies are formed in the clad
Lead to the perforation of the first surface and second surface；The conduction material is formed on the hole wall in the perforation；And form the filling material
To fill up the perforation in the perforation.For example, the perforation is formed by the way of machine drilling.
In electronic packing piece above-mentioned and its preparation method, the line layer is not formed on the sensing area.
It further include forming insulating protective layer in the first surface of the clad in electronic packing piece above-mentioned and its preparation method
On, and the line layer is covered, and the insulating protective layer has the opening of an exposed sensing area.
It further include setting transmission element on the first surface of the clad in electronic packing piece above-mentioned and its preparation method, with
The cover is on the sensing area.
It further include forming line construction on the second surface of the clad in electronic packing piece above-mentioned and its preparation method,
And the line construction is electrically connected the line layer.
From the foregoing, it will be observed that be mainly set in the clad by by electric conductor in electronic packing piece and its preparation method of the invention,
To be electrically connected the line layer by the electric conductor, therefore compared to TSV technology is noted, the present invention can make each according to depth-to-width ratio demand
The perforation of kind size, thus process difficulty can be reduced, to save the cost of a large amount of processing times and chemical agent, and then can save
Cost of manufacture simultaneously can improve yield.
Furthermore using the technology of machine drilling and resin consent, and cooperate patterning process, to avoid TSV processing procedure is noted
Plating filling perforation (copper post body) quality problem, therefore compared to the technology that notes, preparation method of the invention can effectively maintain the electric conductor
Quality, to promote the reliability of the electric conductor, and reduce production cost.
In addition, preparation method of the invention notes package substrate with the line layer (or the line construction) substitution, and led by this
Electric body substitution notes bonding wire, therefore compared to routing type encapsulating structure is noted, the Electronic Packaging can be greatly decreased in preparation method of the invention
The height of part enables the electronic product of follow-up process to meet light, thin, short, small to provide ultra-thin and inexpensive encapsulating structure
Demand.
Detailed description of the invention
Figure 1A is the schematic cross-sectional view for noting encapsulating structure；
Figure 1B is another schematic cross-sectional view for noting encapsulating structure；
Fig. 2A to Fig. 2 E is the schematic cross-sectional view of the preparation method of sensing packaging part of the invention；
Fig. 3 A is the schematic cross-sectional view of another embodiment of Fig. 2 E；
Fig. 3 B is the schematic cross-sectional view of another embodiment of Fig. 3 A；And
Fig. 4 is the schematic cross-sectional view of the other embodiments of Fig. 2 E.
Description of symbols
1a, 1b encapsulating structure
10 package substrates
100 electric connection pads
11 sensor chips
110,210,410 electronic pads
111 conductive columns
12 bonding wires
13 packing colloids
14,24,34 transmission elements
140,340 grooves
2,3a, 3b, 4 electronic packing piece
20 load-bearing parts
21,41 electronic components
21a, 41a sensing face
21b, 41b non-sensing face
22 electric conductors
220 conduction materials
221 filling materials
23 clads
23a first surface
23b second surface
230 perforation
Vacancy in 240
25 line constructions
25a first line layer
The second line layer of 25b
250 insulating layers
251 line parts
26 insulating protective layers
260 openings
27 conducting elements
30 circuit boards
A sensing area
B recess portion
L height
H depth.
Specific embodiment
Illustrate embodiments of the present invention by particular specific embodiment below, people skilled in the art can be by this theory
Bright book disclosure of that understands other advantages and technical effect of the invention easily.
It should be clear that structure depicted in this specification attached drawing, ratio, size etc., only to cooperate disclosed in specification
Content is not intended to limit the invention enforceable qualifications for the understanding and reading of people skilled in the art, therefore not
Has technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing institute of the present invention
Under the technical effect and achieved purpose that can generate, it should all still fall in technology contents disclosed in this invention and obtain and can cover
In range.Meanwhile cited such as "upper" in this specification, " first ", " second " and " one " term, be merely convenient to chat
That states is illustrated, rather than to limit the scope of the invention, relativeness is altered or modified, and is changing skill without essence
It is held in art, when being also considered as the enforceable scope of the present invention.
Fig. 2A to Fig. 2 E is the diagrammatic cross-section of the preparation method of sensing electronic packing piece 2 of the invention.
As shown in Figure 2 A, it in an at least electronic component 21 is arranged on a load-bearing part 20, re-forms a clad 23 and is held in this
To coat the electronic component 21 in holder 20.
In this present embodiment, which is inductance semiconductor chip, for example, becoming to detect biological volume charge
The sensor chip of change, temperature difference, pressure etc., more preferably identification of fingerprint chip.Specifically, which has opposite sense
Survey face 21a and non-sensing face 21b, sensing face 21a are incorporated into the load-bearing part 20, and have multiple electrodes on sensing face 21a
Pad 210 and a sensing area A, to carry out biological (fingerprint) identification by sensing area A received signal.
Furthermore the clad 23 has opposite first surface 23a and second surface 23b, and the electronic component 21 is embedded into
In in the first surface 23a of the clad 23, wherein the first surface 23a of the clad 23 flushes the sense of the electronic component 21
Survey face 21a.
In addition, the clad 23 is formed on the load-bearing part 20 with die cast, coating method or pressing mode, and formed
The material of the clad 23 is dielectric material, which can be epoxy resin (Epoxy), and the epoxy resin also includes casting
Mold compound (Molding Compound) or bottom coating (Primer), such as epoxy moldable resin (Epoxy Molding
Compound, abbreviation EMC), wherein the epoxy moldable resin contains charges (filler), and the charges content be 70 to
90wt%.
As shown in Figure 2 B, the load-bearing part 20 is removed, with the first surface 23a of the exposed clad 23 and the electronic component 21
Sensing face 21a.Then, the perforation of multiple connection first surface 23a and second surface 23b are formed in the clad 23
230。
In this present embodiment, which is formed by the way of machine drilling.
As shown in Figure 2 C, conduction material 220 is formed on the first surface 23a and second surface 23b of the clad 23, and this
Conduction material 220 more extends to form on the hole wall in the respectively perforation 230.Later, filling material 221 is formed in the respectively perforation 230
To fill up the remaining space of the respectively perforation 230.
In this present embodiment, the copper material which is formed with plating mode, and form the material of the filling material 221
For resin.
As shown in Figure 2 D, route redistribution layer (Redistribution layer, abbreviation RDL) processing procedure is carried out, that is, is patterned
The conduction material 220, to form first line layer 25a in the first surface 23a of the clad 23 and the sensing of the electronic component 21
On the 21a of face, and the second line layer 25b is formed on the second surface 23b of the clad 23, and the conduction material in the perforation 230
220 are used as electric conductor 22 with filling material 221, and first line layer 25a is made to be electrically connected the electronic pads 210 of the electronic component 21,
And the electric conductor 22 is made to be electrically connected the first line layer 25a and second line layer 25b.
In this present embodiment, with exposure development processing procedure cooperate etching mode, with formed the first line layer 25a and this second
Line layer 25b.Preferably, remove the conduction material 220 above the sensing area A of the sensing face 21a of the electronic component 21, make this first
Line layer 25a will not be formed on sensing area A.
As shown in Figure 2 E, insulating protective layer 26 is formed on the first surface 23a of the clad 23, and covers the First Line
Road floor 25a, and the insulating protective layer 26 has the opening 260 of an exposed sensing area A.
In this present embodiment, it can be formed multiple if the conducting element 27 of soldered ball is in second line layer in follow-up process
On 25b, can also be formed on demand a line construction 25 on the second surface 23b of the clad 23 to be electrically connected second line
On the floor 25b of road, it is incorporated into the conducting element 27 on the line construction 25, to enable the conducting element 27 be electrically connected the route knot
Structure 25.Specifically, which includes an at least insulating layer 250 and the line part 251 being formed in the insulating layer 250,
Wherein, which is electrically connected the second line layer 25b and the conducting element 27.
Furthermore the insulating layer 250 is formed in 23 top of clad with die cast, coating method or pressing mode, and
The material for forming the insulating layer 250 is dielectric material, which can be epoxy resin, and the epoxy resin also includes mold
Compound or bottom coating, such as epoxy moldable resin, wherein the epoxy moldable resin contains charges, and the charges content
It is 70 to 90wt%.It should be appreciated that ground, the material of the insulating layer 250 can be identical or not identical with the material of the clad 23.
In addition, the processing procedure in relation to the line construction 25 is many kinds of, such as increasing layer (build-up) processing procedure, rewiring road
(RDL) processing procedure etc., there is no particular restriction.
In addition, in follow-up process, a transmission element 24 can be set to the clad by electronic packing piece 3a as shown in Figure 3A
On insulating protective layer 26 on 23 first surface 23a, with the cover on sensing area A, sensing area A and the transmission element 24 are enabled
Between formed one in vacancy 240, make light via in this vacancy 240 arrive at sensing area A, for sensing area A receive signal and
Carry out biological (fingerprint) identification.On the other hand, it can be connect on the conducting element 27 and set a circuit board 30.
In this present embodiment, which can be a plate body；In another embodiment, Electronic Packaging as shown in Figure 3B
Part 3b, the transmission element 34 can be body, have a groove 340, to accommodate structure as shown in Figure 2 E.
Preparation method of the invention mainly uses silicon external perforation (Through Outside Silicon Via, abbreviation TOSV)
Technology forms electric conductor 22 in the clad 23, with by the electric conductor 22 be electrically connected the first line layer 25a and this
Two line layers 25b, therefore compared to TSV technology is noted, the present invention uses TOSV technology, can make various rulers according to depth-to-width ratio demand
The perforation 230 of very little (such as depth-to-width ratio is small), thus process difficulty can be reduced, with save a large amount of processing times and chemical agent at
This, and then cost of manufacture can be saved and yield (Throughput) can be improved.
Furthermore using the technology of machine drilling and resin consent, and cooperate patterning process (as exposure, development, etching,
Removal photoresist and etc.), to avoid the quality problem (such as recess or gas chamber) for the plating filling perforation for noting TSV processing procedure, therefore compare
In the technology that notes, preparation method of the invention can effectively maintain the quality of the electric conductor 22, to promote the reliability of the electric conductor 22, and
And reduce production cost.
In addition, preparation method of the invention notes package substrate with second line layer 25b (or the line construction 25) substitution, and
Bonding wire is noted by the electric conductor 22 substitution, therefore compared to routing type encapsulating structure is noted, preparation method of the invention can be greatly decreased
The electronic packing piece 2,3a, the height of 3b enable the electronic product of follow-up process to provide ultra-thin and inexpensive encapsulating structure
Meet light, thin, short, small demand.
In addition, it should thus be appreciated that ground, electronic packing piece 4 as shown in Figure 4 also can be by the electronic pads 410 of the electronic component 41
On the 41b of the non-sensing face, and the second surface 23b of the clad 23 flushes non-sensing face 41b.
The present invention provides a kind of electronic packing piece 2,3a, 3b, 4, comprising: a clad 23, an electronic component 21, one first
Line layer 25a, one second line layer 25b and multiple electric conductors 22.
The clad 23 has opposite first surface 23a and second surface 23b.
The electronic component 21 is embedded on the inside of the first surface 23a of the clad 23, and have expose to this first
The sensing area A of surface 23a.
The first line layer 25a is formed on the first surface 23a of the clad 23.
The second line layer 25b is formed on the second surface 23b of the clad 23.
The electric conductor 22 is formed in the clad 23 and is connected to first surface 23a and second surface 23b and electricity
Property connect the first line layer 25a and the second line layer 25b, wherein the electric conductor 22 include filling material 221 with surround the filling
The conduction material 220 of material 221.
In an embodiment, the material for forming the clad 23 includes casting die compound or bottom coating.
In an embodiment, the first surface 23a of the clad 23 is flushed with the electronic component 21.
In an embodiment, the second surface 23b of the clad 23 is flushed with the electronic component 21.
In an embodiment, which is inductance semiconductor chip.
In an embodiment, which is electrically connected the first line layer 25a or the second line layer 25b.
In an embodiment, the perforation of connection first surface 23a and second surface 23b is formed in the clad 23
230, and the conduction material 220 is formed on the hole wall in the perforation 230, and the filling material 221 is formed in the perforation 230 to fill out
The full perforation 230.
In an embodiment, first line layer 25a is not formed on sensing area A.
In an embodiment, electronic packing piece 2,3a, 3b, 4 further include an insulating protective layer 26, are formed in this
To cover first line layer 25a on the first surface 23a of clad 23, and the insulating protective layer 26 has the exposed sensing
The opening 260 of area A.
In an embodiment, the electronic packing piece 3a, 3b further include transmission element 24,34, are set to the clad 23
First surface 23a on, with the cover on sensing area A.
In an embodiment, electronic packing piece 2,3a, 3b, 4 further include a line construction 25, are formed in the packet
On the second surface 23b of coating 23, and the line construction 25 is electrically connected second line layer 25b.
In conclusion electronic packing piece and its preparation method of the invention, be set in the clad by by electric conductor, with by
The electric conductor is electrically connected the first line layer and second line layer, therefore the present invention can reduce process difficulty, to save production
Cost simultaneously can improve yield, and can effectively maintain the quality of the electric conductor, to promote the reliability of the electric conductor.
Furthermore the present invention notes package substrate with second line layer (or the line construction) substitution, and by the conduction
Body substitution notes bonding wire, therefore the height of the electronic packing piece can be greatly decreased, enable the electronic product of follow-up process meet it is light,
Thin, short, small demand.
Above-described embodiment is only to be illustrated the principle of the present invention and its technical effect, not for limiting this hair
It is bright.Any those skilled in the art without departing from the spirit and scope of the present invention, repairs above-described embodiment
Change.Therefore the scope of the present invention, should be as listed in the claims.
Claims (21)
1. a kind of electronic packing piece, it is characterized in that, which includes:
Clad, with opposite first surface and second surface；
Electronic component is embedded on the inside of the first surface of the clad, and has the sensing area for exposing to the first surface；
Line layer is formed on the clad；And
Electric conductor is formed in the clad and is connected to the first surface and second surface and is electrically connected the line layer,
In, which includes filling material and the conduction material for surrounding the filling material.
2. electronic packing piece according to claim 1, it is characterized in that, the material for forming the clad includes casting die compound
Or bottom coating.
3. electronic packing piece according to claim 1, it is characterized in that, the first surface of the clad and the electronic component are neat
It is flat.
4. electronic packing piece according to claim 1, it is characterized in that, the second surface of the clad and the electronic component are neat
It is flat.
5. electronic packing piece according to claim 1, it is characterized in that, which is electrically connected the line layer.
6. electronic packing piece according to claim 1, it is characterized in that, be formed in the clad be connected to the first surface with
The perforation of second surface, and the conduction material is formed on the hole wall in the perforation, and the filling material is formed in the perforation to fill out
The full perforation.
7. electronic packing piece according to claim 1, it is characterized in that, the line layer is not formed on the sensing area.
8. electronic packing piece according to claim 1, it is characterized in that, which is formed in the first surface of the clad
On, which further includes insulating protective layer, it is formed on the first surface of the clad, and cover the line layer,
And the insulating protective layer has the opening of an exposed sensing area.
9. electronic packing piece according to claim 1, it is characterized in that, which further includes transmission element, is set to
On the first surface of the clad, with the cover on the sensing area.
10. electronic packing piece according to claim 1, it is characterized in that, which further includes line construction, shape
At on the second surface of the clad, and the line construction is electrically connected the line layer.
11. a kind of preparation method of electronic packing piece, it is characterized in that, which includes:
One clad with opposite first surface and second surface is provided, and is embedded on the inside of the first surface of the clad
An at least electronic component, wherein the electronic component has the sensing area for exposing to the first surface；And
The electric conductor for being connected to the first surface and second surface is formed in the clad, and forms line layer in the clad
On, so that the electric conductor is electrically connected the line layer, wherein the electric conductor includes filling material and the conduction material for surrounding the filling material.
12. the preparation method of electronic packing piece according to claim 11, it is characterized in that, the material for forming the clad includes casting
Mold compound or bottom coating.
13. the preparation method of electronic packing piece according to claim 12, it is characterized in that, the first surface of the clad and the electricity
Subcomponent flushes.
14. the preparation method of electronic packing piece according to claim 11, it is characterized in that, the second surface of the clad and the electricity
Subcomponent flushes.
15. the preparation method of electronic packing piece according to claim 11, it is characterized in that, which is electrically connected the route
Layer.
16. the preparation method of electronic packing piece according to claim 11, it is characterized in that, the processing procedure of the electric conductor includes:
The perforation of multiple the connection first surfaces and second surface is formed in the clad；
The conduction material is formed on the hole wall in the perforation；And
The filling material is formed in the perforation to fill up the perforation.
17. the preparation method of electronic packing piece according to claim 16, it is characterized in that, the perforation is by the way of machine drilling
It is formed.
18. the preparation method of electronic packing piece according to claim 11, it is characterized in that, the line layer is not formed in the sensing area
On.
19. the preparation method of electronic packing piece according to claim 11, it is characterized in that, it is formed on the first surface of the clad
Have a line layer, and the preparation method further include to be formed insulating protective layer on the first surface of the clad to cover the line layer,
And enable opening of the insulating protective layer with an exposed sensing area.
20. the preparation method of electronic packing piece according to claim 11, it is characterized in that, the preparation method further include setting transmission element in
On the first surface of the clad, with the cover on the sensing area.
21. the preparation method of electronic packing piece according to claim 11, it is characterized in that, which further includes forming line construction
In on the second surface of the clad, and the line construction is electrically connected the line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711460307.XA CN109979890A (en) | 2017-12-28 | 2017-12-28 | Electronic packing piece and its preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711460307.XA CN109979890A (en) | 2017-12-28 | 2017-12-28 | Electronic packing piece and its preparation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109979890A true CN109979890A (en) | 2019-07-05 |
Family
ID=67074738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711460307.XA Pending CN109979890A (en) | 2017-12-28 | 2017-12-28 | Electronic packing piece and its preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109979890A (en) |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050001331A1 (en) * | 2003-07-03 | 2005-01-06 | Toshiyuki Kojima | Module with a built-in semiconductor and method for producing the same |
| TW200820396A (en) * | 2006-10-18 | 2008-05-01 | Advanced Semiconductor Eng | Semiconductor chip package manufacturing method and structure thereof |
| US20090039527A1 (en) * | 2007-08-06 | 2009-02-12 | Siliconware Precision Industries Co., Ltd. | Sensor-type package and method for fabricating the same |
| EP2309535A1 (en) * | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
| CN103227272A (en) * | 2012-01-25 | 2013-07-31 | 新光电气工业株式会社 | Wiring substrate, light emitting device, and manufacturing method of wiring substrate |
| US20130337648A1 (en) * | 2012-06-14 | 2013-12-19 | Bridge Semiconductor Corporation | Method of making cavity substrate with built-in stiffener and cavity |
| CN103579022A (en) * | 2012-08-03 | 2014-02-12 | 矽品精密工业股份有限公司 | Structure and manufacturing method of semiconductor package |
| CN105405775A (en) * | 2014-08-15 | 2016-03-16 | 矽品精密工业股份有限公司 | Method for manufacturing package structure |
| CN105575915A (en) * | 2014-09-03 | 2016-05-11 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN105870023A (en) * | 2014-12-27 | 2016-08-17 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN106206463A (en) * | 2015-04-24 | 2016-12-07 | 矽品精密工业股份有限公司 | Method for manufacturing electronic packaging piece and electronic packaging structure |
| US20170084528A1 (en) * | 2015-09-18 | 2017-03-23 | Samsung Electro-Mechanics Co., Ltd. | Package substrate and manufacturing method thereof |
| CN206312887U (en) * | 2016-12-06 | 2017-07-07 | 苏州源戍微电子科技有限公司 | Chip embedded encapsulating structure with closed cavity |
| CN107403785A (en) * | 2016-05-18 | 2017-11-28 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
-
2017
- 2017-12-28 CN CN201711460307.XA patent/CN109979890A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050001331A1 (en) * | 2003-07-03 | 2005-01-06 | Toshiyuki Kojima | Module with a built-in semiconductor and method for producing the same |
| TW200820396A (en) * | 2006-10-18 | 2008-05-01 | Advanced Semiconductor Eng | Semiconductor chip package manufacturing method and structure thereof |
| US20090039527A1 (en) * | 2007-08-06 | 2009-02-12 | Siliconware Precision Industries Co., Ltd. | Sensor-type package and method for fabricating the same |
| EP2309535A1 (en) * | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
| CN103227272A (en) * | 2012-01-25 | 2013-07-31 | 新光电气工业株式会社 | Wiring substrate, light emitting device, and manufacturing method of wiring substrate |
| US20130337648A1 (en) * | 2012-06-14 | 2013-12-19 | Bridge Semiconductor Corporation | Method of making cavity substrate with built-in stiffener and cavity |
| CN103579022A (en) * | 2012-08-03 | 2014-02-12 | 矽品精密工业股份有限公司 | Structure and manufacturing method of semiconductor package |
| CN105405775A (en) * | 2014-08-15 | 2016-03-16 | 矽品精密工业股份有限公司 | Method for manufacturing package structure |
| CN105575915A (en) * | 2014-09-03 | 2016-05-11 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN105870023A (en) * | 2014-12-27 | 2016-08-17 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN106206463A (en) * | 2015-04-24 | 2016-12-07 | 矽品精密工业股份有限公司 | Method for manufacturing electronic packaging piece and electronic packaging structure |
| US20170084528A1 (en) * | 2015-09-18 | 2017-03-23 | Samsung Electro-Mechanics Co., Ltd. | Package substrate and manufacturing method thereof |
| CN107403785A (en) * | 2016-05-18 | 2017-11-28 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN206312887U (en) * | 2016-12-06 | 2017-07-07 | 苏州源戍微电子科技有限公司 | Chip embedded encapsulating structure with closed cavity |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105845635B (en) | Electron package structure | |
| CN105261606B (en) | Method for manufacturing coreless packaging substrate | |
| CN105637633B (en) | Embedded encapsulation with pre-formed via hole | |
| CN107104055B (en) | Semiconductor device and method for manufacturing the same | |
| US10204852B2 (en) | Circuit substrate and semiconductor package structure | |
| CN105405835B (en) | Interposer substrate and method of manufacturing the same | |
| CN105731354B (en) | Wafer-class encapsulation and corresponding manufacturing process for MEMS sensor device | |
| CN105304584B (en) | Interposer substrate and method of manufacturing the same | |
| CN107424973A (en) | Package substrate and its preparation method | |
| US20170057808A1 (en) | Mems chip package and method for manufacturing the same | |
| EP3067929A2 (en) | Semiconductor package assembly | |
| CN105489565B (en) | Package structure of embedded device and method for fabricating the same | |
| CN110364491A (en) | Electronic packing piece and its preparation method | |
| KR20220026658A (en) | Semiconductor package | |
| CN105323948B (en) | Interposer substrate and method of manufacturing the same | |
| EP3065173B1 (en) | Semiconductor package assembly | |
| CN105845639A (en) | Electronic encapsulation structure and conductive structure | |
| CN104681523B (en) | Fingerprint Lock identifies module package structure | |
| CN104810339B (en) | Package substrate and method for fabricating the same, and semiconductor package and method for fabricating the same | |
| CN109979890A (en) | Electronic packing piece and its preparation method | |
| TWI672786B (en) | Electronic package and method of manufacture | |
| CN1312763C (en) | Structure for constructing and installing chip embedded typed semiconductor components | |
| CN103681610B (en) | Chip laminated structure and manufacture method thereof | |
| CN109148357B (en) | Test interface board assembly and manufacturing method thereof | |
| CN108962868A (en) | Encapsulating structure and its preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200703 Address after: Hsinchu County, Taiwan, China Applicant after: PHOENIX PIONEER TECHNOLOGY Co.,Ltd. Address before: Grand Cayman Islands Applicant before: PHOENIX & Corp. |
|
| TA01 | Transfer of patent application right | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190705 |
|
| WD01 | Invention patent application deemed withdrawn after publication |