CN109976686B

CN109976686B - Distributed display system and method

Info

Publication number: CN109976686B
Application number: CN201711459814.1A
Authority: CN
Inventors: 王新成; 顾约翰
Original assignee: Zhejiang Uniview Technologies Co Ltd
Current assignee: Zhejiang Uniview Technologies Co Ltd
Priority date: 2017-12-28
Filing date: 2017-12-28
Publication date: 2023-03-14
Anticipated expiration: 2037-12-28
Also published as: CN109976686A

Abstract

The embodiment of the invention provides a distributed display system and a distributed display method. The system comprises a switching chip and a plurality of Intel chips, wherein the plurality of Intel chips comprise a first Intel chip and at least one second Intel chip. The switching chip comprises a DMA processor and a plurality of PCIE interfaces. Each Intel chip comprises a PCIE interface, and the switching chip is connected with each Intel chip through the PCIE interface in a non-transparent bridge mode. And the DMA processor sends the data decoded by the first Intel chip to a second Intel chip connected with the exchange chip so as to display the image on a display screen corresponding to the second Intel chip after the image is rendered by the second Intel chip. And sending the decoded data to the corresponding second Intel chip through the DMA processor to realize the full exchange and real-time display of the data.

Description

Distributed display system and method

Technical Field

The invention relates to the technical field of display, in particular to a distributed display system and a distributed display method.

Background

With the development of decoding mosaic display systems and the pursuit of decoding capability and image rendering capability, more and more embedded-level Intel chips are also beginning to be adopted. In order to maximize the decoding capability and expand the output ports of a single decoding display device, a cascade connection method of a plurality of CPU chips is generally selected. The current Intel chip mainly utilizes a CPU to send coded data to a corresponding CPU through network cascade connection, and then decodes and displays the coded data.

Disclosure of Invention

In order to overcome the above disadvantages in the prior art, embodiments of the present invention provide a distributed display system and method.

The embodiment of the invention provides a distributed display system, which comprises a switching chip and a plurality of Intel chips, wherein the Intel chips comprise a first Intel chip and at least one second Intel chip,

the switching chip comprises a DMA processor and a plurality of PCIE interfaces;

each Intel chip comprises a PCIE interface, and the switch chip and each Intel chip are connected by the PCIE interface in a non-transparent bridge manner;

the DMA processor is connected with a PCIE interface of the exchange chip and used for sending the data decoded by the first Intel chip to the second Intel chip connected with the exchange chip so as to display images on a display screen corresponding to the second Intel chip after the images are rendered through the second Intel chip.

The embodiment of the invention also provides a distributed display method, which is applied to the distributed display system and comprises the following steps:

the first Intel chip decodes data to be displayed to obtain decoded data, and stores the decoded data in a memory block with continuous memory space;

the first Intel chip generates data transfer information based on the stored address mapping information and sends the data transfer information to the DMA processor of the exchange chip;

the DMA processor sends the decoded data to a second Intel chip corresponding to the data transfer information based on the received data transfer information;

and the second Intel chip performs image rendering on the received decoded data and performs image display on a corresponding display screen.

The embodiment of the present invention further provides a distributed display method, which is applied to a first Intel chip connected to an exchange chip, where the exchange chip is connected to the first Intel chip and at least one second Intel chip through a PCIE interface in a non-transparent bridge manner, and the method includes:

decoding data to be displayed to obtain decoded data, and storing the decoded data in a memory block with continuous memory space;

and generating data transfer information based on the stored address mapping information, and sending the data transfer information to a DMA processor of the exchange chip, so that the DMA processor sends decoded data to a second Intel chip corresponding to the data transfer information based on the received data transfer information, and the image is rendered by the second Intel chip and then displayed on a corresponding display screen.

Compared with the prior art, the invention has the following beneficial effects:

the embodiment of the invention provides a distributed display system and a distributed display method. The system comprises a switching chip and a plurality of Intel chips. The plurality of Intel chips comprise a first Intel chip and at least one second Intel chip. The switching chip comprises a DMA processor and a plurality of PCIE interfaces. Each Intel chip includes a PCIE interface. The switching chip and each Intel chip are connected in a non-transparent bridge mode through the PCIE interface. The DMA processor is connected with a PCIE interface of the exchange chip and used for sending the data decoded by the first Intel chip to the second Intel chip connected with the exchange chip so as to display images on a display screen corresponding to the second Intel chip after the images are rendered through the second Intel chip. The DMA processor sends the decoded data to the corresponding second Intel chip, so that full exchange and real-time display of the data are realized, and the situation that encoding and decoding are needed before the decoded data are displayed on a display screen corresponding to the second Intel chip, which causes that full exchange, decoding resource sharing and real-time display cannot be realized in a real sense is avoided.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a block diagram of a distributed display system according to an embodiment of the present invention.

Fig. 2 is a second block diagram of a distributed display system according to an embodiment of the present invention.

Fig. 3 is a schematic flowchart of a distributed display method according to a first embodiment of the present invention.

Fig. 4 is a flowchart illustrating the sub-steps included in step S110 in fig. 3.

Fig. 5 is a second flowchart of the distributed display method according to the first embodiment of the present invention.

Fig. 6 is a flowchart illustrating a distributed display method according to a second embodiment of the present invention.

Fig. 7 is a flowchart illustrating sub-steps included in step S210 in fig. 6.

An icon: 10-a distributed display system; 110-first Intel chip; 120-a second Intel chip; 200-a switch chip; 210-DMA processor.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In the prior art, the cascade connection of the Intel chips is mainly realized through a network. And after decoding the data to be displayed by an Intel chip, segmenting the decoded data according to the number of the spliced screens. Due to limited network bandwidth, after being segmented, the data needs to be coded and then sent to other Intel chips, and the other Intel chips decode the received data and then display the data on corresponding display screens. This approach does not achieve true full switching, sharing of decoding resources, and real-time display.

The defects of the above solutions are the results obtained after the inventors have tested and studied carefully, and therefore, the discovery process of the above problems and the solutions proposed by the following embodiments of the present application for the above problems should be the contributions of the inventors to the present application in the course of the present invention.

Based on the above research, in this embodiment, PCIE concatenation is adopted. PCIE concatenation not only has considerable bandwidth, but also very reliable transport. Among them, PCIE is a high-speed serial computer expansion bus standard.

The following describes the distributed display system and method provided in this embodiment in detail.

Referring to fig. 1, fig. 1 is a block diagram illustrating a distributed display system 10 according to an embodiment of the present invention. In the distributed display system 10, one CPU decodes data, and the CPU distributes the decoded data to other CPUs for partial display after decoding, and finally splices the data into a complete image. In this embodiment, the distributed display system 10 may include a switch chip 200 and a plurality of Intel chips. The plurality of Intel chips may include a first Intel chip 110 and at least one second Intel chip 120.

In this embodiment, the switch chip 200 may include a DMA (Direct Memory Access) processor 210 and a PCIE interface. The Intel chip comprises a PCIE interface. The switch chip 200 is connected to each Intel chip through the PCIE interface in a Non-Transparent bridge (NT bridge). The Intel chip can only be set as an RC device, and the non-transparent bridge can connect two different PCIE domains and can be used for multi-RC interconnection compared to a general PCI bridge (transparent bridge), so that the non-transparent bridge is used in the cascade connection. The non-transparent bridge connects two independent processor domains. The RC is a device with active configuration capability.

In this embodiment, the DMA processor 210 is connected to the PCIE interface of the switch chip 200, so that the DMA processor 210 can be connected to the Intel chip through the PCIE interface of the switch chip 200. The DMA processor 210 is configured to send the decoded data of the first Intel chip 110 to the second Intel chip 120 connected to the switch chip 200. The second Intel chip 120 is configured to render an image of the received data, and further display the image of the data on a display screen corresponding to the second Intel chip 120. The first Intel chip 110 and the second Intel chip 120 have the same hardware structure and are respectively connected to the switch chip 200, and the first Intel chip 110 is an Intel chip used for decoding data to be displayed among the plurality of Intel chips and is not a fixed Intel chip. The first Intel chip 110 and the second Intel chip 120 are different in identity in one decoding and distributing process, and the actual Intel chips corresponding to the first Intel chip 110 and the second Intel chip 120 are changeable in other decoding and distributing processes.

For example, there are an Intel chip 1, an Intel chip 2, and an Intel chip 3, and in a decoding distribution process, the Intel chip 2 is responsible for decoding, the Intel chip 2 is the first Intel chip 110, and the Intel chip 1 and the Intel chip 3 are the second Intel chip 120; in another decoding distribution process, the Intel chip 3 is responsible for decoding, wherein the Intel chip 3 is the first Intel chip 110, the Intel chip 1 and the Intel chip 2 are the second Intel chip 120.

In the prior art, one Intel chip sends decoded data to other Intel chips through a network, and the transmission data is large and the network bandwidth is limited, so that the method greatly occupies the bandwidth and the CPU performance and is limited by the network bandwidth and the CPU forwarding capacity. In this embodiment, the DMA processor 210 sends the decoded data of the first Intel chip 110 to the second Intel chip 120, which is not only fast, but also the DMA transfer mode does not require the participation of the CPU in the data transfer process, so that the DMA transfer mode is not limited by the network bandwidth and the forwarding capability of the CPU.

Referring to fig. 1 again, the Intel chip includes a CPU and an embedded GPU. The CPU of the Intel chip is connected to the switch chip 200 through the PCIE interface of the Intel chip. The GPU of the Intel chip is used for rendering and/or decoding data.

In this embodiment, the address mapping information between the plurality of Intel chips is stored in the Intel chip. The first Intel chip 110 is configured to decode data to be displayed, and transport the decoded data to the second Intel chip 120 through the DMA processor 210 based on the stored address mapping information.

The address mapping is also called address translation, and addresses are independent in different PCIE domains. To realize that DMA transports data across different domains, the address of the opposite domain needs to be translated into the address of the domain to correctly start the transport. That is to say, the communication between different PCIE domains needs to use the address mapping function of the non-transparent bridge to implement the memory read/write operation between the RC devices. One PCIE interface of the switch chip 200 corresponds to one PCIE domain. The PCIE interface of the switch chip 200 may be referred to as an NT port.

In the embodiment of this embodiment, if the first Intel chip 110 does not correspond to a display screen, the GPU of the first Intel chip 110 may be used for decoding only; if the first Intel chip 110 corresponds to a display screen, the GPU of the first Intel chip 110 is configured to decode and render, and display data on the corresponding display screen. The GPU of the second Intel chip 120 is configured to render the data sent by the first Intel chip 110, and display the rendered data on a corresponding display screen.

Referring to fig. 2, fig. 2 is a second block diagram of the distributed display system 10 according to the embodiment of the present invention. In an implementation manner of this embodiment, the Intel chip may be an Intel Braswell CPU. In a PCIE system, the Intel brand CPU can only exist as an RC device, a non-transparent bridge is needed during the cascade connection, and the chip 32NT8 of the IDT includes an NT port, so that the chip 32NT8 of the IDT can be selected as the switch chip 200. In which a 32NT8 includes 8 NT ports and two DMA processors 210, theoretically, a maximum of 8 RC devices can be cascaded, that is, a 32NT8 can be cascaded with a maximum of 8 Intel slave CPUs. If more than 8 Intel Braswell CPUs need to be cascaded, the purpose of expanding the NT port can be achieved through the cascade connection of a plurality of 32NT8, and more than 8 Intel Braswell CPUs are cascaded.

As shown in fig. 2, the distributed display system 10 includes 4 Intel brand CPUs cascaded, with 4 non-transparent bridges separating the CPUs into different PCIE domains. Wherein only the P0 and P3 domains have DMA processors 210. During data transfer, one of the DMA processors 210 may be selected according to actual conditions to transfer the decoded data from the first Intel chip 110 to the second Intel chip 120. For example, if the CPU0 is responsible for decoding, the DMA processor 210 closest to the CPU0 may be selected to carry data, or a relatively idle DMA processor 210 may be selected to carry data. Thus, arbitrary stacking, roaming and resource sharing of display effects can be achieved, and encoding and decoding of decoded data are not required.

The Intel Braswell CPU is internally integrated with a GPU display card and a matched mediaSDK, and can realize decoding and rendering of image data and cutting and scaling of the image data.

In the embodiment of this embodiment, the bare data decoded by one of the CPUs can be carried to any other CPU for rendering and displaying. And vice versa. The following are illustrated by way of example: suppose that each CPU is connected to an HDMI (High Definition Multimedia Interface ) Interface, the distributed display system 10 includes a 2 × 2 display wall, and if full-screen display of one path of camera video on the whole wall is to be achieved, the video can be decoded on the CPU0, then cut into 4 equal parts, and sent to the corresponding CPU through PCIE respectively to render and send display. Therefore, the full exchange of the decoded data, and the resource sharing and splicing roaming functions of the images are realized.

First embodiment

Referring to fig. 1, fig. 2 and fig. 3, fig. 3 is a flowchart illustrating a distributed display method according to a first embodiment of the present invention. The method is applied to the distributed display system 10. The distributed display method is explained in detail below.

Step S110, the first Intel chip 110 decodes the data to be displayed to obtain decoded data, and stores the decoded data in a memory block with continuous memory space.

Referring to fig. 4, fig. 4 is a flowchart illustrating sub-steps included in step S110 in fig. 3. Step S110 may include substep S111, substep S112, and substep S113.

And a substep S111, decoding the data to be displayed by the GPU in the first Intel chip 110 to obtain decoded data.

In this embodiment, the decoding and rendering of the GPU of the CPU in the first Intel chip 110 are implemented based on a set of media libraries issued by the Intel, and a plurality of first memory blocks are applied for the decoding and rendering of the GPU in the whole process, representing corresponding memories. The above implementation process does not require memory space continuity, that is, the memories of the first memory blocks for storing the decoded data may not be physically continuous.

In sub-step S112, the CPU in the first Intel chip 110 creates a second memory block with continuous memory space.

DMA data transfer requires memory to be contiguous. Therefore, the CPU of the first Intel chip 110 may create a second memory block with continuous memory space for storing decoded data, so as to satisfy the DMA data transfer requirement. The second memory block may be created in a manner, but not limited to, that the CPU of the first Intel chip 110 creates the second memory block with continuous memory through the interface dma _ zalloc _ coherent.

In substep S113, the GPU in the first Intel chip 110 copies the decoded data from the first memory block with discontinuous memory spaces to the second memory block.

In an embodiment of this embodiment, the first Intel chip 110 may be integrated with a GPU display card and a matched MediaSDK. The first Intel chip 110 may use an original interface pfnPpDirectAvs (ppchan, srcsurfd, dstsufid, stSrcRect, u32 Flags) of the SDK to quickly copy the decoded data srcSurfId to a newly-created continuous memory dstSurfId through the GPU, that is, copy the decoded data from a plurality of first memory blocks with discontinuous memory space to a second memory block with continuous memory space. The interface pfnpdirectavs can not only realize the rapid copying of decoded data, but also perform cutting and scaling according to the size and the position.

Therefore, the problem that DMA data transportation requires a continuous memory is solved. For example, in fig. 2, the CPU0 side may store the decoded data into a memory block with continuous memory space by copying, so as to use the DMA processor 210 to transfer the data from the memory block with continuous memory space to another CPU (e.g., CPU 1).

In step S120, the first Intel chip 110 generates data transfer information based on the stored address mapping information, and sends the data transfer information to the DMA processor 210 of the switch chip 200.

In this embodiment, address mapping in different PCIE domains is completed first, for example, after the DDR address addr1 of the CPU1 in the P1 domain is mapped, the addr10 is changed in the P0 domain, and the operation addr10 is equal to the operation addr1.

In this embodiment, the CPU of the first Intel chip 110 may apply for a DMA data control block with a size of 32 bytes using the DMA _ zalloc _ coherent interface. The DMA data control block is configured to store the generated data transfer information, where the data transfer information may include a start address, a destination address (e.g., address addr10 of CPU 1), a data length, and the like of the data to be transferred. After generating the data handling information according to the decoded data and address mapping information stored in the second memory block, the CPU of the first Intel chip 110 sends the data transfer information to the DMA processor 210, and sets a DMA transfer start command.

In step S130, the DMA processor 210 sends the decoded data to the second Intel chip 120 corresponding to the data transfer information based on the received data transfer information.

In this embodiment, the CPU of the first Intel chip 110 sends the data transfer information and the transfer start command to the DMA processor 210. The DMA processor 210 transfers data to the second Intel chip 120 corresponding to the data transfer information according to the data transfer information. In the data transfer process, an interrupt may be generated, and the DMA processor 210 processes the interrupt to complete DMA data transfer.

In step S140, the second Intel chip 120 renders the received decoded data into an image and displays the image on a corresponding display screen.

In this embodiment, after receiving the decoded data, which is sent by the DMA processor 210 and decoded by the first Intel chip 110, the second Intel chip 120 renders an image of the data, and displays the rendered data on a corresponding display screen. Thereby, the image data is distributively displayed.

Referring to fig. 5, fig. 5 is a second flowchart illustrating a distributed display method according to a first embodiment of the invention. Before step S110, the method may further include step S101.

Step S101, reserving a target memory area with continuous memory space and certain capacity size when the CPU in the Intel chip is initialized.

In this embodiment, after the decoded data is displayed, the decoded data stored in the second memory block of the first Intel chip 110 and the decoded data distributed in the second Intel chip 120 need to be deleted. Meanwhile, other services also have behaviors of storing data and deleting data during operation. After long-term operation, the memory is fragmented. In this case, the CPU of the first Intel chip 110 may not be able to create a second memory block with continuous memory space, or there is not enough continuous memory space in the second Intel chip 120 for storing the data carried by the DMA processor 210 from the first Intel chip 110, so that the decoded data cannot be sent to the corresponding second Intel chip 120. In order to avoid the above situation, a target memory area with continuous memory space and a certain capacity is reserved for the CPU in the Intel chip during initialization. The target memory area is only used for storing decoded data copied from a first memory block with discontinuous memory spaces. The CPU in the first Intel chip 110 creates the second memory block with continuous memory space in the target memory area.

The specific capacity of the target memory area may be set according to actual conditions.

In the implementation manner of this embodiment, if in the linux system, the CPU in the first Intel chip 110 may reserve the target memory area through the interface E820_ add _ region (start, size, E820_ RESERVED) at the time of system initialization. Wherein the size is the capacity of the target storage area. The memory block does not participate in a partner system of Linux, and can be completely distributed and recycled by an engineer, so that the problem of memory fragmentation is solved.

Further, memory management may be performed on the target storage area to mitigate the memory fragmentation problem of the target storage area.

The lack of a DMA processor 210 during the cascading of Intel chips is addressed by the DMA processor 210 of the switching chip 200, enabling data transfer between the first Intel chip 110 and the second Intel chip 120. And, a second memory block with continuous memory is created to store the decoded data copied from the first memory block with discontinuous memory spaces, so as to provide continuous memory for the DMA processor 210 to perform data transportation. Therefore, resource sharing and arbitrary roaming splicing are realized.

Second embodiment

Referring to fig. 6, fig. 6 is a flowchart illustrating a distributed display method according to a second embodiment of the present invention. The method is applied to a first Intel chip 110 in communication connection with a switch chip 200, and the switch chip 200 is connected to the first Intel chip 110 and at least one second Intel chip 120 through a PCIE interface in a non-transparent bridge manner. The method may include step S210 and step S220.

Step S210, decoding the data to be displayed to obtain decoded data, and storing the decoded data in a memory block with continuous memory space.

The first Intel chip 110 includes a CPU and an embedded GPU. Referring to fig. 7, fig. 7 is a flowchart illustrating sub-steps included in step S210 in fig. 6. Step S210 may include substep S211, substep S212, and substep S213.

In substep S211, the GPU decodes the data to be displayed to obtain decoded data.

The decoded data are stored in a first memory block with discontinuous memory spaces.

In the sub-step S212, the CPU creates a second memory block with continuous memory space.

In the substep S213, the GPU copies the decoded data from the first memory block with discontinuous memory spaces to the second memory block.

Step S220, generating data transfer information based on the stored address mapping information, and sending the data transfer information to the DMA processor 210 of the switch chip 200, so that the DMA processor 210 sends the decoded data to the second Intel chip 120 corresponding to the data transfer information based on the received data transfer information, and performs image rendering via the second Intel chip 120 and then performs image display on the corresponding display screen.

For the detailed description of steps S210 to S220, please refer to the description of the distributed display method in the first embodiment, which is not repeated herein.

In summary, the embodiments of the present invention provide a distributed display system and method. The system comprises a switching chip and a plurality of Intel chips. The plurality of Intel chips comprise a first Intel chip and at least one second Intel chip. The switching chip comprises a DMA processor and a plurality of PCIE interfaces. Each Intel chip includes a PCIE interface. And the switching chip and each Intel chip are connected in a non-transparent bridge mode through the PCIE interface. The DMA processor is connected with a PCIE interface of the exchange chip and used for sending the data decoded by the first Intel chip to the second Intel chip connected with the exchange chip so as to display images on a display screen corresponding to the second Intel chip after the images are rendered through the second Intel chip. The DMA processor sends the decoded data to the corresponding second Intel chip, so that full exchange and real-time display of the data are realized, and the problem that the decoded data needs to be encoded and decoded before being displayed on a display screen corresponding to the second Intel chip, which causes that full exchange, decoding resource sharing and real-time display cannot be realized in the real sense is avoided.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A distributed display system, the system includes an exchange chip and a plurality of Intel chips, the plurality of Intel chips includes a first Intel chip and at least a second Intel chip, each Intel chip includes a PCIE interface, the exchange chip and each Intel chip are connected by the PCIE interface in a non-transparent bridge manner, characterized in that,

the DMA processor is connected with a PCIE interface of the exchange chip and is used for sending the data decoded by the first Intel chip to the second Intel chip connected with the exchange chip so as to display images on a display screen corresponding to the second Intel chip after the images are rendered through the second Intel chip;

the first Intel chip is coupled to the second Intel chip through the DMA processor.

2. The system of claim 1, wherein the Intel chip comprises a CPU and an embedded GPU, the CPU is connected to the switch chip through a PCIE interface of the Intel chip, and the GPU is configured to render and/or decode data.

3. The system according to claim 2, wherein the first Intel chip stores therein address mapping information between the plurality of Intel chips, and is configured to decode data to be displayed, and transport the decoded data to the second Intel chip through the DMA processor based on the address mapping information.

4. A distributed display method applied to the distributed display system according to any one of claims 1 to 3, the method comprising:

a target memory area with continuous memory space and certain capacity is reserved in the CPU of the Intel chip during initialization;

the second Intel chip performs image rendering on the received decoded data and performs image display on a corresponding display screen;

the first Intel chip decodes the data to be displayed to obtain decoded data, and stores the decoded data in a memory block with continuous memory space, and the method comprises the following steps:

the GPU in the first Intel chip decodes data to be displayed to obtain decoded data, wherein the decoded data are stored in a plurality of first memory blocks with discontinuous memory spaces;

a CPU in the first Intel chip creates a second memory block with continuous memory space;

and the GPU in the first Intel chip copies the decoded data to the second memory block from the first memory block with discontinuous memory spaces.

5. The method of claim 4, wherein the data transfer information comprises a start address, a data length, and a destination address of the decoded data.

6. The method of claim 4, wherein the manner in which the CPU in the first Intel chip creates a second memory block with contiguous memory space comprises:

and the CPU in the first Intel chip creates the second memory block with continuous memory space in the target memory area.

7. A distributed display method is applied to a first Intel chip connected with an exchange chip, wherein the exchange chip is connected with the first Intel chip and at least one second Intel chip in a non-transparent bridge mode through a PCIE interface, and the method comprises the following steps:

8. The method according to claim 7, wherein the first Intel chip includes a CPU and an embedded GPU, and the step of decoding the data to be displayed to obtain decoded data and storing the decoded data in a memory block having a continuous memory space includes:

the GPU decodes data to be displayed to obtain decoded data, wherein the decoded data are stored in a plurality of first memory blocks with discontinuous memory spaces;

the CPU creates a second memory block with continuous memory space;

and the GPU copies the decoded data to the second memory block from the first memory block with discontinuous memory spaces.