CN109976686A - Distributed display system and method - Google Patents
Distributed display system and method Download PDFInfo
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- CN109976686A CN109976686A CN201711459814.1A CN201711459814A CN109976686A CN 109976686 A CN109976686 A CN 109976686A CN 201711459814 A CN201711459814 A CN 201711459814A CN 109976686 A CN109976686 A CN 109976686A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1407—General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The embodiment of the present invention provides a kind of distributed display system and method.It include the first Intel chip and at least one the 2nd Intel chip in multiple Intel chips the system comprises an exchange chip and multiple Intel chips.Exchange chip includes dma processor and multiple PCIE interfaces.Each Intel chip includes PCIE interface, and exchange chip is connect in a manner of non-transparent bridge with each Intel chip PCIE interface.The first decoded data of Intel chip are sent to the 2nd Intel chip connecting with exchange chip by dma processor, by performing image display on the corresponding display screen of the 2nd Intel chip after the 2nd Intel chip progress image rendering.Decoded data are sent to corresponding 2nd Intel chip by dma processor, realize the total exchange and real-time display of data.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of distributed display system and method.
Background technique
It is more and more as the development of control display system, and the pursuit to decoding capability, image rendering abilities are spelled in decoding
The other Intel chip of embedded also start to be used.One decoding shows equipment, in order to pursue the maximization of decoding capability
And the extension of delivery outlet, it generally can all select the cascade mode of multiple cpu chips.Current Intel chip mainly passes through net
Network cascade, the data after coding are sent to corresponding CPU using CPU, then be decoded send it is aobvious.
Summary of the invention
In order to overcome above-mentioned deficiency in the prior art, the embodiment of the present invention is designed to provide a kind of distributed display
System and method.
The embodiment of the present invention provides a kind of distributed display system, and the system comprises an exchange chip and multiple Intel
Chip, includes the first Intel chip and at least one the 2nd Intel chip in the multiple Intel chip,
The exchange chip includes dma processor and multiple PCIE interfaces；
Each Intel chip includes PCIE interface, the exchange chip and each Intel chip described in
PCIE interface is connected in a manner of non-transparent bridge；
The dma processor is connect with the PCIE interface of the exchange chip, for decoding the first Intel chip
Data afterwards are sent to the 2nd Intel chip connecting with the exchange chip, with by the 2nd Intel chip into
It is performed image display on the corresponding display screen of the 2nd Intel chip after row image rendering.
The embodiment of the present invention also provides a kind of distributed display methods, described applied to the distributed display system
Method includes:
The first Intel chip is decoded to obtain decoded data to data to be displayed, and by decoded number
According to being stored in the continuous memory block of memory headroom；
The first Intel chip generates data transfer information based on the address mapping information of storage, and by the data
Transinformation is sent to the dma processor of the exchange chip；
Decoded data are sent to and the number by the dma processor based on the data transfer information received
According to the corresponding 2nd Intel chip of transinformation；
The 2nd Intel chip carries out image rendering to received decoded data, and on corresponding display screen
It performs image display.
The embodiment of the present invention also provides a kind of distributed display methods, applied to the first Intel connecting with exchange chip
Chip, the exchange chip PCIE interface in a manner of non-transparent bridge with the first Intel chip and at least one the
The connection of two Intel chips, which comprises
Data to be displayed is decoded to obtain decoded data, and decoded data are stored in memory headroom and are connected
In continuous memory block；
Address mapping information based on storage generates data transfer information, and the data transfer information is sent to described
The dma processor of exchange chip, so that the dma processor is based on the data transfer information received by decoded number
According to the 2nd Intel chip corresponding with the data transfer information is sent to, image rendering is carried out through the 2nd Intel chip
It is performed image display on corresponding display screen afterwards.
In terms of existing technologies, the invention has the following advantages:
The embodiment of the present invention provides a kind of distributed display system and method.The system comprises an exchange chips and multiple
Intel chip.It include the first Intel chip and at least one the 2nd Intel chip in the multiple Intel chip.The friendship
Changing chip includes dma processor and multiple PCIE interfaces.Each Intel chip includes PCIE interface.The exchange chip with
Each Intel chip is connected in a manner of non-transparent bridge the PCIE interface.The dma processor and the exchange chip
The connection of PCIE interface, connect for being sent to the decoded data of the first Intel chip with the exchange chip
The 2nd Intel chip, with by the 2nd Intel chip carry out image rendering after in the 2nd Intel chip pair
It is performed image display on the display screen answered.Corresponding 2nd Intel core is sent by decoded data by dma processor
Piece realizes the total exchange and real-time display of data, avoids decoded data on display screen corresponding with the 2nd Intel chip
It needs to carry out encoding and decoding before being shown, leads to can not achieve total exchange, decoding resource-sharing and reality truly
When show.
For enable invention above objects, features, and advantages be clearer and more comprehensible, present pre-ferred embodiments are cited below particularly, and
Cooperate appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is one of the block diagram of distributed display system provided in an embodiment of the present invention.
Fig. 2 is the two of the block diagram of distributed display system provided in an embodiment of the present invention.
Fig. 3 is one of the flow diagram for the distributed display methods that first embodiment of the invention provides.
Fig. 4 is the flow diagram for the sub-step that step S110 includes in Fig. 3.
Fig. 5 is the two of the flow diagram for the distributed display methods that first embodiment of the invention provides.
Fig. 6 is the flow diagram for the distributed display methods that second embodiment of the invention provides.
Fig. 7 is the flow diagram for the sub-step that step S210 includes in Fig. 6.
Icon: 10- distribution display system；The first Intel chip of 110-；The 2nd Intel chip of 120-；200- exchanges core
Piece；210-DMA processor.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, term " first ", " second " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
Mainly pass through the cascade of network implementations Intel chip in the prior art.One Intel chip carries out data to be displayed
After decoding, decoded data are split processing according to the quantity of mosaic screen.Since network bandwidth is limited, dividing
Need to be then forwarded to other Intel chips after cutting after being encoded data, other Intel chips solve received data
Data are shown on corresponding display screen again after code.This mode cannot achieve total exchange truly, decoding
Resource-sharing and real-time display.
For defect present in above scheme, be inventor being obtained through overtesting and after carefully studying as a result,
Therefore, the discovery procedure of the above problem and the solution that hereinafter the embodiment of the present application is proposed regarding to the issue above, all
It should be the contribution that inventor makes the application in process of the present invention.
Based on the studies above, therefore in the present embodiment, cascaded using PCIE.PCIE cascade not only has considerable bandwidth,
Also there is very reliable transporting.Wherein, PCIE is a kind of high speed serialization computer expansion bus standard.
Distributed display system provided in this embodiment and method are described in detail below.
Fig. 1 is please referred to, Fig. 1 is the block diagram of distributed display system 10 provided in an embodiment of the present invention.It is being distributed
In formula display system 10, a CPU carries out data decoding, which after the decoding goes decoded data distribution to other CPU
Part is shown, is finally spliced into complete image.In the present embodiment, the distributed display system 10 may include an exchange core
Piece 200 and multiple Intel chips.May include in the multiple Intel chip one the oneth Intel chip 110 and at least one
2nd Intel chip 120.
In the present embodiment, the exchange chip 200 may include DMA (Direct Memory Access, direct memory
Accessing operation) processor 210 and PCIE interface.The Intel chip includes PCIE interface.The exchange chip 200 passes through institute
It states PCIE interface and each Intel chip is connected in the mode of non-transparent bridge (Non-Transparent, NT bridge).Wherein,
Intel chip can only be set as RC equipment, non-transparent bridge compared to general PCI Bridge (transparent bridge), can connect two it is different
The domain PCIE can be used for more RC interconnections, therefore use non-transparent bridge in cascade.Non-transparent bridge connects two independent processors
Domain.RC is the equipment with active arrangement ability.
In the present embodiment, the dma processor 210 is connect with the PCIE interface of the exchange chip 200, therefore described
Dma processor 210 can be connect by the PCIE interface of the exchange chip 200 with Intel chip.The dma processor 210
For the decoded data of the first Intel chip 110 to be sent to connect with the exchange chip 200 described second
Intel chip 120.The 2nd Intel chip 120 is used to analyze the received data carry out image rendering, so by data with
It is performed image display on the corresponding display screen of the 2nd Intel chip 120.Wherein, the first Intel chip 110 and
Two Intel chips, 120 hardware configuration is identical, and connect respectively with the exchange chip 200, and the first Intel chip 110 is
Intel chip in multiple Intel chips for being decoded to data to be displayed is not some fixed Intel chip.
The first Intel chip 110 and the 2nd Intel chip 120 herein refers to that the identity in once decoding distribution procedure is different, when
So in others decoding distribution procedure, the first Intel chip 110 and the corresponding practical Intel core of the 2nd Intel chip 120
Piece is variable.
For example, have Intel chip 1, Intel chip 2 and Intel chip 3, and in once decoding distribution procedure, Intel core
Piece 2 is responsible for decoding, and Intel chip 2 is the first Intel chip 110, and Intel chip 1 and Intel chip 3 are second
Intel chip 120；In another decoding distribution procedure, Intel chip 3 is responsible for decoding, and Intel chip 3 is described first
Intel chip 110, Intel chip 1 and Intel chip 2 are the 2nd Intel chips 120.
Decoded data are sent other Intel chips by network by an Intel chip in the prior art, and are transmitted
Data are big and network bandwidth is limited, therefore this mode very occupied bandwidth and cpu performance, forwarded by network bandwidth and CPU
The limitation of ability.In the present embodiment, the decoded data of the oneth Intel chip 110 are sent to by dma processor 210
2nd Intel chip 120, not only speed is fast, while DMA transfer mode does not need the participation of CPU in data transfer procedure, because
This not will receive the limitation of network bandwidth and CPU transfer capability.
Referring once again to Fig. 1, the Intel chip includes the CPU and GPU being embedded.The CPU of the Intel chip passes through
The PCIE interface of the Intel chip is connect with the exchange chip 200.The GPU of the Intel chip is used to carry out data
Rendering and/or decoding.
In the present embodiment, the mutual address of cache of the multiple Intel chip is stored in the Intel chip
Information.The first Intel chip 110 is for being decoded data to be displayed, and the address of cache letter based on storage
Decoded data are carried to the 2nd Intel chip 120 by the dma processor 210 by breath.
Wherein, address of cache is called address translation, and in the different domains PCIE, address is independent of each other.Realize that DMA is removed
Destiny needs the address in the address translation cost domain in other side domain could correctly start carrying according to different domains is passed through.Namely
It says, the communication between the different domains PCIE needs the address of cache function by non-transparent bridge, is just able to achieve interior between RC equipment
Deposit read-write operation.Wherein, the corresponding domain PCIE of a PCIE interface of the exchange chip 200.The exchange chip 200
PCIE interface is properly termed as NT mouthfuls.
In the embodiment of the present embodiment, if the first Intel chip 110 does not correspond to display screen, described first
The GPU of Intel chip 110 can then be only used for decoding；If the corresponding display screen of the first Intel chip 110, described first
The GPU of Intel chip 110 shows data on corresponding display screen for decoding and rendering.Described second
The data that the GPU of Intel chip 120 is used to send the first Intel chip 110 render, and in corresponding display
The data after rendering are shown on screen.
Referring to figure 2., Fig. 2 is the two of the block diagram of distributed display system 10 provided in an embodiment of the present invention.?
In an embodiment of the present embodiment, the Intel chip can be Intel Braswell CPU.In PCIE system,
Intel Braswell CPU can only exist as RC equipment, and cascade when needs to use non-transparent bridge, the 32NT8 of IDT this
Money chip includes NT mouthfuls, therefore can choose this chip of the 32NT8 of IDT as the exchange chip 200.Wherein, one
32NT8 includes 8 NT mouthfuls and two dma processors 210, and theoretically maximum can cascade 8 RC equipment, that is to say, that one
32NT8 can at most cascade 8 Intel Braswell CPU.If desired 8 or more Intel Braswell CPU are cascaded,
It can then achieve the purpose that NT mouthfuls of extension by the cascade of multiple 32NT8, thus the Intel Braswell of cascade 8 or more
CPU。
As shown in Fig. 2, the distribution display system 10 includes cascade 4 Intel Braswell CPU, 4 non-
Bright bridge separates each CPU in the different domains PCIE.Wherein, there is dma processor 210 in only P0 and the domain P3.Carrying out data
When carrying, one of dma processor 210 can be selected decoded data by the first Intel chip according to the actual situation
110 are carried to the 2nd Intel chip 120.For example, can choose with CPU0 at nearest DMA if CPU0 is responsible for decoding
It manages device 210 and carries data, or the dma processor 210 of one relative free of selection carries data.Thus, it is possible to realize display effect
Any lamination, roaming and the resource-sharing of fruit, while not needing decoded data carrying out encoding and decoding.
Wherein, Intel Braswell CPU has been internally integrated a GPU video card and matched MediaSDK, Ke Yishi
Now to the decoding of image data, rendering, and cutting and scaling to image data.
In the embodiment of the present embodiment, one of decoded uncorrected data of CPU can be transported to any other one
Rendering is gone to send in a CPU aobvious.Vice versa.It is illustrated below with citing: assuming that each CPU connects a HDMI (High
Definition Multimedia Interface, high-definition multimedia interface) interface, the distribution display system 10
It then can be in CPU0 to realize full screen display of the camera video on entire wall all the way including one 2 × 2 display wall
On be decoded, be then cut into 4 equal portions, respectively by PCIE be sent to corresponding CPU up render send it is aobvious.Hereby it is achieved that
The resource-sharing and splicing roaming function of the total exchange and image of decoded data.
First embodiment
Fig. 1, Fig. 2 and Fig. 3 are please referred to, Fig. 3 is that the process for the distributed display methods that first embodiment of the invention provides is shown
One of be intended to.The method is applied to the distributed display system 10.Distributed display methods is described in detail below.
Step S110, the first Intel chip 110 are decoded data to be displayed to obtain decoded data, and
Decoded data are stored in the continuous memory block of memory headroom.
Referring to figure 4., Fig. 4 is the flow diagram for the sub-step that step S110 includes in Fig. 3.Step S110 may include
Sub-step S111, sub-step S112 and sub-step S113.
Sub-step S111, the GPU in the first Intel chip 110 are decoded after obtaining decoding data to be displayed
Data.
In the present embodiment, the GPU decoding and rendering of CPU are all based on Intel hair in the first Intel chip 110
A set of media library of cloth is realized, applies for multiple first memory blocks in the whole process, represent corresponding memory for decode and
The rendering of GPU.Wherein, above-mentioned realization process does not require memory headroom continuous, that is to say, that for storing decoded data
The memory of multiple first memory blocks may not be that physics is continuous.
Sub-step S112, the CPU in the first Intel chip 110 create continuous second memory block of a memory headroom.
DMA data carrying requires memory continuous.Therefore, the CPU of the first Intel chip 110 can create a memory
Continuous second memory block in space carries requirement for storing decoded data, to meet DMA data.Wherein, the second memory
The creation mode of block may be, but not limited to, and the CPU of the first Intel chip 110 passes through interface dma_zalloc_
Coherent creates continuous second memory block of memory.
Sub-step S113, the GPU in the first Intel chip 110 is by decoded data by multiple memory headrooms
Discontinuous first memory block copies in second memory block.
In the embodiment of the present embodiment, it can integrate GPU video card in the first Intel chip 110 and matched
The MediaSDK of set.The first Intel chip 110 can be used SDK original interface pfnPpDirectAvs (pPpChan,
SrcSurfId, dstSurfId, stSrcRect, u32Flags) by decoded data srcSurfId pass through GPU quick copy
Into newly-built contiguous memory dstSurfId, that is to say, that by decoded data by memory headroom discontinuous multiple first
It is copied in memory block in continuous second memory block of memory headroom.Wherein, interface pfnPpDirectAvs not only may be implemented
The quick copy of decoded data can also be cut according to size and location, be scaled.
Solve the problems, such as that DMA data carrying requires contiguous memory as a result,.For example, passing through copy in the side CPU0 in Fig. 2
Decoded data can be stored in the continuous memory block of a memory headroom, to use dma processor 210 by data by interior
It deposits and is transported to other CPU (for example, CPU1) in the continuous memory block in space.
Step S120, the first Intel chip 110 generate data transfer information based on the address mapping information of storage,
And the data transfer information is sent to the dma processor 210 of the exchange chip 200.
In the present embodiment, complete the address of cache in the different domains PCIE first, for example, in the domain P1 CPU1 the address DDR
Addr1 just becomes addr10 after mapping in the domain P0, and operation addr10 is equivalent to operation addr1.
In the embodiment of the present embodiment, dma_zalloc_ is can be used in the CPU of the first Intel chip 110
One size of coherent interface application is the DMA data control block of 32 bytes.For storing life in the DMA data control block
At data transfer information, the data transfer information may include the initial address of data for needing to shift, destination address (ratio
Such as, the address addr10 of CPU1) and data length etc..According to decoded data and the address being stored in the second memory block
After map information generates the data carrying information, the CPU of the first Intel chip 110 sends out the data transfer information
The dma processor 210 is given, and DMA transfer initial order is set.
Step S130, the dma processor 210 are sent out decoded data based on the data transfer information received
Give the 2nd Intel chip 120 corresponding with the data transfer information.
In the present embodiment, the CPU of the first Intel chip 110 orders the data transfer information and transfer starting
Order is sent to the dma processor 210.Data are transferred to and institute by the dma processor 210 according to the data transfer information
State the corresponding 2nd Intel chip 120 of data transfer information.Wherein, interruption can be generated in data transfer process, at the DMA
It manages the processing of device 210 to interrupt, completes DMA data and carry.
Step S140, the 2nd Intel chip 120 carry out image rendering to received decoded data, and right
It is performed image display on the display screen answered.
In the present embodiment, the 2nd Intel chip 120 receive dma processor 210 transmission by described first
After the decoded data that Intel chip 110 is decoded, image rendering is carried out to the data, and then in corresponding display screen
On shown.Image data is subjected to distributed display as a result,.
Referring to figure 5., Fig. 5 is the two of the flow diagram for the distributed display methods that first embodiment of the invention provides.
Before step S110, the method can also include step S101.
Step S101, CPU in the Intel chip a reserved memory headroom in initialization is continuous and amount of capacity one
Fixed target memory area.
In the present embodiment, after the decoding it after data are shown, needs to be stored in the first Intel chip for decoded
The decoded data being distributed in data and the 2nd Intel chip 120 in 110 the second memory block are deleted.Together
When, other business can also have the behavior for saving data, deleting data at runtime.After long-term operation in this way, memory will cause
Fragmentation.In this case, the CPU of the first Intel chip 110 cannot may create again memory headroom continuous the
There is no enough contiguous memory spaces for storing the dma processor 210 in two memory blocks or the 2nd Intel chip 120
The data carried from the first Intel chip 110, and then cause decoded data that cannot be sent to corresponding second
Intel chip 120.To avoid the occurrence of above situation, the CPU in the Intel chip reserves a memory headroom in initialization
Continuous and certain amount of capacity target memory area.The target memory area is only used for saving discontinuous by multiple memory headrooms
The decoded data replicated in first memory block.CPU in the first Intel chip 110 is in the target memory area
Create continuous second memory block of memory headroom.
Wherein, the particular capacity in the target memory area can be set according to the actual situation.
In embodiment in the present embodiment, if the CPU under Linux system, in the first Intel chip 110
The mesh can be reserved by interface e820_add_region (start, size, E820_RESERVED) in system initialization
Mark memory block.Wherein size size is the capacity of the target storage.This block memory is not involved in the buddy system of Linux,
It can distribute and be recycled with engineer oneself completely, to solve the problems, such as RAM fragmentation.
It is possible to further carry out memory management for the target storage to alleviate the memory of the target storage
Fragmentation problem.
It is solved by the dma processor 210 by exchange chip 200 and lacks dma processor in Intel chip cascade
210 the problem of, realizes that the data between the first Intel chip 110 and the 2nd Intel chip 120 are transmitted.Also, create memory
Continuous second memory block to store the decoded data by replicating in discontinuous first memory block of multiple memory headrooms, with
Data carrying is carried out for dma processor 210, and contiguous memory is provided.Hereby it is achieved that resource-sharing and arbitrary roaming splicing.
Second embodiment
Fig. 6 is please referred to, Fig. 6 is the flow diagram for the distributed display methods that second embodiment of the invention provides.It is described
Method is applied to the first Intel chip 110 communicated to connect with exchange chip 200, and the exchange chip 200 passes through PCIE interface
It is connect in a manner of non-transparent bridge with the first Intel chip 110 and at least one the 2nd Intel chip 120.The method
It may include step S210 and step S220.
Step S210 is decoded data to be displayed to obtain decoded data, and decoded data is stored in
In the continuous memory block of memory headroom.
The first Intel chip 110 includes the CPU and GPU being embedded.Fig. 7 is please referred to, Fig. 7 is step S210 packet in Fig. 6
The flow diagram of the sub-step included.Step S210 may include sub-step S211, sub-step S212 and sub-step S213.
Sub-step S211, GPU are decoded data to be displayed to obtain decoded data.
Wherein, decoded data are stored in discontinuous first memory block of multiple memory headrooms.
Sub-step S212, CPU create continuous second memory block of a memory headroom.
Decoded data are copied to institute by discontinuous first memory block of multiple memory headrooms by sub-step S213, GPU
It states in the second memory block.
Step S220, address mapping information based on storage generate data transfer information, and by the data transfer information
It is sent to the dma processor 210 of the exchange chip 200, so that the dma processor 210 is based on the data received
Decoded data are sent to the 2nd Intel chip 120 corresponding with the data transfer information by transinformation, through described
Two Intel chips 120 perform image display on corresponding display screen after carrying out image rendering.
Specific descriptions about step S210~S220 please refer to the description in first embodiment to distributed display methods,
Details are not described herein.
In conclusion the embodiment of the present invention provides a kind of distributed display system and method.The system comprises an exchanges
Chip and multiple Intel chips.It include the first Intel chip and at least one the 2nd Intel core in the multiple Intel chip
Piece.The exchange chip includes dma processor and multiple PCIE interfaces.Each Intel chip includes PCIE interface.The friendship
Chip is changed to connect in a manner of non-transparent bridge with each Intel chip the PCIE interface.The dma processor with it is described
The PCIE interface of exchange chip connects, and exchanges core with described for being sent to the decoded data of the first Intel chip
Piece connection the 2nd Intel chip, with by the 2nd Intel chip carry out image rendering after described second
It is performed image display on the corresponding display screen of Intel chip.Corresponding is sent by decoded data by dma processor
Two Intel chips realize the total exchange and real-time display of data, avoid decoded data corresponding with the 2nd Intel chip
Display screen on shown before need to carry out encoding and decoding, lead to can not achieve total exchange truly, decoding money
Source is shared and real-time display.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of distribution display system, which is characterized in that the system comprises an exchange chip and multiple Intel chips, institutes
State in multiple Intel chips include the first Intel chip and at least one the 2nd Intel chip,
The exchange chip includes dma processor and multiple PCIE interfaces；
Each Intel chip includes PCIE interface, and the exchange chip and each Intel chip pass through the PCIE
Interface is connected in a manner of non-transparent bridge；
The dma processor is connect with the PCIE interface of the exchange chip, for the first Intel chip is decoded
Data are sent to the 2nd Intel chip connecting with the exchange chip, to carry out figure by the 2nd Intel chip
As being performed image display on the corresponding display screen of the 2nd Intel chip after rendering.
2. system according to claim 1, which is characterized in that the Intel chip includes the CPU and GPU being embedded, described
CPU connect by the PCIE interface of the Intel chip with the exchange chip, the GPU be used to that data to be carried out to render with/
Or decoding.
3. system according to claim 2, which is characterized in that be stored in the first Intel chip the multiple
The mutual address mapping information of Intel chip, the first Intel chip are used to be decoded data to be displayed, and
Decoded data are carried to the 2nd Intel chip by the dma processor based on the address mapping information.
4. a kind of distribution display methods, which is characterized in that aobvious applied to distribution described in any one of claim 1-3
Show system, which comprises
The first Intel chip is decoded data to be displayed to obtain decoded data, and decoded data are deposited
Storage is in the continuous memory block of memory headroom；
The first Intel chip generates data transfer information based on the address mapping information of storage, and the data are shifted
Information is sent to the dma processor of the exchange chip；
Decoded data are sent to by the dma processor based on the data transfer information received to be turned with the data
Move the corresponding 2nd Intel chip of information；
The 2nd Intel chip carries out image rendering to received decoded data, and carries out on corresponding display screen
Image is shown.
5. according to the method described in claim 4, it is characterized in that, the data transfer information includes rising for decoded data
Beginning address, data length and destination address.
6. according to the method described in claim 4, it is characterized in that, the first Intel chip solves data to be displayed
Code obtains decoded data, and includes: by the step that decoded data are stored in the continuous memory block of memory headroom
GPU in the first Intel chip is decoded data to be displayed to obtain decoded data, wherein after decoding
Data be stored in discontinuous first memory block of multiple memory headrooms；
CPU in the first Intel chip creates continuous second memory block of a memory headroom；
GPU in the first Intel chip is answered decoded data by discontinuous first memory block of multiple memory headrooms
It makes in second memory block.
7. according to the method described in claim 6, it is characterized in that, being carried out in the first Intel chip to data to be displayed
Before the step of decoding obtains decoded data, the method also includes:
CPU in the Intel chip reserves the target memory that a memory headroom is continuous and amount of capacity is certain in initialization
Area.
8. the method according to the description of claim 7 is characterized in that the CPU in the first Intel chip creates memory sky
Between the mode of continuous second memory block include:
CPU in the first Intel chip creates continuous second memory of memory headroom in the target memory area
Block.
9. a kind of distribution display methods, which is characterized in that described applied to the first Intel chip being connect with exchange chip
Exchange chip PCIE interface in a manner of non-transparent bridge with the first Intel chip and at least one the 2nd Intel core
Piece connection, which comprises
Data to be displayed is decoded to obtain decoded data, and it is continuous that decoded data are stored in memory headroom
In memory block；
Address mapping information based on storage generates data transfer information, and the data transfer information is sent to the exchange
The dma processor of chip, so that the dma processor is sent out decoded data based on the data transfer information received
Give the 2nd Intel chip corresponding with the data transfer information, through the 2nd Intel chip carry out image rendering after
It is performed image display on corresponding display screen.
10. according to the method described in claim 9, it is characterized in that, the first Intel chip includes CPU and is embedded
GPU, it is described that data to be displayed is decoded to obtain decoded data, and decoded data are stored in memory headroom and are connected
Step in continuous memory block includes:
GPU is decoded data to be displayed to obtain decoded data, wherein it is empty that decoded data are stored in multiple memories
Between in discontinuous first memory block；
CPU creates continuous second memory block of a memory headroom；
GPU is copied to decoded data in second memory block by discontinuous first memory block of multiple memory headrooms.
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