CN109950253B - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
- Publication number
- CN109950253B CN109950253B CN201910196977.8A CN201910196977A CN109950253B CN 109950253 B CN109950253 B CN 109950253B CN 201910196977 A CN201910196977 A CN 201910196977A CN 109950253 B CN109950253 B CN 109950253B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal layer
- insulating layer
- adhesion
- nitrogen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses an array substrate, a manufacturing method thereof and a display panel, wherein the manufacturing method of the array substrate comprises the following steps: forming a first metal layer; introducing nitrogen and ammonia gas to the first metal layer to form an adhesion layer; forming a first insulating layer on the adhesion layer; etching the first insulating layer to form a via hole exposing the first metal layer; and forming a transparent electrode layer connected with the first metal layer through the via hole on the first insulating layer; the adhesive force between the adhesive layer and the first insulating layer is larger than that between the first metal layer and the first insulating layer. The adhesion layer increases the adsorption force of the first insulating layer, so that the etching speed of the first insulating layer is relatively slow, and the undercutting phenomenon is further improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
Liquid crystal displays have been widely used in various fields of work and life as a main medium for transmitting information. Few people know a seemingly simple liquid crystal panel, and the manufacturing of the panel requires hundreds of processes. Generally, a liquid crystal display panel is composed of an array substrate including active devices such as thin film transistors, a color filter substrate including color filters, and a liquid crystal cell sandwiched therebetween, and a transparent electrode layer on the surface of the array substrate needs to be connected to a metal layer in an active switch.
In the manufacturing of the array substrate, when the insulating layer on the surface of the metal layer is etched to form the contact hole, an Undercut (Passivation Undercut) phenomenon is easily generated, and in a serious case, abnormal display of the liquid crystal panel may be directly caused.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method thereof and a display panel to improve the undercut phenomenon of an insulating layer.
In order to achieve the above object, the present invention discloses a method for manufacturing an array substrate, comprising the steps of:
forming a first metal layer;
introducing nitrogen and ammonia gas to the first metal layer to form an adhesion layer;
forming a first insulating layer on the adhesion layer;
etching the first insulating layer to form a via hole exposing the first metal layer; and
forming a transparent electrode layer connected with the first metal layer through the via hole on the first insulating layer;
wherein an adhesive force between the adhesive layer and the first insulating layer is greater than an adhesive force between the first metal layer and the first insulating layer.
Optionally, the first metal layer includes a metal molybdenum material, the first insulating layer includes a silicon nitride material, and the adhesion layer is a molybdenum nitride material.
Optionally, the step of introducing nitrogen and ammonia gas to the first metal layer to form the adhesion layer includes the steps of:
decomposing nitrogen and ammonia into nitrogen atoms and hydrogen atoms;
and depositing nitrogen atoms and hydrogen atoms on the first metal layer, and carrying out chemical reaction with the first metal layer to form the attachment layer.
Optionally, in the step of decomposing the nitrogen gas and the ammonia gas into the nitrogen atoms and the hydrogen atoms, the nitrogen gas and the ammonia gas are decomposed into the nitrogen atoms and the hydrogen atoms through a plasma process.
Optionally, the step of decomposing the nitrogen gas and the ammonia gas into nitrogen atoms and hydrogen atoms includes the steps of:
adding ammonia gas on the first metal layer;
the ammonia gas is decomposed into hydrogen atoms and nitrogen atoms by a plasma process.
Adding nitrogen on the first metal layer; and
the nitrogen gas is decomposed into nitrogen atoms by a plasma process.
Alternatively, the plasma process time for nitrogen gas is between 7 seconds and 60 seconds, and the plasma process time for ammonia gas is between 4 seconds and 10 seconds.
Alternatively, the plasma process time for nitrogen is between 10 seconds and 20 seconds, and the plasma process time for ammonia is 7 seconds.
Optionally, the power of the plasma process is controlled between 8kw and 16kw while the plasma process is performed.
Optionally, the power of the plasma process is controlled between 10kw and 12kw while the plasma process is performed.
Optionally, a step of performing a preheating treatment on the first metal layer is added before the step of introducing nitrogen and ammonia gas to the first metal layer to form the adhesion layer.
Optionally, the pre-heat treatment time is 25 seconds.
The invention also discloses an array substrate, which comprises a substrate, an active switch and a transparent electrode layer, wherein the active switch is arranged on the surface of the substrate, the transparent electrode layer is arranged on the surface of the active switch, and the active switch comprises: the second metal layer is arranged on the surface of the substrate; the second insulating layer is arranged on the surface of the second metal layer; a semiconductor layer provided on a surface of the second insulating layer; the first metal layer covers the surface of the semiconductor layer; the adhesion layer is arranged on the surface of the first metal layer; a channel penetrating the first metal layer and the adhesion layer; a first insulating layer disposed on the adhesion layer and the surface of the channel; a via hole penetrating through the first insulating layer to expose the first metal layer; the transparent electrode layer is connected with the first metal layer through the via hole; the adhesive force between the adhesive layer and the first insulating layer is larger than that between the first metal layer and the first insulating layer; the adhesion layer is formed by decomposing ammonia gas and nitrogen gas and then reacting with the first metal layer.
The invention also discloses a display panel which comprises a color film substrate, the array substrate and a liquid crystal box filled between the color film substrate and the array substrate.
Compared with the scheme without the adhesion layer in the active switch, the ammonia gas and the nitrogen gas are introduced into the first metal layer, the adhesion layer is formed between the first metal layer and the first insulating layer, the first insulating layer is easy to adhere to the first metal layer during deposition, and due to good adhesion, the etching speed of the first insulating layer is relatively slow, so that the undercutting phenomenon is improved; in addition, the adhesion layer is formed by reacting nitrogen atoms with the first metal layer, so that more nitrogen atoms can be decomposed by adding nitrogen gas when ammonia gas is added, and the forming speed of the adhesion layer is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of an active switch;
FIG. 2 is a schematic illustration of an undercutting phenomenon;
FIG. 3 is a schematic illustration of the effect of an undercutting phenomenon on a transparent electrode layer;
fig. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
FIG. 5 is a flow chart based on FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a flow chart based on FIG. 5 according to an embodiment of the present invention;
FIG. 7 is a flow chart based on FIG. 4 according to another embodiment of the present invention;
FIG. 8 is a flow chart based on FIG. 4 according to another embodiment of the present invention;
fig. 9 is a flowchart of a method for manufacturing an array substrate according to another embodiment of the invention;
FIG. 10 is a schematic view of an array substrate of the present invention;
fig. 11 is a schematic diagram of a display panel according to the present invention.
100, an array substrate; 110. a substrate; 120. an active switch; 121. a first metal layer; 122. an adhesion layer; 123. a first insulating layer; 124. a via hole; 125. a channel; 126. a second metal layer; 127. a second insulating layer; 128. a semiconductor layer; 1281. a first semiconductor layer; 1282. a second semiconductor layer; 130. a transparent electrode layer; 140. a color film substrate; 150. a liquid crystal cell; 160. a display panel.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
As shown in fig. 1, the active switch 120 known to the inventor is disposed between the substrate 110 and the transparent electrode layer 130, and sequentially includes, in a direction away from the substrate 110: the second metal layer 126, the second insulating layer 127, the first semiconductor layer 1281, the second semiconductor layer 1282, the first metal layer 121, and the first insulating layer 123, and further includes a via hole 124 penetrating the first insulating layer 123 and a channel 125 penetrating the first insulating layer 123, the first metal layer 121, and the second semiconductor layer 1282; there is no adhesion layer 122 between the first metal layer 121 and the first insulating layer 123, and when the first insulating layer 123 on the surface of the first metal layer 121 is etched to form the via 124, an Undercut (Passivation Undercut) phenomenon is easily generated.
Fig. 2 is a schematic diagram illustrating an undercut phenomenon occurring on the first insulating layer 123, where M is an undercut phenomenon occurring on the first insulating layer 123, which may directly cause abnormal display of the liquid crystal panel in a severe case, and may become a latent reliability problem in a slight undercut phenomenon, which may cause a problem of dark spots or the like in the display of the liquid crystal panel during use, thereby affecting the quality of the liquid crystal panel.
Fig. 3 is a schematic diagram of the transparent electrode layer 130 laid on the first insulating layer 123 where the undercutting occurs, where N is a portion of the transparent electrode layer 130 affected by the undercutting phenomenon, and it can be seen from the figure that the thickness of the transparent electrode layer 130 in the via hole 124 is not uniform, which may cause problems such as abnormal display of the display panel 160.
The invention will be further elucidated with reference to the drawings and alternative embodiments.
As shown in fig. 4, an embodiment of the invention discloses a method for manufacturing an array substrate 100, including the steps of:
s41: forming a first metal layer;
s42: introducing nitrogen and ammonia gas to the first metal layer to form an adhesion layer;
s43: forming a first insulating layer on the adhesion layer;
s44: etching the first insulating layer to form a via hole exposing the first metal layer;
s45: forming a transparent electrode layer connected with the first metal layer through the via hole on the first insulating layer;
the adhesion between the adhesion layer 122 and the first insulating layer 123 is greater than the adhesion between the first metal layer 121 and the first insulating layer 123.
Wherein the thickness of the adhesion layer 122 is not more than 1 nm.
According to the invention, the adhesion layer 122 is added between the first metal layer 121 and the first insulating layer 123, because the adhesion force between the adhesion layer 122 and the first insulating layer 123 is greater than the adhesion force between the first metal layer 121 and the first insulating layer 123, the adhesion force between the first metal layer 121 and the first insulating layer 123 is increased through the adhesion layer 122, so that the first insulating layer 123 is easy to adhere to the first metal layer 121 during deposition, and because the adhesion force is better, the etching speed of the first insulating layer 123 is slower, and further, the undercutting phenomenon is improved; without the adhesion layer 122, the adhesion effect of the first insulating layer 123 and the first metal layer 121 is poor, and the surface of the first insulating layer 123 is fragile, so that the etching speed is increased, thereby causing an undercut phenomenon.
In addition, since the adhesion layer 122 is formed by reacting nitrogen atoms with the first metal layer 121, adding nitrogen gas when ammonia gas is added can decompose more nitrogen atoms, thereby increasing the forming speed of the adhesion layer 122.
The active switch 120 includes a thin film transistor, the first metal layer 121 is a source/drain electrode layer, the first insulating layer 123 is a passivation layer, and the transparent electrode layer 130 may be made of a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), Cadmium Tin Oxide (CTO), tin oxide (SnO2), or zinc oxide (ZnO), but is not limited thereto.
In one embodiment, the source/drain electrode layer includes a metal molybdenum material, the passivation layer includes a silicon nitride material, and the adhesion layer 122 is a molybdenum nitride material. The source and drain electrode layers contain molybdenum, the passivation layer contains silicon nitride, and the molybdenum nitride material contains the same components as the source and drain electrode layers and the passivation layer, so that the source and drain electrode layers and the passivation layer have a good combination effect, and the adhesive force between the source and drain electrode layers and the passivation layer can be increased.
In one embodiment, as shown in fig. 5, in the step S42, the method includes the steps of:
s51: decomposing nitrogen and ammonia into nitrogen atoms and hydrogen atoms;
s52: and depositing nitrogen atoms and hydrogen atoms on the first metal layer, and carrying out chemical reaction with the first metal layer to form the attachment layer.
In step S51, the nitrogen gas and the ammonia gas are decomposed into nitrogen atoms and hydrogen atoms by the plasma process. Wherein the Plasma process can also be called a Plasma process, which is a flow of a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method; since the film formation rate is an important parameter in the fabrication process of the array substrate 100 and the film formation rate in the film deposition process is low, the time consumption of the film deposition process is relatively long, and thus the film formation rate becomes an important factor that restricts the film deposition throughput. Compared with other film deposition methods, the PECVD method has multiple advantages, one of which is that the large-area uniform film deposition can be realized, and in addition, the film deposition can be carried out at a high rate, so that the efficiency of the film deposition by the PECVD method is higher, and the productivity can be improved.
In one embodiment, as shown in fig. 6, in the step S51, the method includes the steps of:
s61: adding ammonia gas on the first metal layer;
s62: decomposing ammonia gas into hydrogen atoms and nitrogen atoms by a plasma process;
s63: adding nitrogen on the first metal layer;
s64: the nitrogen gas is decomposed into nitrogen atoms by a plasma process.
In step S62, the plasma processing time of ammonia gas is between 4 seconds and 10 seconds, and experimental tests show that the plasma processing time of ammonia gas is preferably 7 seconds; in step S64, the plasma process time of the nitrogen gas is between 7 seconds and 60 seconds, and experimental tests show that the plasma time of the nitrogen gas is preferably between 10 seconds and 20 seconds.
The plasma process is performed by introducing ammonia gas into the first metal layer 121, and then the plasma process is performed by introducing nitrogen gas, so as to prevent the thickness of the adhesion layer 122 formed after the adhesion layer reacts with the first metal layer 121 from increasing due to the excessive concentration of nitrogen atoms caused by the plasma process by introducing nitrogen gas at the beginning, thereby generating conductivity and causing the display panel 160 to have a residual image phenomenon.
In theory, the longer the plasma process of ammonia gas, the more nitrogen atoms and hydrogen atoms are contained in the adhesion layer 122, the better the adhesion layer 122 is, but the longer the plasma process is, the lower the productivity is, and the ammonia gas is decomposed into atoms during the plasma process, which generates atomic energy that will impact the surface of the channel 125 of the active switch 120, causing damage like etching, so the time of the ammonia gas plasma process should be controlled; the plasma process time of nitrogen is too long, which will cause waste; if the plasma process time is too short, the effect of the adhesion layer 122 will be poor, and if the plasma process time is too short, the effect of neutralizing ammonia will not be obtained, so the plasma process time needs to be controlled.
In one embodiment, as shown in fig. 7, in the step S51, the method includes the steps of:
s71: adding nitrogen on the first metal layer;
s72: decomposing nitrogen into nitrogen atoms by a plasma process;
s73: adding ammonia gas on the first metal layer;
s74: the ammonia gas is decomposed into hydrogen atoms and nitrogen atoms by a plasma process.
In step S72, the plasma process time of the nitrogen gas is between 7 seconds and 60 seconds, and experimental tests show that the plasma time of the nitrogen gas is preferably between 10 seconds and 20 seconds; in step S74, the plasma process time of ammonia gas is between 4 seconds and 10 seconds, and experimental tests show that the plasma time of ammonia gas is preferably 7 seconds.
In one embodiment, as shown in fig. 8, in the step S51, the method includes the steps of:
s81: simultaneously adding nitrogen and ammonia gas on the first metal layer;
s82: the nitrogen gas and the ammonia gas are decomposed into hydrogen atoms and nitrogen atoms by a plasma process.
Meanwhile, nitrogen and ammonia are added, so that the content of nitrogen atoms can be increased in a short time, the forming time of the adhesion layer is shortened, and the efficiency of the whole manufacturing process is improved.
In the step S81, when ammonia gas and nitrogen gas are simultaneously added, the ratio of ammonia gas to nitrogen gas is in the range of 0.1 to 1; in step S82, when ammonia and nitrogen are added simultaneously, ammonia and nitrogen are decomposed directly by a plasma process, the plasma process time is between 7 seconds and 60 seconds; wherein the plasma process time of the ammonia gas and the nitrogen gas is preferably 10 seconds to 30 seconds. When ammonia and nitrogen are introduced, the content of ammonia cannot exceed the content of nitrogen, and if the ammonia cannot be neutralized, the ammonia neutralization effect cannot be achieved, and the ammonia and nitrogen ratio is tested to be between 0.1 and 1, so that the generated adhesion layer can achieve the effect, and the ammonia cannot cause bad influence.
In one embodiment, the power of the plasma process is controlled between 8KW and 16KW while the plasma process is performed. When the ammonia gas and the nitrogen gas are used for the plasma process, the power of the plasma process is increased to 8KW to 16KW, the decomposition rate of the ammonia gas and the nitrogen gas can be increased, the forming rate of the adhesion layer 122 is increased, and the productivity is further improved; if the power of the plasma process is too high, the atomic energy generated when ammonia and nitrogen are decomposed into atoms in a short time is too high, which may cause etching damage to the active switch 120, so that the power of the plasma process needs to be limited to 16 KW.
In one embodiment, the power of the plasma process is controlled to be between 10KW and 12KW while the plasma process is performed. By controlling the power of the plasma process more precisely, the power of the plasma process can achieve better effects in both improving the productivity and reducing the damage.
In one embodiment, a step of preheating the first metal layer is added before the step of introducing nitrogen and ammonia to form the adhesion layer on the first metal layer; wherein the first metal layer 121 is a source drain electrode layer. The method has the advantages that the source drain electrode layer and the channel are subjected to preheating treatment before the plasma processing procedure, so that the passivation layer can be better contacted with the source drain electrode layer during deposition, the undercutting phenomenon occurring when the passivation layer is etched to form a contact hole can be improved, although the problem of undercutting cannot be thoroughly solved through simple preheating treatment, a certain effect can be achieved, and the undercutting phenomenon can be better improved by matching with the plasma processing procedure after preheating treatment.
In one embodiment, the preheat treatment time is 25 seconds. Generally, if there is no ammonia and nitrogen plasma process, the preheating time is 50 seconds, but with ammonia and nitrogen plasma process, the undercutting phenomenon can be better improved, the preheating time can be shortened, thereby increasing the productivity, and the test shows that when the preheating time is controlled at 25 seconds, the effect of improving the undercutting phenomenon is better by combining with the ammonia and nitrogen plasma process.
As shown in fig. 9, as another embodiment of the present invention, a method for manufacturing an array substrate 100 is disclosed, which includes the steps of:
s91: forming a first metal layer;
s92: carrying out preheating treatment on the first metal layer;
s93: adding ammonia gas on the first metal layer;
s94: decomposing ammonia gas into hydrogen atoms and nitrogen atoms by a plasma process;
s95: adding nitrogen on the first metal layer;
s96: decomposing nitrogen into nitrogen atoms by a plasma process;
s97: depositing nitrogen atoms and hydrogen atoms on the surface of the first metal layer, and carrying out chemical reaction with the first metal layer to form an attachment layer;
s98: forming a first insulating layer on the adhesion layer;
s99: etching the first insulating layer to form a via hole exposing the first metal layer;
s910: forming a transparent electrode layer connected with the first metal layer through the via hole on the first insulating layer;
the adhesion between the adhesion layer 122 and the first insulating layer 123 is greater than the adhesion between the first metal layer 121 and the first insulating layer 123.
As shown in fig. 10, as another embodiment of the present invention, an array substrate 100 is disclosed, which includes a substrate 110, an active switch 120 and a transparent electrode layer 130, wherein the active switch 120 is disposed on a surface of the substrate 110, the transparent electrode layer 130 is disposed on a surface of the active switch 120, and the active switch 120 includes: a second metal layer 126 disposed on the surface of the substrate 110; a second insulating layer 127 disposed on a surface of the second metal layer 126; a semiconductor layer 128 provided on a surface of the second insulating layer 127; a first metal layer 121 covering the surface of the semiconductor layer 128; an adhesion layer 122 disposed on a surface of the first metal layer 121; a channel 125 penetrating the first metal layer 121 and the adhesion layer 122; a first insulating layer 123 disposed on the surfaces of the adhesion layer 122 and the channel 125; a via 124 penetrating the first insulating layer 123 to expose the first metal layer 121; the transparent electrode layer 130 is connected to the first metal layer 121 through the via 124; the adhesion between the adhesion layer 122 and the first insulating layer 123 is greater than the adhesion between the first metal layer 121 and the first insulating layer 123; the adhesion layer 122 is formed by decomposing ammonia gas and nitrogen gas and then reacting with the first metal layer 121.
The active switch 120 includes a thin film transistor, the first metal layer 121 is a source/drain electrode layer, the first insulating layer 123 is a passivation layer, and the transparent electrode layer 130 may be made of a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), Cadmium Tin Oxide (CTO), tin oxide (SnO2), or zinc oxide (ZnO), without limitation; the second metal layer 126 is a gate electrode layer formed on the substrate 110 by sputtering and masking processes, and is made of copper, aluminum, molybdenum, titanium, or a stacked structure thereof; the second metal layer 126 is a gate insulating layer, and a gate insulating layer covering the entire gate electrode layer is formed on the gate electrode layer, and the gate insulating layer may be made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like, and may be deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The source and drain electrode layers comprise a metal molybdenum material, the passivation layer comprises a silicon nitride material, and the adhesion layer 122 is a molybdenum nitride material; the thickness of the adhesion layer 122 does not exceed 1 nm.
The semiconductor layer 128 may be a single-layer structure, or may be a two-layer structure including a first semiconductor layer 1281 and a second semiconductor layer 1282, which is not limited herein; if the semiconductor layer 128 has a single-layer structure, the semiconductor layer 128 is an active layer and is made of hydrogenated amorphous silicon material, and if the semiconductor layer 127 has a two-layer structure, the first semiconductor layer 1281 is an active layer and may be made of hydrogenated amorphous silicon material or oxide, wherein the oxide includes at least one of zinc oxide, tin oxide, indium oxide, and gallium oxide, and the active layer is formed by sputtering and a mask process; the second semiconductor layer 1282 is an ohmic contact layer, and is a hydrogenated amorphous silicon thin film layer formed by doping phosphorus, which is also formed by sputtering and photo-masking.
As another embodiment of the present invention, as shown in fig. 11, a display panel 160 is further disclosed, which includes a color filter substrate 140, the array substrate 100, and a liquid crystal cell 150 filled between the color filter substrate 140 and the array substrate 100.
It should be noted that, the limitations of the steps involved in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all should be considered to belong to the protection scope of the present disclosure.
The technical solution of the present invention can be widely applied to various display panels, such as a Twisted Nematic (TN) display panel, an In-Plane Switching (IPS) display panel, a Vertical Alignment (VA) display panel, and a Multi-Domain Vertical Alignment (MVA) display panel, and of course, other types of display panels, such as an Organic Light-Emitting Diode (OLED) display panel, can be applied to the above solution.
The foregoing is a more detailed description of the invention in connection with specific alternative embodiments, and the practice of the invention should not be construed as limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
forming a first metal layer;
introducing nitrogen and ammonia gas to the first metal layer to form an adhesion layer;
forming a first insulating layer on the adhesion layer;
etching the first insulating layer to form a via hole exposing the first metal layer; and
forming a transparent electrode layer connected with the first metal layer through the via hole on the first insulating layer;
wherein an adhesion force between the adhesion layer and the first insulating layer is greater than an adhesion force between the first metal layer and the first insulating layer; the first metal layer is a source drain electrode layer, and the first insulating layer is a passivation layer; the first metal layer comprises a metal molybdenum material, the first insulating layer comprises a silicon nitride material, and the adhesion layer is a molybdenum nitride material;
and in the step of introducing nitrogen and ammonia gas to the first metal layer to form the adhesion layer, the method comprises the following steps:
decomposing nitrogen and ammonia into nitrogen atoms and hydrogen atoms; and
depositing nitrogen atoms and hydrogen atoms on the first metal layer, and carrying out chemical reaction with the first metal layer to form an adhesion layer;
the step of decomposing nitrogen gas and ammonia gas into nitrogen atoms and hydrogen atoms includes the steps of:
adding ammonia gas on the first metal layer;
decomposing ammonia gas into hydrogen atoms and nitrogen atoms by a plasma process;
adding nitrogen on the first metal layer; and
decomposing nitrogen into nitrogen atoms by a plasma process;
wherein the plasma processing time of nitrogen gas is between 7 seconds and 60 seconds, and the plasma processing time of ammonia gas is between 4 seconds and 10 seconds.
2. The method of claim 1, wherein the plasma process is performed while controlling a power of the plasma process to be between 8 kilowatts and 16 kilowatts.
3. The method of claim 1, wherein a pre-heating step is added to the first metal layer before the step of introducing nitrogen and ammonia to form the adhesion layer.
4. The method of claim 1, wherein the adhesion layer has a thickness of no more than 1 nm.
5. An array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 4, comprising a substrate, an active switch disposed on a surface of the substrate, and a transparent electrode layer disposed on a surface of the active switch, wherein the active switch comprises:
the second metal layer is arranged on the surface of the substrate;
the second insulating layer is arranged on the surface of the second metal layer;
a semiconductor layer provided on a surface of the second insulating layer;
the first metal layer covers the surface of the semiconductor layer;
the adhesion layer is arranged on the surface of the first metal layer;
a channel penetrating the first metal layer and the adhesion layer;
a first insulating layer disposed on the adhesion layer and the surface of the channel; and
a via hole penetrating through the first insulating layer to expose the first metal layer;
the transparent electrode layer is connected with the first metal layer through the via hole;
the adhesive force between the adhesive layer and the first insulating layer is larger than that between the first metal layer and the first insulating layer; the adhesion layer is formed by decomposing ammonia gas and nitrogen gas and then reacting with the first metal layer; the first metal layer is a source drain electrode layer, and the first insulating layer is a passivation layer.
6. A display panel comprising a color filter substrate, the array substrate of claim 5, and a liquid crystal cell filled between the color filter substrate and the array substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910196977.8A CN109950253B (en) | 2019-03-15 | 2019-03-15 | Array substrate, manufacturing method thereof and display panel |
| PCT/CN2020/078101 WO2020187056A1 (en) | 2019-03-15 | 2020-03-06 | Array substrate and fabrication method therefor, and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910196977.8A CN109950253B (en) | 2019-03-15 | 2019-03-15 | Array substrate, manufacturing method thereof and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109950253A CN109950253A (en) | 2019-06-28 |
| CN109950253B true CN109950253B (en) | 2022-08-05 |
Family
ID=67009954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910196977.8A Active CN109950253B (en) | 2019-03-15 | 2019-03-15 | Array substrate, manufacturing method thereof and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109950253B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020187056A1 (en) * | 2019-03-15 | 2020-09-24 | 惠科股份有限公司 | Array substrate and fabrication method therefor, and display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8624238B2 (en) * | 2010-01-18 | 2014-01-07 | Samsung Display Co., Ltd. | Thin-film transistor substrate and method of fabricating the same |
| CN103956386A (en) * | 2014-04-11 | 2014-07-30 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, array substrate, manufacturing method of array substrate and display device |
| CN109216264A (en) * | 2018-08-31 | 2019-01-15 | 上海华力微电子有限公司 | A kind of connecting hole adherency layer optimizing method |
-
2019
- 2019-03-15 CN CN201910196977.8A patent/CN109950253B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8624238B2 (en) * | 2010-01-18 | 2014-01-07 | Samsung Display Co., Ltd. | Thin-film transistor substrate and method of fabricating the same |
| CN103956386A (en) * | 2014-04-11 | 2014-07-30 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, array substrate, manufacturing method of array substrate and display device |
| CN109216264A (en) * | 2018-08-31 | 2019-01-15 | 上海华力微电子有限公司 | A kind of connecting hole adherency layer optimizing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109950253A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7816693B2 (en) | Thin film transistor in which an interlayer insulating film comprises two distinct layers of insulating material | |
| US20080176364A1 (en) | Method of manufacturing thin film transistor substrate | |
| KR20080008562A (en) | Method of manufacturing thin film transistor substrate, thin film transistor substrate and display device having the same | |
| US8223312B2 (en) | Method of manufacturing a display device using a barrier layer to form an ohmic contact layer | |
| JP2012118531A (en) | Display device and method for manufacturing the same | |
| KR20100075026A (en) | Thin film transistor array substrate and method of fabricating the same | |
| KR20110072270A (en) | Transistor, method of manufacturing the same and electronic device comprising transistor | |
| KR20060097648A (en) | Copper wire or copper electrode protected by silver thin layer and liquid crystal display device having the wire or electrode | |
| CN109950254B (en) | Array substrate, manufacturing method thereof and display panel | |
| US8551822B2 (en) | Method for manufacturing array substrate | |
| KR20060081470A (en) | Tft substrate and manufacturing method of the same | |
| CN102629592A (en) | Array substrate, producing method and displaying device thereof | |
| KR20080084084A (en) | Method for fabricating thin film transistor and array substrate for lcd including the same | |
| CN101963726B (en) | FFS (Fringe Field Switching) type TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array base plate and manufacturing method thereof | |
| CN105261589A (en) | Conductive pattern forming method, semiconductor device, and electronic apparatus | |
| CN109950253B (en) | Array substrate, manufacturing method thereof and display panel | |
| CN110379819B (en) | Array substrate, manufacturing method thereof and display panel | |
| CN108305879A (en) | Thin-film transistor array base-plate and production method and display device | |
| CN107507850A (en) | A kind of array base palte and preparation method thereof, display device | |
| CN109950255B (en) | Array substrate, manufacturing method thereof and display panel | |
| CN109935551B (en) | Manufacturing method of array substrate and array substrate | |
| CN102637631B (en) | Manufacturing method of TFT (thin film transistor)-LCD (liquid crystal display) array substrate | |
| US9136354B2 (en) | Methods for manufacturing passivation layer and thin film transistor array substrate | |
| CN108198819B (en) | Array substrate and preparation method thereof | |
| WO2020187056A1 (en) | Array substrate and fabrication method therefor, and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |