CN109935168B - Substrate base plate and preparation method thereof, array base plate and display device - Google Patents
Substrate base plate and preparation method thereof, array base plate and display device Download PDFInfo
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- CN109935168B CN109935168B CN201910238145.8A CN201910238145A CN109935168B CN 109935168 B CN109935168 B CN 109935168B CN 201910238145 A CN201910238145 A CN 201910238145A CN 109935168 B CN109935168 B CN 109935168B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Abstract
The invention provides a substrate base plate and a preparation method thereof, an array base plate and a display device, and relates to the technical field of display. The substrate comprises a through hole, and a first insulating layer, a conductive metal layer and a second insulating layer are stacked in the through hole along the direction of pointing the first surface of the substrate to the second surface; the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole; the second insulating layer is provided with a via hole extending to the conductive metal layer; the first surface is opposite to the second surface. In the invention, the conductive metal layer on the first surface of the substrate base plate and the conductive metal layer exposed on one side of the second surface of the substrate base plate can be respectively used for connecting the pixel circuit and the driving circuit, namely the pixel circuit and the driving circuit can be respectively arranged on the two opposite surfaces of the substrate base plate, and the pixel circuit and the driving circuit can be connected with the conductive metal layer through the through hole extending to the conductive metal layer through the second insulating layer, so that a frame area is not required to be arranged for shielding the driving circuit, and the screen occupation ratio of the display device is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a substrate base plate and a preparation method thereof, an array base plate and a display device.
Background
With the continuous progress of science and technology, visual information is more and more important in people's life, and therefore, display devices bearing visual information, such as televisions, computers, mobile phones, wearable devices and the like, also take more and more important position in people's life. With the continuous development of display technology, people also put higher quality demands on display devices, such as full-screen with high screen ratio.
In a conventional display device, a driving circuit and a connecting line thereof are usually disposed in a non-display area at the periphery of a display area, and therefore, a larger frame area is usually required to be disposed for shielding, so that the improvement of the screen occupation ratio of the display device is limited.
Disclosure of Invention
The invention provides a substrate base plate and a preparation method thereof, an array base plate and a display device, which can improve the screen ratio of the existing display device to a certain extent.
In order to solve the above problems, the present invention discloses a substrate base plate, which includes a through hole, wherein a first insulating layer, a conductive metal layer, and a second insulating layer are stacked in the through hole along a direction from a first surface of the substrate base plate to a second surface of the substrate base plate; wherein the content of the first and second substances,
the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole;
the second insulating layer is provided with a via hole extending to the conductive metal layer;
the first surface of the substrate base plate is opposite to the second surface of the substrate base plate.
Optionally, the cross section of the first insulating layer is in an inverted trapezoid or rectangle shape in the through hole; wherein the cross-section is parallel to a thickness direction of the substrate base.
Optionally, a target angle between a sidewall of the via hole in contact with the conductive metal layer and a thickness direction of the substrate base is less than or equal to 30 degrees.
Optionally, a first thickness ratio between a thickness of the second insulating layer and a thickness of the substrate base is greater than or equal to 5% and less than or equal to 20%.
Optionally, a second thickness ratio between the thickness of the conductive metal layer and the thickness of the substrate base is greater than or equal to 0.1% and less than or equal to 1%.
Optionally, the thickness of the conductive metal layer is greater than or equal to 1 micrometer and less than or equal to 10 micrometers.
Optionally, the thickness of the first insulating layer is less than or equal to the thickness from the first surface of the substrate to the conductive metal layer;
and/or the presence of a gas in the gas,
the thickness of the second insulating layer is smaller than or equal to the thickness from the second surface of the substrate base plate to the conductive metal layer.
Optionally, the material of the conductive metal layer is at least one of copper, aluminum, silver and titanium.
Optionally, the material of the first insulating layer and/or the second insulating layer is polysiloxane.
Optionally, the substrate base plate is made of silicon, glass or polyimide.
In order to solve the above problems, the present invention further discloses an array substrate, which includes the substrate, and a pixel circuit and a driving circuit respectively disposed on a first surface and a second surface of the substrate opposite to each other; the pixel circuit and the driving circuit are connected through the conductive metal layer and a via hole extending from the second insulating layer to the conductive metal layer.
In order to solve the above problem, the present invention further discloses a display device including the above array substrate.
In order to solve the above problems, the present invention also discloses a method for manufacturing a substrate, comprising:
providing a substrate base plate;
forming a first blind hole on a first surface of the substrate base plate;
forming a conductive metal layer on the first surface of the substrate base plate, wherein the conductive metal layer covers the bottom and at least part of the side wall of the first blind hole;
forming a first insulating layer on one side, close to the first surface of the substrate base plate, of the conductive metal layer in the first blind hole;
forming a second blind hole on a second surface of the substrate base plate opposite to the first surface, wherein the first blind hole and the second blind hole form a through hole;
and forming a second insulating layer in the second blind hole, wherein the second insulating layer is provided with a through hole extending to the conductive metal layer.
Optionally, the forming a second insulating layer in the second blind via includes:
filling a second insulating layer in the second blind hole by a solution method;
and patterning the second insulating layer to form a via hole extending to the conductive metal layer.
Optionally, the forming a conductive metal layer on the first surface of the substrate base plate includes:
and forming a conductive metal layer on the first surface of the substrate base plate, the bottom of the first blind hole and at least part of the side wall through a sputtering process or an evaporation process.
Compared with the prior art, the invention has the following advantages:
in the embodiment of the invention, the substrate base plate comprises a through hole, and a first insulating layer, a conductive metal layer and a second insulating layer are stacked in the through hole along the direction of pointing the first surface of the substrate base plate to the second surface of the substrate base plate; wherein the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole; the second insulating layer is provided with a via hole extending to the conductive metal layer; the first surface of the substrate base plate is opposite to the second surface of the substrate base plate. In the embodiment of the invention, a part of the conductive metal layer on the first surface of the substrate base plate can be used for connecting one of the pixel circuit and the driving circuit, and a part of the conductive metal layer exposed from the bottom of the via hole of the second insulating layer on one side of the second surface of the substrate base plate can be used for connecting the other of the pixel circuit and the driving circuit, so that the pixel circuit can be prepared on one side of the substrate base plate, the driving circuit is arranged on the other side of the substrate base plate, and the pixel circuit and the driving circuit can be connected through the via hole extending to the conductive metal layer in the second insulating layer and the conductive metal layer. Therefore, the pixel circuit and the driving circuit can be respectively arranged on two surfaces of the substrate back to back, so that a frame region is not required to be arranged for shielding, the frame region of the display device can be reduced, and the screen occupation ratio of the display device can be improved.
Drawings
FIG. 1 shows a schematic cross-sectional view of a substrate base plate of an embodiment of the present invention;
FIG. 2 illustrates a top view of a first surface of a substrate base of an embodiment of the present invention;
FIG. 3 illustrates a top view of a second surface of a substrate base plate in accordance with an embodiment of the present invention;
FIG. 4 is a flow chart illustrating steps of a method of fabricating a substrate base plate in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a substrate after forming a first blind via, in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of a substrate after forming a conductive metal layer according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a substrate after forming a first insulating layer according to an embodiment of the invention;
FIG. 8 is a schematic view of a substrate after forming second blind vias according to an embodiment of the present invention;
FIG. 9 is a schematic view of a substrate after forming a second insulating layer according to an embodiment of the invention;
fig. 10 is a schematic diagram of a substrate after forming a via hole of a second insulating layer according to an embodiment of the invention.
Description of reference numerals:
10-substrate base plate, 11-through hole, 12-first insulating layer, 13-conductive metal layer, 14-second insulating layer, 141-through hole, 01-first blind hole, 02-second blind hole.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example one
Referring to fig. 1, a schematic cross-sectional view of a substrate according to a first embodiment of the present invention is shown, where the substrate 10 includes a through hole 11, and a first insulating layer 12, a conductive metal layer 13, and a second insulating layer 14 are stacked in the through hole 11 along a direction pointing from a first surface S1 of the substrate to a second surface S2 of the substrate. Wherein, the conductive metal layer 13 extends to the first surface S1 of the substrate base plate 10 along the sidewall of the through hole 10, that is, the conductive metal layer 13 at least partially covers the first surface S1 of the substrate base plate 10; the second insulating layer 14 is provided with a via hole 141 extending to the conductive metal layer 13 so that the conductive metal layer 13 can be exposed from a bottom portion of the via hole 141; the first surface S1 of the base substrate 10 is opposite to the second surface S2 of the base substrate 10. In a specific application, the substrate base plate 10 may include one or more through holes 11, which is not particularly limited by the embodiment of the present invention.
In the embodiment of the present invention, the conductive metal layer 13 is formed on the first surface S1 of the substrate base plate 10, and this part of the conductive metal layer 13 may be used for connecting one of the pixel circuit and the driving circuit. In addition, the conductive metal layer 13 may be partially exposed from the bottom of the via hole 141 of the second insulating layer 14, that is, the conductive metal layer 13 may be exposed from the second surface S2 of the substrate base 10, and this portion of the conductive metal layer 13 may be used to connect the other of the pixel circuit and the driving circuit, so that the pixel circuit may be prepared on one side of the substrate base 10, the driving circuit may be disposed on the other side of the substrate base 10, and the pixel circuit and the driving circuit may be connected through the via hole 141 extending to the conductive metal layer 13 in the second insulating layer 14 and the conductive metal layer 13. Like this, pixel circuit and drive circuit can set up respectively on two surfaces that substrate base plate 10 carried on the back mutually, consequently need not to set up the frame region and shelter from to can reduce display device's frame region, and then can improve display device's screen and account for the ratio. It should be noted that the driving circuit may be a driving circuit for display, and may also be a driving circuit with other functions.
Further, in a specific application, the cross section of the first insulating layer 12 is an inverted trapezoid or a rectangle in the through hole 11, wherein the cross section is parallel to the thickness direction of the substrate base plate 10. For any cross section of the first insulating layer 12 parallel to the thickness direction of the substrate base plate 10, the cross section is an inverted trapezoid or a rectangle in the through hole 11, and correspondingly, the cross section of the first insulating layer 12 perpendicular to the thickness direction of the substrate base plate 10 is a circle in the through hole 11. When the cross section of the first insulating layer 12 is inverted trapezoid in the through hole 11, that is, the side wall of the through hole 11 contacting the conductive metal layer 13 may be an inclined surface, and then the conductive metal layer 13 may be deposited on the side wall of the through hole 11 more uniformly, thereby reducing the difficulty of the process for forming the conductive metal layer 13. Of course, the cross section of the first insulating layer 12 may also be rectangular in the through hole 11, that is, the side wall of the through hole 11 contacting the conductive metal layer 13 may be a vertical surface, which is not particularly limited in the embodiment of the present invention.
Specifically, the target angle α between the sidewall of the through hole 11 in contact with the conductive metal layer 13 and the thickness direction of the base substrate 10 is less than or equal to 30 degrees. Referring to fig. 1, a target angle α may be formed between a side wall of the through hole 11 in contact with the conductive metal layer 13 and the thickness direction of the substrate base plate 10, when the target angle α is greater than 0 degree, the side wall of the through hole 11 in contact with the conductive metal layer 13 is an inclined surface, a cross section of the first insulating layer 12 parallel to the thickness direction of the substrate base plate is an inverted trapezoid in the through hole 11, when the target angle α is equal to 0 degree, the side wall of the through hole 11 in contact with the conductive metal layer 13 is a vertical surface, and a cross section of the first insulating layer 12 parallel to the thickness direction of the substrate base plate is a rectangle in the. In a preferred implementation, the target angle α between the sidewall of the via 11 in contact with the conductive metal layer 13 and the thickness direction of the substrate base plate 10 may be greater than or equal to 10 degrees and less than or equal to 30 degrees, thereby facilitating more uniform deposition of the conductive metal layer 13 on the via sidewall.
In practical applications, the first thickness ratio between the thickness of the second insulating layer 14 and the thickness of the substrate 10 may be greater than or equal to 5% and less than or equal to 20%, and correspondingly, the thickness ratio between the total thickness of the first insulating layer 12 and the conductive metal layer 13 and the thickness of the substrate 10 may be greater than or equal to 80% and less than or equal to 95%, that is, the depth of the portion of the through hole 11 accommodating the first insulating layer 12 and the conductive metal layer 13 is deep, and the depth of the portion of the through hole 11 accommodating the second insulating layer 14 is shallow. When the material layer or the connection line of another device is disposed on the second surface S2 of the substrate, the material layer or the connection line needs to be extended to the bottom of the via hole 141 of the second insulating layer 14 and connected to the conductive metal layer 13 exposing the second insulating layer 14 to achieve conduction between devices, so if the depth of the portion of the through hole 11 accommodating the second insulating layer 14 is deep, the material layer or the connection line on the second surface S2 of the substrate needs to have a larger thickness so as to be connected to the conductive metal layer 13 at the bottom of the via hole 141, and if the depth of the portion of the through hole 11 accommodating the second insulating layer 14 is shallow, the thinner material layer or the connection line formed on the second surface S2 of the substrate can be conducted to the conductive metal layer 13 at the bottom of the via hole 141, thereby reducing the difficulty in manufacturing subsequent devices.
Further, in practical applications, the inventors found that, if the through hole 11 of the substrate base plate 10 is completely filled with the conductive metal layer 13, the conductive metal layer 13 in the through hole 11 may swell and bulge in some high temperature processes for preparing the pixel circuit, such as a CVD (Chemical Vapor Deposition) process, an annealing process, and the like, thereby causing a squeezing on the film layer in the pixel structure, and thus, the film layer in the pixel structure may be easily broken, so that the yield of the display device is low.
Based on the above findings, in a specific application, the second thickness ratio between the thickness of the conductive metal layer 13 and the thickness of the base substrate 10 may be greater than or equal to 0.1%, and less than or equal to 1%. Because the thickness of the conductive metal layer 13 is only 0.1% -1% of the thickness of the substrate base plate, the thickness of the conductive metal layer 13 is far smaller than that of the substrate base plate 10, that is, the conductive metal layer 13 is in a sheet shape, so that when the substrate base plate 10 undergoes a high-temperature process in the subsequent process, the expansion degree of the conductive metal layer 13 is small, and further, the pixel structure film layer on the substrate base plate 10 cannot be extruded, and thus, the pixel structure film layer is not easy to break, and further, the yield of the display device can be improved. In practical applications, the thickness of the conductive metal layer 13 may be greater than or equal to 1 micrometer and less than or equal to 10 micrometers.
In addition, the thickness of the first insulating layer 12 may be less than or equal to the thickness of the substrate base plate first surface S1 to the conductive metal layer 13, and/or the thickness of the second insulating layer 14 may be less than or equal to the thickness of the substrate base plate first surface S2 to the conductive metal layer 13. In practical applications, the surface of the first insulating layer 12 may be slightly lower than the first surface S1 of the substrate 10, and the surface of the second insulating layer 14 may be slightly lower than the second surface S2 of the substrate 10, so that even if the conductive metal layer 13 slightly expands in a high-temperature process, a certain height space exists between the first insulating layer 12 and the first surface S1 of the substrate, and between the second insulating layer 14 and the second surface S2 of the substrate, which can be used for buffering, and can further avoid the extrusion of the pixel structure film disposed on the substrate 10.
As shown in fig. 1, in one implementation, the outer diameter of the sidewall of the through hole 11 contacting the second insulating layer 14 may be smaller than the outer diameter of the sidewall of the through hole 11 contacting the conductive metal layer 13, so that the second insulating layer 14 may contact the conductive metal layer 13 in a larger area while having a smaller thickness, thereby saving the material of the second insulating layer 14. In addition, in a specific application, the center of the first insulating layer 12, the center of the second insulating layer 14, and the center of the conductive metal layer portion between the first insulating layer 12 and the second insulating layer 14 may overlap in the thickness direction of the base substrate 10.
Fig. 2 shows a top view of a first surface of a substrate base plate according to a first embodiment of the present invention, fig. 3 shows a top view of a second surface of a substrate base plate according to a first embodiment of the present invention, and as shown in fig. 2 and fig. 3, a cross section of the through hole 11 perpendicular to a thickness direction of the substrate base plate may be a circle, but in practical application, the cross section may also be another shape such as an ellipse, and the embodiment of the present invention is not limited thereto.
Further, in a specific application, the material of the conductive metal layer 13 may be at least one of copper, aluminum, silver, and titanium, that is, the material of the conductive metal layer 13 may be a single metal or an alloy, which is not limited in this embodiment of the present invention.
In addition, in practical applications, the material of the first insulating layer 12 and/or the second insulating layer 14 may be polysiloxane, and of course, other organic insulating materials capable of withstanding high temperature processes may also be used, which is not specifically limited in this embodiment of the present invention. It should be noted that the high temperature process mentioned in the embodiments of the present invention may refer to a process with a processing temperature of 200 degrees celsius or higher. In a specific application, the material of the first insulating layer 12 and the material of the second insulating layer 14 may be the same or different, and this embodiment of the present invention is not limited to the specific one.
In addition, in the embodiment of the present invention, the material of the substrate base plate 10 may be silicon, glass, or polyimide, which is not particularly limited in the embodiment of the present invention.
It should be noted that the thickness described in each embodiment of the present invention refers to the thickness of each structure along the thickness direction of the substrate base plate, and the thickness of each structure along other directions is not specifically limited in this embodiment of the present invention.
In the embodiment of the invention, the substrate base plate comprises a through hole, and a first insulating layer, a conductive metal layer and a second insulating layer are stacked in the through hole along the direction of pointing the first surface of the substrate base plate to the second surface of the substrate base plate; wherein the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole; the second insulating layer is provided with a via hole extending to the conductive metal layer; the first surface of the substrate base plate is opposite to the second surface of the substrate base plate. In the embodiment of the invention, a part of the conductive metal layer on the first surface of the substrate base plate can be used for connecting one of the pixel circuit and the driving circuit, and a part of the conductive metal layer exposed from the bottom of the via hole of the second insulating layer on one side of the second surface of the substrate base plate can be used for connecting the other of the pixel circuit and the driving circuit, so that the pixel circuit can be prepared on one side of the substrate base plate, the driving circuit is arranged on the other side of the substrate base plate, and the pixel circuit can be connected with the driving circuit through the via hole extending to the conductive metal layer in the second insulating layer and the conductive metal layer. Therefore, the pixel circuit and the driving circuit can be respectively arranged on two surfaces of the substrate back to back, so that a frame region is not required to be arranged for shielding, the frame region of the display device can be reduced, and the screen occupation ratio of the display device can be improved.
Example two
Referring to fig. 4, a flow chart illustrating steps of a method for manufacturing a substrate base plate according to a second embodiment of the present invention is shown, where the method may include the following steps:
step 401: a substrate is provided.
In an embodiment of the present invention, a substrate 10 may be provided, where the substrate 10 may be a silicon substrate, a glass substrate, or a flexible Polyimide (PI) substrate, and the embodiment of the present invention is not limited in this respect.
Step 402: a first blind via is formed on a first surface of a substrate base.
In the embodiment of the present invention, referring to fig. 5, the first blind via 01 may be formed on the first surface S1 of the substrate base 10 by a drilling method such as laser drilling. The first blind hole 01 can penetrate through 80-95% of the thickness of the substrate base plate, and a target angle alpha between the side wall of the first blind hole 01 and the thickness direction of the substrate base plate 10 can be smaller than or equal to 30 degrees.
Step 403: and forming a conductive metal layer on the first surface of the substrate base plate, wherein the conductive metal layer covers the bottom and at least part of the side wall of the first blind hole.
In this step, the conductive metal layer 13 may be formed on the first surface S1 of the substrate base plate 10, the bottom of the first blind via 01 and at least a portion of the sidewall by a sputtering (Sputter) process or an evaporation process, as shown in fig. 6. Here, the conductive metal layer 13 may extend from a part or all of the sidewalls of the first blind via 01 to the first surface S1 of the substrate base 10. Devices subsequently disposed on the first surface S1 of the substrate base plate may be partially in conductive communication with the conductive metal layer disposed on the first surface S1. In practical applications, the thickness ratio between the thickness of the conductive metal layer 13 and the thickness of the substrate base plate 10 may be greater than or equal to 0.1% and less than or equal to 1%. The thickness of the conductive metal layer 13 may be greater than or equal to 1 micrometer and less than or equal to 10 micrometers. The material of the conductive metal layer 13 may be at least one of copper, aluminum, silver, and titanium.
Step 404: and forming a first insulating layer on one side of the conductive metal layer positioned in the first blind hole, which is close to the first surface of the substrate base plate.
In this step, referring to fig. 7, a first insulating layer 12 may be coated on the conductive metal layer 13 located within the first blind via 01 by a solution method. The thickness of the first insulating layer 12 may be smaller than or equal to the difference between the thickness of the first blind via 01 and the thickness of the conductive metal layer 13, that is, the surface of the first insulating layer 12 may be lower than the first surface S1 of the substrate base plate 10 or flush with the first surface S1.
In addition, in practical applications, the material of the first insulating layer 12 may be an organic insulating material such as polysiloxane that can withstand a high temperature process, and this is not particularly limited in the embodiment of the present invention.
Step 405: and forming a second blind hole on a second surface of the substrate base plate, which is opposite to the first surface, wherein the first blind hole and the second blind hole form a through hole.
In the embodiment of the present invention, as shown in fig. 8, the second blind via 02 may be formed on the second surface S2 of the substrate opposite to the first surface S1 of the substrate by drilling such as laser drilling. The second blind hole 02 can penetrate through the substrate by 5-20% of the thickness. The second blind hole 02 can extend to the first blind hole 01, so as to form a through hole together with the first blind hole 01, and correspondingly, the bottom of the second blind hole 02 is the conductive metal layer 13, so that the conductive metal layer 13 can be exposed from the second blind hole 02.
Step 406: and forming a second insulating layer in the second blind hole, wherein the second insulating layer is provided with a through hole extending to the conductive metal layer.
In this step, referring to fig. 9, the second insulating layer 14 may be filled in the second blind via 02 by a solution method, so that the second insulating layer 14 covers the bottom and at least a portion of the sidewall of the second blind via 02, and then, as shown in fig. 10, the second insulating layer 14 may be patterned to form a via hole 141 extending to the conductive metal layer 13, that is, a portion of the conductive metal layer 13 at the bottom of the second blind via 02 may be exposed, and the bottom of the via hole 141 is the conductive metal layer 13. The devices subsequently disposed on the second surface S2 of the substrate base plate can be electrically connected to the portion of the conductive metal layer exposing the second-insulation-layer via 141, so that the devices disposed on the first surface S1 of the substrate base plate can be connected to the devices disposed on the second surface S2 of the substrate base plate through the via 141 in the second insulation layer 14 extending to the conductive metal layer 13 and the conductive metal layer 13.
In practical applications, the thickness of the second insulating layer 14 may be less than or equal to the depth of the second blind hole 02, that is, the surface of the second insulating layer 14 may be lower than the second surface S2 of the substrate base plate 10 or flush with the second surface S2 of the substrate base plate 10. In addition, in practical applications, the material of the second insulating layer 14 may also be an organic insulating material such as polysiloxane that can withstand a high temperature process, and this is not particularly limited in the embodiment of the present invention.
In practical applications, as shown in fig. 3, a cross section of the via hole 141 of the second insulating layer 14 in a direction perpendicular to the thickness direction of the substrate may be circular, or may be in other shapes, and a center of the via hole 141 and a center of the second blind hole 02 may overlap in the thickness direction of the substrate, or may not overlap, which is not particularly limited in the embodiment of the present invention.
Further, the pixel circuit may be fabricated on the first surface S1 of the substrate base 10 and the driving circuit may be fabricated on the second surface S2 of the substrate base 10, and of course, the pixel circuit may also be fabricated on the second surface S2 of the substrate base 10 and the driving circuit may also be fabricated on the first surface S1 of the substrate base 10, which is not particularly limited in the embodiments of the present invention.
In the embodiment of the present invention, a substrate may be provided, a first blind via may be formed on a first surface of the substrate, a conductive metal layer may be formed on the first surface of the substrate, the conductive metal layer covers a bottom and a sidewall of the first blind via, a first insulating layer may be formed on a side of the conductive metal layer located in the first blind via, the side being close to the first surface of the substrate, a second blind via may be formed on a second surface of the substrate, the second surface being opposite to the first surface, the first blind via and the second blind via forming a through hole, a second insulating layer may be formed in the second blind via, and the second insulating layer is provided with a via hole extending to the conductive metal layer. In the embodiment of the invention, a part of the conductive metal layer on the first surface of the substrate base plate can be used for connecting one of the pixel circuit and the driving circuit, and a part of the conductive metal layer exposed from the bottom of the via hole of the second insulating layer on one side of the second surface of the substrate base plate can be used for connecting the other of the pixel circuit and the driving circuit, so that the pixel circuit can be prepared on one side of the substrate base plate, the driving circuit is arranged on the other side of the substrate base plate, and the pixel circuit and the driving circuit can be connected through the via hole extending to the conductive metal layer in the second insulating layer and the conductive metal layer. Therefore, the pixel circuit and the driving circuit can be respectively arranged on two surfaces of the substrate back to back, so that a frame region is not required to be arranged for shielding, the frame region of the display device can be reduced, and the screen occupation ratio of the display device can be improved.
EXAMPLE III
The embodiment of the invention also discloses an array substrate, which comprises the substrate base plate, and the pixel circuit and the drive circuit which are respectively arranged on the first surface and the second surface of the substrate base plate, which are opposite to each other; the pixel circuit and the driving circuit are connected through a via hole extending to the conductive metal layer in the second insulating layer and the conductive metal layer.
In the embodiment of the invention, the array substrate comprises a substrate base plate, the substrate base plate comprises a through hole, and a first insulating layer, a conductive metal layer and a second insulating layer are stacked in the through hole along the direction from the first surface of the substrate base plate to the second surface of the substrate base plate; wherein the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole; the second insulating layer is provided with a via hole extending to the conductive metal layer; the first surface of the substrate base plate is opposite to the second surface of the substrate base plate. In the embodiment of the invention, a part of the conductive metal layer on the first surface of the substrate base plate can be used for connecting one of the pixel circuit and the driving circuit, and a part of the conductive metal layer exposed from the bottom of the via hole of the second insulating layer on one side of the second surface of the substrate base plate can be used for connecting the other of the pixel circuit and the driving circuit, so that the pixel circuit can be prepared on one side of the substrate base plate, the driving circuit is arranged on the other side of the substrate base plate, and the pixel circuit and the driving circuit can be connected through the via hole extending to the conductive metal layer in the second insulating layer and the conductive metal layer. Therefore, the pixel circuit and the driving circuit can be respectively arranged on two surfaces of the substrate back to back, so that a frame region is not required to be arranged for shielding, the frame region of the display device can be reduced, and the screen occupation ratio of the display device can be improved.
Example four
The embodiment of the invention also discloses a display device which comprises the array substrate.
In the embodiment of the present invention, the display device may be: liquid crystal display panels, electronic paper, OLED (Organic Light-Emitting Diode) panels, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigators and other products or components with display functions.
In the embodiment of the invention, the array substrate of the display device comprises a substrate base plate, wherein the substrate base plate comprises a through hole, and a first insulating layer, a conductive metal layer and a second insulating layer are stacked in the through hole along the direction from the first surface of the substrate base plate to the second surface of the substrate base plate; wherein the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole; the second insulating layer is provided with a via hole extending to the conductive metal layer; the first surface of the substrate base plate is opposite to the second surface of the substrate base plate. In the embodiment of the invention, a part of the conductive metal layer on the first surface of the substrate base plate can be used for connecting one of the pixel circuit and the driving circuit, and a part of the conductive metal layer exposed from the bottom of the via hole of the second insulating layer on one side of the second surface of the substrate base plate can be used for connecting the other of the pixel circuit and the driving circuit, so that the pixel circuit can be prepared on one side of the substrate base plate, the driving circuit is arranged on the other side of the substrate base plate, and the pixel circuit and the driving circuit can be connected through the via hole extending to the conductive metal layer in the second insulating layer and the conductive metal layer. Therefore, the pixel circuit and the driving circuit can be respectively arranged on two surfaces of the substrate back to back, so that a frame region is not required to be arranged for shielding, the frame region of the display device can be reduced, and the screen occupation ratio of the display device can be improved.
While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present invention is not limited by the illustrated ordering of acts, as some steps may occur in other orders or concurrently with other steps in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The substrate, the manufacturing method thereof, the array substrate and the display device provided by the invention are described in detail above, and the principle and the implementation of the invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (14)
1. The substrate base plate is characterized by comprising a through hole, wherein a first insulating layer, a conductive metal layer and a second insulating layer are stacked in the through hole along the direction from a first surface of the substrate base plate to a second surface of the substrate base plate; wherein the content of the first and second substances,
the conductive metal layer extends to the first surface of the substrate base plate along the side wall of the through hole;
the second insulating layer is provided with a via hole extending to the conductive metal layer;
the first surface of the substrate base plate is opposite to the second surface of the substrate base plate;
wherein a surface of the first insulating layer is lower than the first surface of the substrate base plate, and a surface of the second insulating layer is lower than the second surface of the substrate base plate.
2. The substrate base plate of claim 1, wherein a cross section of the first insulating layer is an inverted trapezoid or a rectangle within the through hole; wherein the cross-section is parallel to a thickness direction of the substrate base.
3. The substrate base of claim 2, wherein a target angle between a sidewall of the via in contact with the conductive metal layer and a thickness direction of the substrate base is less than or equal to 30 degrees.
4. The substrate base plate according to claim 1, wherein a first thickness ratio between a thickness of the second insulating layer and a thickness of the substrate base plate is greater than or equal to 5% and less than or equal to 20%.
5. The substrate base plate according to claim 1, wherein a second thickness ratio between the thickness of the conductive metal layer and the thickness of the substrate base plate is greater than or equal to 0.1% and less than or equal to 1%.
6. The substrate of claim 1, wherein the conductive metal layer has a thickness greater than or equal to 1 micron and less than or equal to 10 microns.
7. The substrate base plate of claim 1, wherein the material of the conductive metal layer is at least one of copper, aluminum, silver and titanium.
8. The substrate base plate according to claim 1, wherein a material of the first insulating layer and/or the second insulating layer is polysiloxane.
9. The substrate base plate of claim 1, wherein the material of the substrate base plate is silicon, glass, or polyimide.
10. An array substrate, comprising the substrate of any one of claims 1 to 9, and pixel circuits and driving circuits respectively disposed on a first surface and a second surface of the substrate opposite to each other;
the pixel circuit and the driving circuit are connected through the conductive metal layer and a via hole extending from the second insulating layer to the conductive metal layer.
11. A display device comprising the array substrate according to claim 10.
12. A method for preparing a substrate base plate, which is characterized by comprising the following steps:
providing a substrate base plate;
forming a first blind hole on a first surface of the substrate base plate;
forming a conductive metal layer on the first surface of the substrate base plate, wherein the conductive metal layer covers the bottom and at least part of the side wall of the first blind hole;
forming a first insulating layer on one side, close to the first surface of the substrate base plate, of the conductive metal layer in the first blind hole;
forming a second blind hole on a second surface of the substrate base plate opposite to the first surface, wherein the first blind hole and the second blind hole form a through hole;
forming a second insulating layer in the second blind hole, wherein the second insulating layer is provided with a through hole extending to the conductive metal layer;
wherein a surface of the first insulating layer is lower than the first surface of the substrate base plate, and a surface of the second insulating layer is lower than the second surface of the substrate base plate.
13. The method of claim 12, wherein forming a second insulating layer within the second blind via comprises:
filling a second insulating layer in the second blind hole by a solution method;
and patterning the second insulating layer to form a via hole extending to the conductive metal layer.
14. The method of claim 12, wherein forming a conductive metal layer on the first surface of the substrate base plate comprises:
and forming a conductive metal layer on the first surface of the substrate base plate, the bottom of the first blind hole and at least part of the side wall through a sputtering process or an evaporation process.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910238145.8A CN109935168B (en) | 2019-03-27 | 2019-03-27 | Substrate base plate and preparation method thereof, array base plate and display device |
| PCT/CN2020/074976 WO2020192286A1 (en) | 2019-03-27 | 2020-02-13 | Substrate and preparation method therefor, and array substrate and display device |
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| CN201910238145.8A CN109935168B (en) | 2019-03-27 | 2019-03-27 | Substrate base plate and preparation method thereof, array base plate and display device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108535928A (en) * | 2018-04-13 | 2018-09-14 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel and display device |
| CN109244086A (en) * | 2018-09-29 | 2019-01-18 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel, display device |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6214728B1 (en) * | 1998-11-20 | 2001-04-10 | Chartered Semiconductor Manufacturing, Ltd. | Method to encapsulate copper plug for interconnect metallization |
| JP4332925B2 (en) * | 1999-02-25 | 2009-09-16 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| CN100508137C (en) * | 2003-12-02 | 2009-07-01 | 株式会社半导体能源研究所 | Electronic appliance, and semiconductor apparatus and formation method therefor |
| JP4745007B2 (en) * | 2005-09-29 | 2011-08-10 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP4483896B2 (en) * | 2007-05-16 | 2010-06-16 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| JP4825259B2 (en) * | 2008-11-28 | 2011-11-30 | 三菱電機株式会社 | Power semiconductor module and manufacturing method thereof |
| CN103377990B (en) * | 2012-04-18 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via structure |
| CN103594414B (en) * | 2012-08-17 | 2016-05-04 | 华邦电子股份有限公司 | Groove isolation construction and forming method thereof |
| CN105845663B (en) * | 2015-01-12 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
| CN106409796A (en) * | 2016-10-25 | 2017-02-15 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display device and manufacturing method thereof |
| JP6823443B2 (en) * | 2016-12-07 | 2021-02-03 | キヤノン株式会社 | Display device and its manufacturing method |
| CN106681067B (en) * | 2016-12-20 | 2019-01-22 | 深圳市华星光电技术有限公司 | Display device |
| WO2018221256A1 (en) * | 2017-05-29 | 2018-12-06 | 株式会社ジャパンディスプレイ | Display device |
| CN207124195U (en) * | 2017-09-04 | 2018-03-20 | 京东方科技集团股份有限公司 | A kind of OLED display panel and OLED display |
| CN109524421A (en) * | 2019-01-04 | 2019-03-26 | 京东方科技集团股份有限公司 | Interposer substrate and its manufacturing method, array substrate and display device |
| CN109935168B (en) * | 2019-03-27 | 2021-02-26 | 京东方科技集团股份有限公司 | Substrate base plate and preparation method thereof, array base plate and display device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108535928A (en) * | 2018-04-13 | 2018-09-14 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel and display device |
| CN109244086A (en) * | 2018-09-29 | 2019-01-18 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel, display device |
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| WO2020192286A1 (en) | 2020-10-01 |
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