CN109933473A - Chip power consumption of internal memory measurement method, device, equipment and medium - Google Patents
Chip power consumption of internal memory measurement method, device, equipment and medium Download PDFInfo
- Publication number
- CN109933473A CN109933473A CN201910194574.XA CN201910194574A CN109933473A CN 109933473 A CN109933473 A CN 109933473A CN 201910194574 A CN201910194574 A CN 201910194574A CN 109933473 A CN109933473 A CN 109933473A
- Authority
- CN
- China
- Prior art keywords
- memory
- power consumption
- test cell
- activity
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
This application discloses a kind of chip power consumption of internal memory measurement methods, it include: in the wafer probing stage, default memory activity is generated by running memory self detection method, the memory self detection method includes test cell sequence, each of test cell sequence test cell includes one group of memory activity, and the default memory activity can simulate the activity of the memory under normal operation mode；The corresponding power consumption of the default memory activity is measured to determine chip power consumption of internal memory.This method only activates the memory part in chip, and the logic circuitry portions in chip are still in closed state, thus measurement result not will receive logic circuitry portions interference, and each chip can be measured, rather than it inspects by random samples after packaging, the process variation bring measurement error of different wafer batches can thus be overcome, improve measurement accuracy.Disclosed herein as well is a kind of chip power consumption of internal memory measuring device, equipment and media.
Description
Technical field
This application involves semiconductor field more particularly to a kind of chip power consumption of internal memory measurement method, device, equipment and meters
Calculation machine storage medium.
Background technique
With the raising of transistor integrated level on chip, the switch energy consumption of transistor is so led there is no significant decline
The promotion of chip power-consumption is caused, so that therefore chip cooling becomes more and more difficult, power problems become many electronic products
The key constraints that can be promoted.
In order to meet the needs of user is growing, the storage performance of chip memory is continuously improved, and chip power-consumption is caused to exist
Accounted in the power consumption of entire chip it is relatively high, in this way, function of the measurement of power loss of memory under normal operating conditions for entire chip
Consumption measurement is most important.Power consumption of internal memory specifically includes operation power consumption, read-write power consumption and input and output power consumption.Wherein, power consumption is run
It is that memory carries out power consumption caused by precharge operation, when read-write power consumption is that data are read from memory or memory is written
Caused power consumption, input and output power consumption are caused when being driving data bus and close from the signal of chip other parts
Power consumption.
Industry provides the methods of two kinds of measurement power consumption of internal memory at present, and a kind of method is using special measurement chip
Agilent 3470 directly measures power consumption of internal memory, and another method is that the power consumption model of activity count based on memory measures memory function
Consumption.However, both methods is just to carry out the measurement and analysis of power consumption of internal memory after chip completes encapsulation.This memory function
The measurement method of consumption has that two first problems are, when chip operates normally in computer or system in progress
The measurement of power loss deposited, since main memory circuit part and logic circuitry portions are all being run, be difficult by the power consumption of main memory circuit with patrol
The power consumption for collecting circuit is accurately distinguished, to influence the precision of power consumption of internal memory measurement；Second Problem is, due to chip system
Process variation in making, the chip of different batches wafer level packaging, the actual power loss of memory are not identical；Even same
On one wafer, the memory actual power loss of different chips be also not quite similar chip complete encapsulation after carry out memory power consumption
Measurement, can face this process variation due to different wafer batches so as to cause power consumption of internal memory variation, in this can also cause
Deposit the error of measurement of power loss.
Summary of the invention
In view of this, this method is surveyed in the wafer probing stage this application provides a kind of chip power consumption of internal memory measurement method
Power consumption of internal memory is measured, power consumption when only main memory circuit activation on the one hand can be measured, the another aspect needle survey stage can be realized same
Wafer difference chip full inspection, thus accuracy with higher.Accordingly, present invention also provides corresponding chip power consumption of internal memory
Measuring device.
The application first aspect provides a kind of chip power consumption of internal memory measurement method, which comprises
In the wafer probing stage, default memory activity, the memory self-test are generated by running memory self detection method
Algorithm includes test cell sequence, and each of described test cell sequence test cell includes one group of memory activity, described
Default memory activity can simulate the activity of the memory under normal operation mode；
The corresponding power consumption of the default memory activity is measured to determine chip power consumption of internal memory.
Optionally, the test cell generates in the following way:
Obtain the corresponding simulation waveform of memory activity under normal operation mode；
Memory active sequences are extracted from the simulation waveform, are survived within the memory activity in the memory active sequences
Dynamic tuple form characterization, the memory activity tuple include current time, the current time corresponding internal memory operation, it is described in
It deposits and operates corresponding memory address and the corresponding word content of the memory address；
The test cell is generated according to the memory active sequences.
Optionally, generating the test cell according to the memory active sequences includes:
The test cell is generated according to the quantity of all types of internal memory operations in the memory active sequences；Alternatively,
The test cell is generated according to the power consumption of the memory active sequences.
Optionally, the quantity according to all types of internal memory operations in the memory active sequences generates the test cell
Include:
For any kind internal memory operation, determine that each memory in chip generates the average value of the type internal memory operation；
Using the ratio of the quantity of word in the average value and memory as the type internal memory operation in the test cell
Number；
The test cell is generated according to the number of all types of internal memory operations.
Optionally, described to include: according to the power consumption of the memory active sequences generation test cell
Obtain initial testing unit；
Determine the first power consumption that the initial testing unit application to memory generates；
It is updated according to the comparison result of first power consumption the second power consumption corresponding with internal memory operation under normal operation mode
The initial testing unit, until the comparison result of first power consumption and second power consumption meets preset condition；
The initial testing unit for meeting preset condition is determined as the test cell.
Optionally, the method also includes:
Memory active sequences described in cutting obtain multiple memory activity segments；
It is then described to include: according to the memory active sequences generation test cell
Corresponding test cell is generated according to each of the multiple memory activity segment memory activity segment.
Optionally, the method also includes:
The test cell is encoded to obtain source unit and self-test parameter；The self-test parameter is for extending the source
Unit obtains multiple test cells.
The application second aspect provides a kind of chip power consumption of internal memory measuring device, and described device includes:
Generation module, for generating default memory activity, institute by running memory self detection method in the wafer probing stage
Stating memory self detection method includes test cell sequence, and each of described test cell sequence test cell includes in one group
Survival is dynamic, and the default memory activity can simulate the activity of the memory under normal operation mode；
Measurement module, for measuring the corresponding power consumption of the default memory activity to determine chip power consumption of internal memory.
Optionally, the generation module is also used to generate the test cell in the following manner:
Obtain the corresponding simulation waveform of memory activity under normal operation mode；
Memory active sequences are extracted from the simulation waveform, are survived within the memory activity in the memory active sequences
Dynamic tuple form characterization, the memory activity tuple include current time, the current time corresponding internal memory operation, it is described in
It deposits and operates corresponding memory address and the corresponding word content of the memory address；
The test cell is generated according to the memory active sequences.
Optionally, the generation module is specifically used for when generating the test cell according to the memory active sequences:
The test cell is generated according to the quantity of all types of internal memory operations in the memory active sequences；Alternatively,
The test cell is generated according to the power consumption of the memory active sequences.
Optionally, the generation module is generating institute according to the quantity of all types of internal memory operations in the memory active sequences
When stating test cell, it is specifically used for:
For any kind internal memory operation, determine that each memory in chip generates the average value of the type internal memory operation；
Using the ratio of the quantity of word in the average value and memory as the type internal memory operation in the test cell
Number；
The test cell is generated according to the number of all types of internal memory operations.
Optionally, the generation module is when generating the test cell according to the power consumption of the memory active sequences, tool
Body is used for:
Obtain initial testing unit；
Determine the first power consumption that the initial testing unit application to memory generates；
It is updated according to the comparison result of first power consumption the second power consumption corresponding with internal memory operation under normal operation mode
The initial testing unit, until the comparison result of first power consumption and second power consumption meets preset condition；
The initial testing unit for meeting preset condition is determined as the test cell.
Optionally, described device further include:
Cutting module obtains multiple memory activity segments for memory active sequences described in cutting；
Then the generation module is specifically used for when generating the test cell according to the memory active sequences:
Corresponding test cell is generated according to each of the multiple memory activity segment memory activity segment.
Optionally, described device further include:
Coding module obtains source unit and self-test parameter for encoding to the test cell；The self-test parameter
Multiple test cells are obtained for extending the source unit.
The application third aspect provides a kind of chip power consumption of internal memory measuring device, and the equipment includes processor and deposits
Reservoir:
Said program code is transferred to the processor for storing program code by the memory；
The processor is in the chip according to instruction execution the application first aspect in said program code
Deposit power consumption measurement method.
The application fourth aspect provides a kind of computer readable storage medium, and the computer readable storage medium is used for
Program code is stored, said program code is for executing chip power consumption of internal memory measurement method described in the application first aspect.
As can be seen from the above technical solutions, the embodiment of the present application has the advantage that
The embodiment of the present application provides a kind of chip power consumption of internal memory measurement method, this method be by for memory from
What test structure was realized, in the wafer probing stage, default memory activity, the self detection method are generated by operation self detection method
Including test cell sequence, each test cell in test cell sequence can simulate the interior survival under normal operation mode
It is dynamic, thus the corresponding power consumption of default memory activity can be measured as chip power consumption of internal memory.Wafer probing stage running memory is certainly
Testing algorithm only activates the memory part in chip, and the logic circuitry portions in chip are still in closed state, thus measures
As a result it not will receive logic circuitry portions interference, and each chip can be measured, rather than inspect by random samples after packaging,
The process variation bring measurement error of different wafer batches can thus be overcome, improve measurement accuracy.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application without any creative labor, may be used also for those of ordinary skill in the art
To obtain other drawings based on these drawings.
Fig. 1 is the scene framework figure of chip memory measurement method in the embodiment of the present application；
Fig. 2 is the flow chart of chip memory measurement method in the embodiment of the present application；
Fig. 3 is the method flow diagram that test cell is generated in the embodiment of the present application；
Fig. 4 is that power consumption generates the schematic diagram of test cell based on memory in the embodiment of the present application；
Fig. 5 is a structural schematic diagram for applying for chip power consumption of internal memory measuring device in embodiment.
Specific embodiment
In order to make those skilled in the art more fully understand application scheme, below in conjunction in the embodiment of the present application
Attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only this
Apply for a part of the embodiment, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall in the protection scope of this application.
The description and claims of this application and term " first ", " second ", " third ", " in above-mentioned attached drawing
The (if present)s such as four " are to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should manage
The data that solution uses in this way are interchangeable under appropriate circumstances, so that embodiments herein described herein for example can be to remove
Sequence other than those of illustrating or describe herein is implemented.In addition, term " includes " and " having " and theirs is any
Deformation, it is intended that cover it is non-exclusive include, for example, containing the process, method of a series of steps or units, system, production
Product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include be not clearly listed or for this
A little process, methods, the other step or units of product or equipment inherently.
For being difficult to accurately distinguish the power consumption of main memory circuit and the power consumption of logic circuit in the prior art, influence
Power consumption of internal memory measurement accuracy and chip complete encapsulation after carry out power consumption of internal memory measurement lead to not differentiation different batches even
The power consumption of same batch difference chip, thus the technical issues of introducing measurement error, this application provides a kind of chip memory function
Measurement method is consumed, this method is combined using the auto testing instrument (Automatic Test Equipment, ATE) for chip
What self detection method was realized.
Specifically, in the wafer probing stage, by ATE running memory self detection method generate default memory activity,
The memory self detection method includes test cell sequence, and each of described test cell sequence test cell includes one group
Memory activity, the default memory activity can simulate the activity of the memory under normal operation mode, then by described in ATE measurement
The default movable corresponding power consumption of memory is to determine chip power consumption of internal memory.In the method, ATE is in wafer probing stage running memory
Self detection method can be realized the memory part only activated in chip, and the logic circuitry portions in chip are still in closing shape
State, thus measurement result not will receive logic circuitry portions interference, and at this stage can to chip each in wafer into
Row measurement, rather than inspect by random samples after packaging, it is thus possible to the process variation bring measurement error for overcoming different wafer batches mentions
High measurement accuracy.
In order to enable the technical solution of the application it is clearer, it can be readily appreciated that being mentioned below with reference to concrete scene to the application
The chip power consumption of internal memory measurement method of confession is introduced.The scene framework of chip power consumption of internal memory measurement method shown in Figure 1
Figure, the scene are the wafer probing stage of chip manufacturing process, include ATE 10 and wafer 20 in the scene, wafer 20 can be cut
It cuts encapsulation and forms multiple chips, for each chip, ATE generates default memory activity by running memory self detection method, should
Default memory activity can simulate the activity of the memory under normal operation mode, thus, it is right that ATE can measure the default memory activity
The power consumption answered is to determine chip power consumption of internal memory, in this way, ATE can determine the corresponding chip memory function of each chip of wafer
Consumption, overcomes the process variation bring measurement error of different wafer batches and same wafer.
Next, will be carried out from the angle of ATE to chip power consumption of internal memory measurement method provided by the embodiments of the present application detailed
It introduces.The flow chart of chip power consumption of internal memory measurement method shown in Figure 2, this method comprises:
S201: in the wafer probing stage, default memory activity is generated by running memory self detection method.
The memory self detection method includes test cell sequence, each of described test cell sequence test cell
Comprising one group of memory activity, the default memory activity can simulate the activity of the memory under normal operation mode.
Specifically, memory can make full use of by ATE running memory self detection method in the wafer probing stage as soon as possible
The characteristics of self-test framework, imitates the internal memory operation under normal operating condition, and by interior survival under normal operating conditions
It is dynamic to be minimized with self-test framework based on memory using the memory activity difference that memory self detection method generates.Also, such
Under situation, ATE only activates the memory part in chip, and the logic circuitry portions in chip is kept to be in close state, in this way,
The chip power-consumption that ATE measurement obtains does not include power consumption caused by logic circuitry portions work in chip.
S202: the movable corresponding power consumption of the measurement default memory is to determine chip power consumption of internal memory.
Since logic circuitry portions are in close state, ATE measures chip power-consumption that is, measuring default memory
The corresponding power consumption of activity, and default memory activity is the memory activity imitated under normal operation mode, it therefore, can be by default memory
The corresponding power consumption of activity corresponds to power consumption namely chip power consumption of internal memory as the memory activity under normal operation mode.
From the foregoing, it will be observed that the embodiment of the present application provides a kind of chip power consumption of internal memory measurement method, this method is by being directed to
What the self-test framework of memory was realized, in the wafer probing stage, default memory activity is generated by operation self detection method, it should
Self detection method includes test cell sequence, and each test cell in test cell sequence can simulate under normal operation mode
Memory activity, thus the corresponding power consumption of default memory activity can be measured as chip power consumption of internal memory.Wafer probing stage fortune
Row memory self detection method only activates the memory part in chip, and the logic circuitry portions in chip are still in closed state,
Thus measurement result not will receive logic circuitry portions interference, and can measure to each chip, rather than seal
It is inspected by random samples after dress, it is thus possible to overcome the process variation bring measurement error of different wafer batches, improve measurement accuracy.
In the embodiment depicted in figure 2, ATE is the interior survival simulated under normal operation mode by memory self detection method
It is dynamic, wherein memory self detection method includes a test cell sequence, and test cell sequence is by least one test cell group
At each test cell includes one group of memory activity, and wherein memory activity can be characterized by internal memory operation, such as read operation
(READ), write operation (WRITE) or without operation (NOP).
Specifically, x NOP operation, the test of y READ operation and z WRITE operation are executed to some word in memory
Unit can be registered as { xNOP, yRead, zWRITE }, wherein x, y, and z is natural number.In memory self-testing structure, to certain
A specific memory, a test cell are applied to word all in the memory with being serialized, own in self detection method
Test cell is applied to the memory with being serialized.Based on this, the internal memory operation in memory self-test can be used in imitating normal
Memory activity under operational mode executes memory self detection method on ATE and measures at this time during wafer probing
Power consumption is deposited, that is, obtaining the real memory power consumption under normal operation mode.
In practical application, can be by the corresponding simulation waveform of memory activity under normal operation mode to determine test
Unit.Fig. 3 is referred to, it illustrates the method flow diagrams for generating test cell, this method comprises:
S301: the corresponding simulation waveform of memory activity under normal operation mode is obtained.
Wherein, simulation waveform can be obtained from design verification environment Imitating functional test.
S302: memory active sequences are extracted from the simulation waveform.
Dynamic tuple form of surviving within memory activity in the memory active sequences characterizes, the memory activity tuple packet
Include current time, the current time corresponding internal memory operation, the corresponding memory address of the internal memory operation and the memory
The corresponding word content in address.
Since a test cell contains the operation of limited quantity, when the test cell is applied to some memory, it
The internal memory operation of limited quantity can only be generated however, test case large-scale for one, in the normal operating mode interior
Active sequences are deposited with very big length it is therefore possible to use multiple test cells simulate entire memory active sequences
In specific implementation, entire memory active sequences can be cut into a series of segment, obtains multiple interior survivals
Movable plate section, each memory activity segment includes the memory activity tuple of a fixed quantity, raw based on multiple memory activity segments
At test cell corresponding with each memory activity segment, for simulating entire memory active sequences.Wherein, the fixed quantity
It can be arranged according to actual needs.As an example, each segment may include the memory activity of 1024 clock cycle
Tuple.
S303: the test cell is generated according to the memory active sequences.
When the difference of the memory active sequences under memory active sequences and normal operation mode meets preset condition, such as reach
Minimum value is less than preset threshold, then can export the memory active sequences and be used as test cell.Wherein, memory activity sequence
The difference of column can be characterized by least one of internal memory operation and power consumption of internal memory.Based on this, this application provides two
Kind generates the implementation of test cell according to memory active sequences.
A kind of implementation is to generate the test singly according to the quantity of internal memory operations all types of in memory active sequences
Member.Specifically, for any kind internal memory operation, determine that each memory in chip generates the average value of the type internal memory operation, it will
Number of the ratio of the quantity of word as the type internal memory operation in the test cell in the average value and memory, according to each
The number of type memory operation generates the test cell.
The process for generating test cell according to internal memory operation in memory active sequences is said below with reference to specific example
It is bright.
For some segment in a memory active sequences, it is desirable that using the test cell of its corresponding memory self-test
Onto all words of memory, it can produce same amount of internal memory operation and assume that certain chip includes K same memories, often
The quantity of the word of a memory is N, and M is the maximum memory operation amount that may be embodied in a test cell in such feelings
Under condition, a segment of memory active sequences may include N × M clock cycle, wherein K, N, M are positive integer.
For the segment, read operation, write operation and the par without operation of each memory are calculated first, is then used
Following formula generates a test cell { xNOP, yRead, zWRITE } (x+y+z=M):
Wherein, No.NOP per memory, No.READ per memory and No.WRITE per memory distinguish
Characterize the average of average of each memory without operation, the average of each memory read operation, each memory write operation.
In memory self-test, above test cell is applied to N number of word of all K memories, it will with the segment
The read operation of the memory of identical quantity, write operation and without operation for example, it is assumed that some chip includes in 16 same types
It deposits, i.e. K=16, each memory includes 256 words, i.e. N=256.The maximum operation amount that one test cell may include
It is 6, i.e. the length of each segment in the activity of M=6. memory is 256 × 6 clock cycle namely 1536 clock cycle.It is false
It is located in a specific segment, the average of the read operation of each memory is 768 (256 × 3), the write operation of each memory
Average is 256 (256 × 1), and the average without operation of each memory is 512 (256 × 2).Therefore, extremely using formula (1)
(3) test cell generated is { 2NOP, 3READ, 1WRITE }.Executing this test cell to 256 all words will generate
With identical read operation in the normal operating mode, write operation and without operation.
Another implementation is to generate the test cell according to the power consumption of the memory active sequences.Specifically, it obtains
Take initial testing unit；Determine the first power consumption that the initial testing unit application to memory generates；According to first power consumption
The comparison result of the second power consumption corresponding with internal memory operation under normal operation mode updates the initial testing unit, until described
The comparison result of first power consumption and second power consumption meets preset condition；The initial testing unit for meeting preset condition is determined
For the test cell.
In this implementation, by under the memory active sequences that generate memory self-test and memory normal operating condition
The power consumption difference of memory active sequences be reduced to preset value or reach minimum, to export test cell.
The implementation for generating test cell to power consumption based on memory below in conjunction with specific example is described in detail.
For some memory, in two continuous clock cycle, the numerical value variation of a certain position in some word will cause
Power consumption.The specific value of power consumption can be determined by power consumption of internal memory numerical tabular, can so be predicted using this numerical tabular embedding
Enter the power consumption of formula static random access memory.
Fig. 4 illustrates the process of the memory active sequences under the description normal operation based on power consumption calculation.It is assumed that interior
Each word deposited includes T, and T is positive integer, to some specific segment, determines and operates normally first by way of tabling look-up
In the case of internal memory operation caused by power consumption namely the second power consumption, the initial value of the word in memory is then set as 0, i.e. Data
[1:T]=0, and initial testing unit is used as using test cell { 1NOP }, referring to power consumption value table, to calculate this initial survey
Try unit application to memory all words power consumption.Next, comparing under normal operational condition and the function of memory self-test
Is consumed, if relative error is greater than preset threshold, such as 5%, then can be updated in the following order by additional internal memory operation
Test cell: (1) write operation and Data [1:T]=1 be set；(2) write operation and Data [1:T]=0 is set.Updated test
Unit will switch over after updating test cell in the continuous clock cycle to position all in Data [1:T], count again
It calculates and this element is applied to power consumption caused by all words of memory, and be compared with normal operation, until phase
Preset threshold is lower than to error.Finally, the unit using relative error lower than preset threshold is as test corresponding to current clip
Unit
In some possible implementations, the test cell number generated for some memory active sequences is more huge
Greatly, in which case, test cell can be encoded, obtains source unit and self-test parameter, it so can be significantly
Reduce storage pressure, when memory self detection method is performed, the self-test parameter for extend the source unit obtain it is multiple
Test cell, ATE execute multiple test cells, generate corresponding memory activity.
For a source unit { xNOP, yREAD, zWRITE } (x+y+z=M), corresponding self-test parameter includes whole
Number variable loop and one-dimension array MASK [1:M], wherein MASK [i] corresponds to i-th of operation in source unit, if MASK
[i] is set to 1, and i-th of operation will be repeated in object element；Otherwise it will not be in object element and repeats, ginseng
Number loop indicate the number that is repeated of each operation in source units, are based on this, can be passed through following formula and extend and be tested
Unit (may also be referred to as object element):
Wherein, NNOP、NREADAnd NWRITERespectively the quantity in characterization test unit without operation, the quantity of read operation and
The quantity of write operation.During memory self detection method executes, multiple test cells can by based on different loop and
MASK [1:M] extends and is decoded to (6) some source unit using formula (4) and obtains.
Next, the process encoded to test cell is described in detail in conjunction with specific example.
Firstly, it is single that exhaustion goes out all possible source using the test cell generated according to above-described embodiment as object element
First { xNOP, yREAD, zWRITE } (x+y+z=M), to each source unit, such as i-th of source unit, trial is found out can be by
Its one group of object element encoded, and the quantity of this group of object element is recorded in NUM_encode [i] array.
For a source unit { xNOP, yREAD, zWRITE } and object element aNOP,
BREAD, cWRITE }, a, b, c are natural number, it is assumed that the read operation in source unit and object element, write operation, and
The difference of the quantity of no operation is registered as DFread, DFwrite, DFNOP, can specifically be calculated by following formula:
DFread=b-y, DFwrite=c-z, DFNOP=a-x.If integer value DFread, DFwrite, DFNOP is equal, then should
Integer value is denoted as DF.In this case, object element can be by appropriately setting self-test parameter loop and MASK [1:M]
To be encoded as source unit.
In practical application, the corresponding source unit of NUM_encode [i] with maximum value can be determined, also can
The source unit of most object elements is encoded, the source unit and object element are then directed to, generates self-test parameter loop and MASK
[1:M]。
For example, a given source unit { 1NOP, 2READ, 1WRITE } and object element { 2NOP, 3READ, 1WRITE },
DFread=1, DFwrite=0, DFNOP=1 is obtained by calculation.Due to positive integer DFread and DFNOP number having the same
Value, can determine self-test parameter by using such as under type.
Firstly, setting loop initial value, such as loop can be set equal to DF；Then, the numerical value of MASK [1:M] is set,
Specifically, everybody is 0 in initialization Mask [1:M], if DFNOP is not equal to 0, a NOP behaviour is randomly selected from source unit
Make, Mask [i] is assigned a value of 1, if DFread is not equal to 0, a READ operation is randomly selected from source unit, it will be by Mask
[j] is assigned a value of 1, if DFwrite is not equal to 0, a WRITE operation is randomly selected from source unit, MASK [k] is assigned a value of
1, then export loop and MASK [1:M].
In this way, using source unit { 1NOP, 2READ, 1WRITE }, and rightly setting self-test parameter loop is 1 He
MASK [1:4] is [1,1,0,0], Lai Shengcheng object element { 2NOP, 3READ, 1WRITE }.
It is important to note that multiple object elements are encoded as the same source unit and different loop and MASK
[1:M] numerical value, these object elements are removed from the list of uncoded unit, to each source unit, such as i-th of source
The numerical value of unit, corresponding NUM_encode [i] will be also updated accordingly.This process is repeated until all targets
Unit is encoded, by this method, memory self-testing system only retain less source unit and self-test parameter loop and
MASK [1:M], rather than store large-scale object element and power consumption of internal memory test can be realized.
The embodiment of the present application also surveys chip power consumption of internal memory by some graphics processor chips and modem chip
Amount method is assessed.
In one example, it can use the 8th of super micro element company (Advanced Micro Devices, AMD)
For the chip power consumption of internal memory measurement method that graphics processor chip evaluation the application proposes, which uses 16 nanometers of processing procedures, tool
2,000,000,000 transistors are had more than, and use memory self-testing system (Self-Test And Repair, STAR), table 1, table 2 show
Gone out for a certain module therein operation amount comparison result in the case where operating normally environment and under memory self-test environment with
And power consumption compares as a result, as follows:
Table 1
Table 2
As shown in table 1, memory under the memory activity and normal operation environment that test cell generates is determined based on operation amount
Movable maximum relative error determines the memory activity and operate normally under environment that test cell generates less than 15%, based on power consumption
The movable maximum relative error of memory shows that this method more can accurately be imitated by memory self-test less than 5%
The activity of memory under normal operating conditions.
After generating test cell, above-mentioned test cell can also be encoded, table 3 is shown to graphics processor chip
Above-mentioned module uses the present processes coding result, as follows:
Table 3
Wherein, 3 second column of table lists the test cell of generation, these test cells describe all segments in table 1
In the case where operating normally environment memory activity, by using the coding method of the application, all test cells can be compiled
Code is source unit { 1NOP, 2READ, 1WRITE } and relevant self-test parameter.The third column of table 3 and the 4th list loop
With the numerical value of MASK [1:M], in this way, STAR memory self-testing system can only store source unit and relevant
Self-test parameter, and 12 not all test cells, then when executing self detection method, by using (4) to the public affairs of (6)
Source unit and self-test parameter nondestructively can be decoded as 12 test cells by formula.
In another example, the above method provided by the present application is assessed using modem chip.The core
Piece uses 28 nanometers of processing procedures, has more than 300000 transistors, is primarily based on internal memory operation quantity and describes the movable side of memory
Method is assessed, and in this scenario, entire memory active sequences is divided into a series of segments, each segment be set to include
512*6 clock cycle, i.e. 3072 clock cycle, table 4 show the example modem chip, in the case where operating normally environment with
The comparison result of the quantity of read operation and write operation under memory self-test environment, as follows:
Table 4
As shown in table 4, the quantity of the read operation and write operation under environment and under memory self-test environment is operated normally most
Big relative error is less than 10%, thus this method can simulate the memory activity operated normally under environment.
Table 5 shows the coding result for using the present processes to obtain for modem chip, as follows:
Table 5
The second column in table 5 lists the test cell of memory self-test obtained in the first stage, passes through the application
Coding method, all test cells can be encoded as source unit { 1NOP, 1READ, 2WRITE } and relevant self-test
Parameter.The numerical value that the third column of table 5 list loop and MASK [1:M] with the 4th, in this way, STAR memory self-test
System can only store a source unit and relevant self-test parameter, and 12 not all test cells.
The above are some specific implementations of chip power consumption of internal memory measurement method provided by the embodiments of the present application, corresponding
, the embodiment of the present application also provides chip power consumption of internal memory measuring devices, will carry out below from the angle of function modoularization detailed
Explanation.
The structural schematic diagram of chip power consumption of internal memory measuring device shown in Figure 5, the device 500 include:
Generation module 510, for generating survival in default by running memory self detection method in the wafer probing stage
Dynamic, the memory self detection method includes test cell sequence, and each of described test cell sequence test cell includes
One group of memory activity, the default memory activity can simulate the activity of the memory under normal operation mode；
Measurement module 520, for measuring the corresponding power consumption of the default memory activity to determine chip power consumption of internal memory.
Optionally, the generation module 510 is also used to generate the test cell in the following manner:
Obtain the corresponding simulation waveform of memory activity under normal operation mode；
Memory active sequences are extracted from the simulation waveform, are survived within the memory activity in the memory active sequences
Dynamic tuple form characterization, the memory activity tuple include current time, the current time corresponding internal memory operation, it is described in
It deposits and operates corresponding memory address and the corresponding word content of the memory address；
The test cell is generated according to the memory active sequences.
Optionally, the generation module 510 is specific to use when generating the test cell according to the memory active sequences
In:
The test cell is generated according to the quantity of all types of internal memory operations in the memory active sequences；Alternatively,
The test cell is generated according to the power consumption of the memory active sequences.
Optionally, the generation module 510 is raw according to the quantity of all types of internal memory operations in the memory active sequences
When at the test cell, it is specifically used for:
For any kind internal memory operation, determine that each memory in chip generates the average value of the type internal memory operation；
Using the ratio of the quantity of word in the average value and memory as the type internal memory operation in the test cell
Number；
The test cell is generated according to the number of all types of internal memory operations.
Optionally, the generation module 510 according to the power consumption of the memory active sequences generate the test cell when,
It is specifically used for:
Obtain initial testing unit；
Determine the first power consumption that the initial testing unit application to memory generates；
It is updated according to the comparison result of first power consumption the second power consumption corresponding with internal memory operation under normal operation mode
The initial testing unit, until the comparison result of first power consumption and second power consumption meets preset condition；
The initial testing unit for meeting preset condition is determined as the test cell.
Optionally, described device 500 further include:
Cutting module obtains multiple memory activity segments for memory active sequences described in cutting；
Then the generation module is specifically used for when generating the test cell according to the memory active sequences:
Corresponding test cell is generated according to each of the multiple memory activity segment memory activity segment.
Optionally, described device 500 further include:
Coding module obtains source unit and self-test parameter for encoding to the test cell；The self-test parameter
Multiple test cells are obtained for extending the source unit.
The embodiment of the present application also provides a kind of chip power consumption of internal memory measuring device, the equipment includes processor and deposits
Reservoir:
Said program code is transferred to the processor for storing program code by the memory；
The processor is used for according to the instruction execution chip memory provided by the embodiments of the present application in said program code
Power consumption measurement method.
The embodiment of the present application also provides a kind of computer readable storage medium, the computer readable storage medium is used for
Program code is stored, said program code is for executing chip power consumption of internal memory measurement method provided by the embodiment of the present application.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the division of the unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be tied
Another system is closed or is desirably integrated into, or some features can be ignored or not executed.Another point, it is shown or discussed
Mutual coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or logical of device or unit
Letter connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It should be appreciated that in this application, " at least one (item) " refers to one or more, and " multiple " refer to two or two
More than a."and/or" indicates may exist three kinds of relationships, for example, " A and/or B " for describing the incidence relation of affiliated partner
It can indicate: only exist A, only exist B and exist simultaneously tri- kinds of situations of A and B, wherein A, B can be odd number or plural number.Word
Symbol "/" typicallys represent the relationship that forward-backward correlation object is a kind of "or"." at least one of following (a) " or its similar expression, refers to
Any combination in these, any combination including individual event (a) or complex item (a).At least one of for example, in a, b or c
(a) can indicate: a, b, c, " a and b ", " a and c ", " b and c ", or " a and b and c ", and wherein a, b, c can be individually, can also
To be multiple.
The above, above embodiments are only to illustrate the technical solution of the application, rather than its limitations；Although referring to before
Embodiment is stated the application is described in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope of each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of chip power consumption of internal memory measurement method, which is characterized in that the described method includes:
In the wafer probing stage, default memory activity, the memory self detection method are generated by running memory self detection method
Including test cell sequence, each of described test cell sequence test cell includes one group of memory activity, described default
Memory activity can simulate the activity of the memory under normal operation mode；
The corresponding power consumption of the default memory activity is measured to determine chip power consumption of internal memory.
2. the method according to claim 1, wherein the test cell generates in the following way:
Obtain the corresponding simulation waveform of memory activity under normal operation mode；
Memory active sequences are extracted from the simulation waveform, dynamic member of surviving within the memory activity in the memory active sequences
Group form characterization, the memory activity tuple include current time, the current time corresponding internal memory operation, memory behaviour
Make corresponding memory address and the corresponding word content of the memory address；
The test cell is generated according to the memory active sequences.
3. according to the method described in claim 2, it is characterized in that, generating the test cell according to the memory active sequences
Include:
The test cell is generated according to the quantity of all types of internal memory operations in the memory active sequences；Alternatively,
The test cell is generated according to the power consumption of the memory active sequences.
4. according to the method described in claim 3, it is characterized in that, described according to all types of memories in the memory active sequences
The quantity of operation generates the test cell
For any kind internal memory operation, determine that each memory in chip generates the average value of the type internal memory operation；
Using the ratio of the quantity of word in the average value and memory as the number of the type internal memory operation in the test cell；
The test cell is generated according to the number of all types of internal memory operations.
5. according to the method described in claim 3, it is characterized in that, described generate institute according to the power consumption of the memory active sequences
Stating test cell includes:
Obtain initial testing unit；
Determine the first power consumption that the initial testing unit application to memory generates；
According to the update of the comparison result of first power consumption the second power consumption corresponding with internal memory operation under normal operation mode
Initial testing unit, until the comparison result of first power consumption and second power consumption meets preset condition；
The initial testing unit for meeting preset condition is determined as the test cell.
6. according to method described in claim 2 to 5 any one, which is characterized in that the method also includes:
Memory active sequences described in cutting obtain multiple memory activity segments；
It is then described to include: according to the memory active sequences generation test cell
Corresponding test cell is generated according to each of the multiple memory activity segment memory activity segment.
7. according to method described in claim 2 to 5 any one, which is characterized in that the method also includes:
The test cell is encoded to obtain source unit and self-test parameter；The self-test parameter is for extending the source unit
Obtain multiple test cells.
8. a kind of chip power consumption of internal memory measuring device, which is characterized in that described device includes:
Generation module, it is described interior for generating default memory activity by running memory self detection method in the wafer probing stage
Depositing self detection method includes test cell sequence, and each of described test cell sequence test cell includes survival in one group
Dynamic, the default memory activity can simulate the activity of the memory under normal operation mode；
Measurement module, for measuring the corresponding power consumption of the default memory activity to determine chip power consumption of internal memory.
9. a kind of chip power consumption of internal memory measuring device, which is characterized in that the equipment includes processor and memory:
Said program code is transferred to the processor for storing program code by the memory；
The processor is used for according in the described in any item chips of instruction execution claim 1 to 7 in said program code
Deposit power consumption measurement method.
10. a kind of computer readable storage medium, which is characterized in that the computer readable storage medium is for storing program generation
Code, said program code require 1 to 7 described in any item chip power consumption of internal memory measurement methods for perform claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910194574.XA CN109933473B (en) | 2019-03-14 | 2019-03-14 | Method, device, equipment and medium for measuring power consumption of chip memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910194574.XA CN109933473B (en) | 2019-03-14 | 2019-03-14 | Method, device, equipment and medium for measuring power consumption of chip memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109933473A true CN109933473A (en) | 2019-06-25 |
| CN109933473B CN109933473B (en) | 2022-09-27 |
Family
ID=66987122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910194574.XA Active CN109933473B (en) | 2019-03-14 | 2019-03-14 | Method, device, equipment and medium for measuring power consumption of chip memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109933473B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347487A (en) * | 2019-07-05 | 2019-10-18 | 中国人民大学 | A kind of energy consumption characters method and system of the data-moving of data base-oriented application |
| CN114627955A (en) * | 2022-05-06 | 2022-06-14 | 长鑫存储技术有限公司 | Power consumption testing method, device, equipment and storage medium |
| CN114692544A (en) * | 2020-12-29 | 2022-07-01 | 上海寒武纪信息科技有限公司 | Method and device for reconnecting power-on and power-off pins of memory for chip design |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6367042B1 (en) * | 1998-12-11 | 2002-04-02 | Lsi Logic Corporation | Testing methodology for embedded memories using built-in self repair and identification circuitry |
| US20130227367A1 (en) * | 2012-01-17 | 2013-08-29 | Allen J. Czamara | Test IP-Based A.T.E. Instrument Architecture |
| CN106298569A (en) * | 2016-07-28 | 2017-01-04 | 深圳芯启航科技有限公司 | The volume production method of testing of a kind of image chip and device |
-
2019
- 2019-03-14 CN CN201910194574.XA patent/CN109933473B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6367042B1 (en) * | 1998-12-11 | 2002-04-02 | Lsi Logic Corporation | Testing methodology for embedded memories using built-in self repair and identification circuitry |
| US20130227367A1 (en) * | 2012-01-17 | 2013-08-29 | Allen J. Czamara | Test IP-Based A.T.E. Instrument Architecture |
| CN106298569A (en) * | 2016-07-28 | 2017-01-04 | 深圳芯启航科技有限公司 | The volume production method of testing of a kind of image chip and device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347487A (en) * | 2019-07-05 | 2019-10-18 | 中国人民大学 | A kind of energy consumption characters method and system of the data-moving of data base-oriented application |
| CN110347487B (en) * | 2019-07-05 | 2021-03-23 | 中国人民大学 | Database application-oriented energy consumption characterization method and system for data movement |
| CN114692544A (en) * | 2020-12-29 | 2022-07-01 | 上海寒武纪信息科技有限公司 | Method and device for reconnecting power-on and power-off pins of memory for chip design |
| CN114692544B (en) * | 2020-12-29 | 2024-06-25 | 上海寒武纪信息科技有限公司 | Memory power-on and power-off pin reconnection method and device for chip design |
| CN114627955A (en) * | 2022-05-06 | 2022-06-14 | 长鑫存储技术有限公司 | Power consumption testing method, device, equipment and storage medium |
| CN114627955B (en) * | 2022-05-06 | 2022-10-28 | 长鑫存储技术有限公司 | Power consumption testing method, device, equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109933473B (en) | 2022-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109933473A (en) | Chip power consumption of internal memory measurement method, device, equipment and medium | |
| CN104040499B (en) | Multi-core processor with the Built-In Self Test (BIST) based on inside voting | |
| CN108664690A (en) | Long-life electron device reliability lifetime estimation method under more stress based on depth belief network | |
| WO2005072287A2 (en) | Remote bist for high speed test and redundancy calculation | |
| CN109543720B (en) | Wafer map defect mode identification method based on countermeasure generation network | |
| CN109524055A (en) | Method and test macro based on SOC ATE positioning memory fail bit | |
| CN1551225A (en) | Built-in self test system and method | |
| US20210326227A1 (en) | Fast and scalable methodology for analog defect detectability analysis | |
| US7865795B2 (en) | Methods and apparatuses for generating a random sequence of commands for a semiconductor device | |
| US6721914B2 (en) | Diagnosis of combinational logic circuit failures | |
| US6012157A (en) | System for verifying the effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory using states indicating by fault severity information | |
| Huang et al. | Raisin: Redundancy analysis algorithm simulation | |
| Huang | Dynamic learning based scan chain diagnosis | |
| CN110472706A (en) | A kind of smart card personalization system and method based on wafer scale | |
| US9310431B2 (en) | Diagnosis framework to shorten yield learning cycles of advanced processes | |
| CN106571165B (en) | A kind of test method and device of DDR device read-write | |
| CN110879348B (en) | Test set reordering method and device for estimating test performance based on testable area | |
| Krištofík et al. | Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults | |
| Li | Testing ternary content addressable memories with comparison faults using march-like tests | |
| Lai et al. | GPGPU-based ATPG system: Myth or reality? | |
| US11361135B2 (en) | Guiding sample size choice in analog defect or fault simulation | |
| CN109325289A (en) | A method of estimation soft copy dependability parameter | |
| CN109323876A (en) | A method of estimation gamma type unit dependability parameter | |
| CN109325287A (en) | A method of estimation mechanical parts dependability parameter | |
| Zakaria et al. | Testing Static Single Cell Faults using static and dynamic data background |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |