CN109933457A - A kind of data-encoding scheme and its system reducing the SSD bit error rate - Google Patents
A kind of data-encoding scheme and its system reducing the SSD bit error rate Download PDFInfo
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Abstract
The present invention relates to a kind of data-encoding schemes and its system for reducing the SSD bit error rate；Wherein, the data-encoding scheme of the SSD bit error rate is reduced, comprising the following steps: S1 enters data into initial data；Data are segmented by S2 according to the rule of setting；S3 is previously inserted into control bit in each data segment according to adjustment rule；S4 is adjusted source data according to control bit；NAND is written in modulated data by S5.The present invention is for the voltage's distribiuting region for being easy error, by way of dynamic regulation data encoding, change NAND Cell in the distribution in different voltages section, reduces the Cell distribution for being easy the voltage range of error, and then the probability of corrupt data is reduced, it being capable of preferably meet demand.
Description
Technical field
The present invention relates to solid state hard disks to read design field, more specifically refers to a kind of number for reducing the SSD bit error rate
According to coding method and its system.
Background technique
SSD (solid state hard disk) has been widely used in various occasions, since it is in performance, power consumption, environmental suitability etc.
The outstanding index of aspect, just gradually replaces traditional hard disk.
Due to the physical characteristic of NAND, there are different failure scenes for the CELL unit of storing data: for example with wiping
The influence of the factors such as number/reading times/data retention over time is write, the state of CELL can generate overturning, and then lead to NAND
The corrupt data of interior storage.Typically, a certain range of mistake is handled by special ECC error correction algorithm inside SSD, still
With the accumulation of wrong data, it may be desirable to introduce the mode of specific variation to read data, this can greatly influence to read
Write performance；Further, with the increase of wrong data, above method can not guarantee correcting data error again, and then lead to user
Loss of data, therefore it is unable to satisfy demand.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, a kind of data encoding side for reducing the SSD bit error rate is provided
Method and its system.
To achieve the above object, the present invention is used in lower technical solution:
A kind of data-encoding scheme reducing the SSD bit error rate, comprising the following steps:
S1 enters data into initial data；
Data are segmented by S2 according to the rule of setting；
S3 is previously inserted into control bit in each data segment according to adjustment rule；
S4 is adjusted source data according to control bit；
NAND is written in modulated data by S5.
Its further technical solution are as follows: in the S1, the every two bit of the data represents the state of a cell, from
And it is mapped to the Cell voltage's distribiuting in a Physical Page.
Its further technical solution are as follows: in the S2, the rule set is with 4 bit, i.e., the value of 2 Cell will
Data are segmented.
Its further technical solution are as follows: in the S3, the adjustment rule, which represents the data bin data for 1, to be taken
Instead, 0 representative remains unchanged.
Its further technical solution are as follows: in the S4, the adjustment negates the data segment step-by-step that control bit is 1.
A kind of data encording system reducing the SSD bit error rate, comprising: input unit, segmenting unit are inserted into unit, adjustment
Unit and writing unit；
The input unit, for entering data into initial data；
The segmenting unit, for being segmented data according to the rule of setting；
The insertion unit, for being previously inserted into control bit in each data segment according to adjustment rule；
The adjustment unit, for being adjusted according to control bit to source data；
Said write unit, for NAND to be written in modulated data.
Its further technical solution are as follows: in the input unit, the every two bit of the data represents the shape of a cell
State, thus the Cell voltage's distribiuting being mapped in a Physical Page.
Its further technical solution are as follows: in the segmenting unit, the rule set is with 4 bit, i.e. 2 Cell
Value, data are segmented.
Its further technical solution are as follows: in the insertion unit, the adjustment rule represents the data bin data for 1 will
It is negated, 0 representative remains unchanged.
Its further technical solution are as follows: in the adjustment unit, the adjustment takes the data segment step-by-step that control bit is 1
Instead.
Compared with the prior art, the invention has the advantages that: for the voltage's distribiuting region of easy error, pass through dynamic
The mode of data encoding is adjusted, changes NANDCell in the distribution in different voltages section, reduces the voltage range for being easy error
Cell distribution, and then reduce the probability of corrupt data, being capable of preferably meet demand.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Fig. 1 is the physical composition schematic diagram of NAND；
Fig. 2 is voltage's distribiuting schematic diagram of the NAND under general scene in the prior art；
Fig. 3 is NAND distribution schematic diagram after voltage moves to right in the prior art；
Fig. 4 is a kind of flow chart for the data-encoding scheme for reducing the SSD bit error rate of the present invention；
Fig. 5 is a kind of application schematic diagram of data-encoding scheme for reducing the SSD bit error rate；
Fig. 6 is voltage's distribiuting schematic diagram adjusted；
After Fig. 7 is write-in NAND, voltage moves to right rear distribution schematic diagram；
Fig. 8 is a kind of block diagram for the data encording system for reducing the SSD bit error rate of the present invention.
10 input unit, 20 segmenting unit
30 insertion 40 adjustment units of unit
50 writing units
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention into
One step introduction and explanation, but not limited to this.
Such as Fig. 1 to specific embodiment shown in Fig. 8, wherein as shown in Figure 1, typical NAND composition is as follows: DIE, it can be only
The unit of vertical concurrent operations；Block, the unit that can independently wipe, next time after the data write-in of interior each physical location
It has to wipe entire Block before writing；Page, read-write cell, the Page in same physical block must be programmed in order: 0-
>1->2->3…。
Wherein, as shown in Figure 2 to Figure 3, NAND is in the voltage's distribiuting under each scene: by taking MLC (flash memory) as an example, each
CELL corresponds to four possible states: A/B/C/D, and wherein A is the state after the erasing of default, B/C/D, respectively Program
To some state；Under general scenario, the Cell quantity under some state is in normal distribution, and is spaced each other relatively more clear
It is clear；At the time of reading, by that can confirm shape locating for some Cell compared with Vref_A/Vref_B/Vref_C reference voltage
State, and then it can be seen that its storage value；When certain pages in some physical block are read out repeatedly, Read Disturb will lead to
(reading disturbance) effect, global voltage distribution can move to right, and the voltage's distribiuting of partial status will appear coincidence at this time, use default
When reference voltage is read, the state of Cell can not be correctly judged；Need to attempt to adjust the position of reference voltage at this time to Vref_
A '/Vref_B '/Vref_C ' attempts to read data；The cut-and-try process will lead to the reduction of reading performance, and if variation
It is excessive, then possibly suitable reference voltage can not be found, and then correct data can not be obtained.
In existing SSD product, the data storage of NAND is carried out by Cell difference situation, by taking MLC as an example, often
Corresponding two bit of a Cell, can be programmed for 0/1 respectively, and 00,01,10,11 four value can be indicated by combining, and this four
A value is associated with different voltage's distribiutings；The reading of data is that the reference voltage in different voltages distribution is compared to
Differentiate that data are 0 or 1；It, generally all can be by randomizing data, so that the cell in each voltage range after data write-in
Quantity is consistent；And in early stage, the interval between each voltage's distribiuting is very big, 0/1 can be easily discriminated, so data total energy
It properly reads；But in some scenarios, such as the data read repeatedly, the problem of due to Read Disturb,
The voltage's distribiuting in physical block is caused to move to right.Under this situation, the default voltage that NAND is read all cannot correctly read back positive exact figures
According to needing to attempt mobile Vref voltage to read data, greatly reduce reading performance；Further, when variation is larger,
So that data can not error correction, so as to cause loss of data.
As shown in Figures 4 to 7, the invention discloses a kind of data-encoding schemes for reducing the SSD bit error rate, including following step
It is rapid:
S1 enters data into initial data；
Data are segmented by S2 according to the rule of setting；
S3 is previously inserted into control bit in each data segment according to adjustment rule；
S4 is adjusted source data according to control bit；
NAND is written in modulated data by S5.
Wherein, in the S1, the every two bit of the data represents the state of a cell, to be mapped to one
Cell voltage's distribiuting in Physical Page.
Wherein, in the S2, data is with 4 bit, i.e., the value of 2 Cell are divided by the rule set
Section.
Wherein, in the S3, the adjustment rule, which represents the data bin data for 1, to be negated, and 0 represents holding not
Become.
Wherein, in the S4, the adjustment negates the data segment step-by-step that control bit is 1.
Wherein, by above-mentioned method, the Cell distribution for the B:01 state for being easy error is reduced, it is original by reducing
01 value in data, after NAND is written, the Cell distribution of B state greatly reduces；After variation occurs, it is easy error
The lap of B state and C-state substantially reduces, and thereby reduces the probability that data can not entangle.
Correspondingly, when reading the data, according to fixed data segment and control bit information, corresponding data is carried out and are turned over
Turn, then ECC (error checking and correction) is decoded again.
Wherein, it in traditional SSD, can be all randomized before NAND is written in data, so that four electricity of similar MLC
Pressure is distributed as impartial.After being analyzed by the failure model to NAND, it can be seen that some regions are easier electricity occur
The coincidence of distribution is pressed, and these regions are exactly the source of wrong data；And the present invention is by changing the data being written on NAND
The voltage's distribiuting of value, i.e., changeable Cell thereby reduces error in data so that overlapping region is smaller after variation
Rate.
As shown in figure 8, the invention discloses a kind of data encording systems for reducing the SSD bit error rate, comprising: input unit
10, segmenting unit 20 is inserted into unit 30, adjustment unit 40 and writing unit 50；
The input unit 10, for entering data into initial data；
The segmenting unit 20, for being segmented data according to the rule of setting；
The insertion unit 30, for being previously inserted into control bit in each data segment according to adjustment rule；
The adjustment unit 40, for being adjusted according to control bit to source data；
Said write unit 50, for NAND to be written in modulated data.
Wherein, in the input unit 10, the every two bit of the data represents the state of a cell, to map
To the Cell voltage's distribiuting in a Physical Page.
Wherein, in the segmenting unit 20, the rule set is with 4 bit, i.e., the value of 2 Cell, by data into
Row segmentation.
Wherein, in the insertion unit 30, the adjustment rule, which represents the data bin data for 1, to be negated, and 0 represents
It remains unchanged.
Wherein, in the adjustment unit 40, the adjustment negates the data segment step-by-step that control bit is 1.
0/1 distribution of the present invention each data segment of dynamic regulation by way of being inserted into control bit in initial data, changes
Become NAND Cell in the distribution in different voltages section；At the time of reading according to the label of control bit, corresponding Data flipping control is carried out
System restores source data；By changing NAND Cell in the distribution in the neighboring voltage section for being easy error, reduce because of voltage
The bit error rate caused by deviating.
In conclusion voltage's distribiuting region of the present invention for easy error, by way of dynamic regulation data encoding,
Change NAND Cell in the distribution in different voltages section, reduces the Cell distribution for being easy the voltage range of error, and then reduce
The probability of corrupt data, being capable of preferably meet demand.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but not
It represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the invention
Protection.Protection scope of the present invention is subject to claims.
Claims (10)
1. a kind of data-encoding scheme for reducing the SSD bit error rate, which comprises the following steps:
S1 enters data into initial data；
Data are segmented by S2 according to the rule of setting；
S3 is previously inserted into control bit in each data segment according to adjustment rule；
S4 is adjusted source data according to control bit；
NAND is written in modulated data by S5.
2. a kind of data-encoding scheme for reducing the SSD bit error rate according to claim 1, which is characterized in that in the S1,
The every two bit of the data represents the state of a cell, thus the Cell voltage's distribiuting being mapped in a Physical Page.
3. a kind of data-encoding scheme for reducing the SSD bit error rate according to claim 1, which is characterized in that in the S2,
Data is with 4 bit, i.e., the value of 2 Cell are segmented by the rule set.
4. a kind of data-encoding scheme for reducing the SSD bit error rate according to claim 1, which is characterized in that in the S3,
The adjustment rule, which represents the data bin data for 1, to be negated, and 0 representative remains unchanged.
5. a kind of data-encoding scheme for reducing the SSD bit error rate according to claim 1, which is characterized in that in the S4,
The adjustment negates the data segment step-by-step that control bit is 1.
6. a kind of data encording system for reducing the SSD bit error rate characterized by comprising input unit, segmenting unit, insertion
Unit, adjustment unit and writing unit；
The input unit, for entering data into initial data；
The segmenting unit, for being segmented data according to the rule of setting；
The insertion unit, for being previously inserted into control bit in each data segment according to adjustment rule；
The adjustment unit, for being adjusted according to control bit to source data；
Said write unit, for NAND to be written in modulated data.
7. a kind of data encording system for reducing the SSD bit error rate according to claim 6, which is characterized in that the input
In unit, the every two bit of the data represents the state of a cell, thus the Cell voltage being mapped in a Physical Page
Distribution.
8. a kind of data encording system for reducing the SSD bit error rate according to claim 6, which is characterized in that the segmentation
In unit, data is with 4 bit, i.e., the value of 2 Cell are segmented by the rule set.
9. a kind of data encording system for reducing the SSD bit error rate according to claim 6, which is characterized in that the insertion
In unit, the adjustment rule, which represents the data bin data for 1, to be negated, and 0 representative remains unchanged.
10. a kind of data encording system for reducing the SSD bit error rate according to claim 6, which is characterized in that the adjustment
In unit, the adjustment negates the data segment step-by-step that control bit is 1.
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Application publication date: 20190625 |