CN109933453B

CN109933453B - Error correction method and semiconductor device using the same

Info

Publication number: CN109933453B
Application number: CN201811044479.3A
Authority: CN
Inventors: 金昌铉; 金溶美
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2017-12-15
Filing date: 2018-09-07
Publication date: 2023-03-10
Anticipated expiration: 2038-09-07
Also published as: CN109933453A; US20190188075A1; TW201937369A; TWI798250B; US10698764B2; KR20190072144A; KR102420641B1

Abstract

The present application relates to an error correction method and a semiconductor device using the same. The semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from the first output data and the first output parity code generated during the first read operation. Further, the read data generation circuit generates second read data from the second output data and the second output parity code generated during the second read operation. The syndrome generating circuit generates a syndrome signal from the first read data and the second read data. The syndrome generating circuit generates the syndrome signal such that a column vector of a first half matrix corresponding to the first read data is symmetrical to a column vector of a second half matrix corresponding to the second read data.

Description

Error correction method and semiconductor device using the same

Cross Reference to Related Applications

This application claims priority from korean patent application No. 10-2017-0173258 filed on 12, 15, 2017, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Embodiments of the present disclosure generally relate to a semiconductor device capable of correcting or recovering data errors.

Background

The semiconductor may be designed according to various schemes to input or output multi-bit data in each clock cycle to increase the operating speed of the semiconductor device. However, as the speed of inputting or outputting data to or from the semiconductor device increases, the probability of data errors also increases. Accordingly, there is a need for improved methods and/or devices to enhance data processing to and from memory devices.

In data processing of semiconductor devices, in order to improve reliability of data transmission, data is generally transmitted with error codes for detecting and correcting errors in the data. Accordingly, typical error codes may include an Error Detection Code (EDC) for detecting errors and an Error Correction Code (ECC) for correcting errors.

Disclosure of Invention

According to one embodiment, a semiconductor device may include a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity generated during a first read operation. Further, the read data generation circuit generates second read data from second output data and a second output parity generated during a second read operation. The syndrome generation circuit generates a syndrome signal based on at least the first read data and the second read data.

According to another embodiment, a method of correcting a data error is provided. The method includes a first step, a second step, and a third step. The first step is performed to generate first read data from first output data and a first output parity provided during a first read operation. The second step is performed to generate a first pre-verify sub-group including error information on the first read data, and the first pre-verify sub-group is stored. Performing the third step to generate second read data from second output data and a second output parity provided during a second read operation, generating a second pre-syndrome group including error information on the second read data, and generating a syndrome signal by performing a logical operation on the first pre-syndrome group and the second pre-syndrome group.

According to another embodiment, a semiconductor device includes a storage region and a syndrome generating circuit. The storage area stores input data and a parity code during a write operation. During a first read operation, the storage area outputs a first input data of the input data as a first output data and outputs the parity as an output parity. The storage area outputs a second input data of the input data as a second output data and outputs the parity as the output parity during a second read operation. The syndrome generation circuit generates the parity code from the input data during the write operation. The syndrome generation circuit generates a parity code by performing a logical operation on the first output data and the output parity code during the first read operation. The syndrome generating circuit generates a syndrome signal by performing a logical operation on the parity code generated during the first read operation, the second output data, and the output parity code during the second read operation. The syndrome generating circuit generates the syndrome signal such that a column vector of a first half matrix corresponding to the first output data is symmetrical to a column vector of a second half matrix corresponding to the second output data.

Other applications of the present disclosure will become apparent to those skilled in the art from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, for practicing the inventive concepts.

Drawings

The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the several views, and wherein:

fig. 1 is a block diagram showing a configuration of a semiconductor device according to one example of the present disclosure;

fig. 2 is a block diagram showing a configuration of a read data generation circuit included in the semiconductor device of fig. 1;

fig. 3 is a circuit diagram showing a configuration of a control circuit included in the read data generation circuit of fig. 2;

fig. 4 is a block diagram showing a configuration of a syndrome generating circuit included in the semiconductor device of fig. 1;

fig. 5 is a circuit diagram showing a configuration of a pre-syndrome generating circuit included in the syndrome generating circuit of fig. 4;

fig. 6 is a circuit diagram showing a configuration of a logic circuit included in the syndrome generating circuit of fig. 4;

FIG. 7 is a block diagram illustrating another example of the syndrome generating circuit shown in FIG. 4;

fig. 8 is a circuit diagram showing a configuration of a logic circuit included in the syndrome generating circuit of fig. 7;

FIG. 9 illustrates a matrix used in one embodiment of the present disclosure;

fig. 10 is a timing diagram illustrating the operation of a semiconductor device according to one embodiment of the present disclosure;

FIG. 11 is a flow diagram illustrating an error correction method according to one embodiment of the present disclosure;

fig. 12 is a block diagram showing a configuration of a semiconductor device according to another embodiment of the present disclosure;

fig. 13 is a block diagram showing a configuration of a column signal generating circuit included in the semiconductor device of fig. 12;

fig. 14 is a circuit diagram showing a configuration of a write pulse generating circuit included in the column signal generating circuit of fig. 13;

fig. 15 is a circuit diagram showing a configuration of a read pulse generating circuit included in the column signal generating circuit of fig. 13;

fig. 16 is a circuit diagram showing a configuration of a control circuit included in the column signal generating circuit of fig. 13;

fig. 17 is a block diagram showing a configuration of a syndrome generating circuit included in the semiconductor device of fig. 12;

fig. 18 is a circuit diagram showing a configuration of a pre-syndrome generating circuit included in the syndrome generating circuit of fig. 17;

fig. 19 is a circuit diagram showing a configuration of a logic circuit included in the syndrome generating circuit of fig. 17;

fig. 20 is a block diagram showing a configuration of an electronic system employing at least one of the semiconductor devices described with reference to fig. 1 to 19.

Fig. 21 is a block diagram showing a configuration of another electronic system employing at least one of the semiconductor devices described with reference to fig. 1 to 19.

Detailed Description

The present invention provides a semiconductor device capable of symmetrically adjusting or controlling column vectors of a matrix, for performing two read operations during a read operation to generate a syndrome for data error correction, and reducing the size of a circuit for establishing the matrix.

In describing the present disclosure, when it is determined that detailed description of known related art may obscure the points of the present disclosure, detailed description thereof will be omitted.

Although terms such as first and second may be used to describe various components, these components are not limited by these terms and these terms are only used to distinguish one component from another component.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention.

It is also noted that, in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment unless specifically stated otherwise, as will be apparent to those skilled in the relevant art(s).

Referring now to fig. 1, an exemplary configuration of a semiconductor device is provided. The semiconductor device includes a parity code generation circuit 10, a storage area 20, a read data generation circuit 30, a syndrome generation circuit 40, and a data correction circuit 50.

In a write operation, the parity generation circuit 10 may generate a parity PI <1:4> that includes error information about the input data DIN <1:6>. During a write operation, the parity generation circuit 10 may generate the parity PI <1:4> including error information on the input data DIN <1:6> in response to the write signal WT input to the parity generation circuit 10. During a write operation, parity generation circuit 10 may perform a logical operation on data bits contained in input data DIN <1:6> to generate parity PI <1:4>. For example, the parity generation circuit 10 may generate the parity P <1:4> using a Hamming code (Hamming code). The Hamming code may be implemented in a matrix for correcting errors in data (e.g., input data DIN <1:6 >). In one embodiment, parity code generation circuit 10 may include an Error Correction Code (ECC) circuit (not shown) that uses a Hamming code to generate parity code P <1:4>.

During a write operation, the storage area 20 may store input data DIN <1:6> and parity PI <1:4>. In the storage area 20, in response to a write signal WT input to the storage area 20 during a write operation, input data DIN <1:6> and a parity PI <1:4> may be stored. Storage area 20 may store some of input data DIN <1:6> (e.g., input data DIN <1:3 >) to a first storage area of storage area 20 in response to write signal WT. Storage area 20 may store other data (e.g., input data DIN <4:6 >) in input data DIN <1:6> to a second storage area of storage area 20 in response to write signal WT. In the storage area 20, the first storage area and the second storage area may be two different storage spaces. In the storage area 20, the first storage area and the second storage area may be two independent storage spaces. The first storage area and the second storage area may be set as a storage space in which the input data DIN <1:6> is stored. The storage area 20 may store some parity codes (e.g., the parity code PI <1:2 >) of the parity code PI <1:4> into a third storage area in the storage area 20 in response to the write signal WT. The storage area 20 may store the remaining parity code of the parity code PI <1:4> (e.g., < parity code PI <3:4 >) to a fourth storage area of the storage area 20 in response to the write signal WT. The third storage area and the fourth storage area may be established as two different storage spaces in the storage area 20. The third storage area and the fourth storage area may be set as a storage space in which the parity PI <1:4> is stored.

In the read operation, the storage area 20 can output the input data DIN <1:3> stored in the first storage area as first output data DO1<1:3> during the first read operation. The memory area 20 may output the input data DIN <1:3> stored in the first memory area as first output data DO1<1:3> in response to the read signal RD. The storage area 20 may output the parity PI <1:2> stored in the third storage area as the first output parity PO1<1:2> during the first read operation. The storage area 20 may output the parity PI <1:2> stored in the third storage area as the first output parity PO1<1:2> in response to the read signal RD. The storage area 20 may output the input data DIN <4:6> stored in the second storage area as second output data DO2<1:3> during the second read operation. The storage area 20 may output the input data DIN <4:6> stored in the second storage area as second output data DO2<1:3> in response to the read signal RD. The storage area 20 may output the parity code PI <3:4> stored in the fourth storage area as a second output parity code PO2<1:2> during the second read operation. The storage area 20 may output the parity PI <3:4> stored in the fourth storage area as a second output parity PO2<1:2> in response to the read signal RD.

During the first read operation, the read data generation circuit 30 may generate the first read data RD1<1:5> based on at least the first output data DO1<1:3> and the first output parity PO1<1:2> output from the storage area 20. Read data generation circuit 30 may combine first output data DO1<1:3> with first output parity PO1<1:2> to generate (or synthesize) first read data RD1<1:5>. During the second read operation, read data generation circuit 30 may generate second read data RD2<1:5> based on at least second output data DO2<1:3> and second output parity PO2<1:2> output from memory area 20. During the second read operation, read data generation circuit 30 may output second read data RD2<1:5> by combining second output data DO2<1:3> output from memory area 20 and second output parity PO2<1:2>. The read data generation circuit 30 may generate a selection signal SEL that can be enabled during a predetermined period in response to the read signal RD. The read data generation circuit 30 may generate a reset signal RST that can be enabled during a predetermined period of time in response to the read signal RD and the select signal SEL.

Syndrome generation circuit 40 may generate syndrome signal SYN <1:4> based on at least first read data RD1<1:5> and second read data RD2<1:5>. Syndrome signal SYN <1:4> may be obtained from a matrix (shown in fig. 9) implemented by first read data RD1<1:5> and second read data RD2<1:5>. Syndrome generating circuit 40 may generate syndrome signal SYN <1:4> by performing a logical operation on data bits contained in first read data RD1<1:5> and second read data RD2<1:5> in response to selection signal SEL and reset signal RST. For example, the syndrome signal SYN <1:4> may be generated by an Error Correction Code (ECC) circuit using a Hamming code. In one embodiment, syndrome generation circuit 40 may include an Error Correction Code (ECC) circuit using a Hamming code for generating an error correction code. The hamming code can be implemented by a matrix (see fig. 9) for correcting errors of the data. The syndrome signal SYN <1:4> may include position information on an error bit among data bits in the first output data DO1<1:3> and the second output data DO2<1:3>. A method of generating the matrix shown in fig. 9 will be described in detail later with reference to the accompanying drawings.

During the second read operation, the data correction circuit 50 may correct the error data of the first output data DO1<1:3> and the second output data DO2<1:3> using the syndrome signal SYN <1:4>. The data correction circuit 50 may combine the first output data DO1<1:3> and the second output data DO2<1:3> that are corrected during the second read operation, and may output the combined data as correction data DC <1:6>.

Referring to fig. 2, the read data generation circuit 30 may include a control circuit 31 and a data synthesis circuit 32.

The control circuit 31 may generate the selection signal SEL in response to the read signal RD and the column delay signal (YID of fig. 3). The selection signal SEL may be enabled in response to the read signal RD and may be disabled in response to the column delay signal YID. The control circuit 31 may generate the reset signal RST in response to the read signal RD and the select signal SEL. For example, the reset signal RST may be enabled in response to the read signal RD and disabled in response to the select signal SEL. The control circuit 31 may generate a column signal YI including a first pulse and a second pulse generated in response to the read signal RD.

The data synthesis circuit 32 may generate the first read data RD1<1:5> based on at least the first output data DO1<1:3> and the first output parity PO1<1:2> in response to the column signal YI, and may generate the second read data RD2<1:5> based on at least the second output data DO2<1:3> and the second output parity PO2<1:2> in response to the column signal YI. The data synthesis circuit 32 may combine (or synthesize) the first output data DO1<1:3> and the first output parity PO1<1:2> in response to the first pulse of the column signal YI to output the first read data RD1<1:5>. The data synthesis circuit 32 may generate the first read data RD1<1:5> by combining the first output data DO1<1:3> and the first output parity PO1<1:2> in response to the first pulse of the column signal YI. The data synthesis circuit 32 may generate the second read data RD2<1:5> from the second output data DO2<1:3> and the second output parity PO2<1:2> in response to the second pulse of the column signal YI. The data synthesis circuit 32 may generate the second read data RD2<1:5> by combining (or synthesizing) the second output data DO2<1:3> and the second output parity PO2<1:2> in response to the second pulse of the column signal YI.

Referring to fig. 3, the control circuit 31 may include a selection signal generation circuit 310, a reset signal generation circuit 320, and a column signal generation circuit 330.

The selection signal generation circuit 310 may generate the selection signal SEL in response to the read signal RD and the column delay signal YID. The selection signal generation circuit 310 may generate the selection signal SEL having a logic "low" level at a time when the read signal RD having a logic "high" level is input to the selection signal generation circuit 310. The selection signal generation circuit 310 may generate the selection signal SEL having a logic "high" level at a time when the column delay signal YID having a logic "high" level is input to the selection signal generation circuit 310.

The reset signal generation circuit 320 may generate a reset signal RST in response to the selection signal SEL and the read signal RD. The reset signal generation circuit 320 may generate the reset signal RST having a logic "high" level when the selection signal SEL has a logic "low" level and the read signal RD has a logic "high" level.

The column signal generating circuit 330 may include a pulse signal generating circuit 331, a column signal output circuit 332, and a delay circuit 333.

The pulse signal generating circuit 331 may generate the first and second pulse signals YIP1 and YIP2 that are sequentially enabled in response to the read signal RD, and when the read signal RD having a logic "high" level is input to the pulse signal generating circuit 331, the pulse signal generating circuit 331 may output the first pulse signal YIP1 having a logic "high" level during a predetermined period and the second pulse signal YIP2 having a logic "high" level during a predetermined period after the first pulse signal YIP1 is output.

The column signal output circuit 332 may output a column signal YI including first and second pulses generated in response to the first and second pulse signals YIP1 and YIP2. The column signal output circuit 332 may perform a logical OR (OR) operation on the first and second pulse signals YIP1 and YIP2 to generate the column signal YI. When one of the first and second pulse signals YIP1 and YIP2 has a logic "high" level, the column signal output circuit 332 may generate the column signal YI having a logic "high" level. The column signal output circuit 332 may output the first pulse signal YIP1 as a first pulse of the column signal YI. The column signal output circuit 332 may output the second pulse signal YIP2 as a second pulse of the column signal YI.

The delay circuit 333 may delay the column signal YI to generate a column delay signal YID. How long the delay circuit 333 delays the column signal YI, i.e., the delay time, may be determined differently according to various embodiments.

As described above, when the read signal RD has a logic "high" level, the control circuit 31 may generate the selection signal SEL having a logic "low" level, and when the column delay signal YID has a logic "high" level, the control circuit 31 may generate the selection signal SEL having a logic "high" level. When the selection signal SEL has a logic "low" level and the read signal RD has a logic "high" level, the control circuit 31 may generate the reset signal RST having a logic "high" level. When the read signal RD has a logic "high" level, the control circuit 31 may output the column signal YI including the first pulse and the second pulse sequentially generated.

Referring to fig. 4, the syndrome generating circuit 40 may include a pre-syndrome generating circuit 41 and a logic circuit 42.

Pre-syndrome generation circuit 41 may perform a logical operation on data bits contained in first read data RD1<1:5> generated during the first read operation to generate first to fourth pre-syndromes PS <1:4>. Pre-syndrome generation circuit 41 may perform a logical operation on data bits contained in second read data RD2<1:5> generated during the second read operation to generate first to fourth pre-syndromes PS <1:4>. First through fourth pre-syndromes PS <1:4> may include error information about first read data RD1<1:5> and second read data RD2<1:5>. The first through fourth pre-syndromes PS <1:4> generated during the first read operation may be established as the first pre-syndrome group. The first through fourth pre-syndromes PS <1:4> generated during the second read operation may be determined as the second pre-syndrome group. The first through fourth pre-syndromes PS <1:4> may be considered as column vectors of a matrix. By way of example and not limitation, a matrix may be provided by pre-syndrome generating circuit 41 to generate syndromes for use in semiconductor devices. The matrix will be described later with reference to fig. 9.

Logic circuit 42 may store first to fourth pre-syndromes PS <1:4> generated during the first read operation as syndrome signals SYN <1:4>, i.e., first to fourth syndromes SYN <1:4>, in response to selection signal SEL. When the selection signal SEL has a logic "low" level, the logic circuit 42 may allocate the first through fourth pre-syndromes PS <1:4> generated during the first read operation as the first through fourth syndromes SYN <1:4>. To generate the first through fourth syndromes SYN <1:4>, the logic circuit 42 may change an array order of the first through fourth pre-syndromes PS <1:4> generated during the second read operation in response to the selection signal SEL and perform a logic operation on the first through fourth pre-syndromes PS <1:4> rearranged according to the changed array order and the first through fourth syndromes SYN <1:4> generated during the first read operation. Logic circuit 42 may generate the initialized first through fourth syndromes SYN <1:4> in response to reset signal RST.

The configuration and operation of the pre-syndrome generating circuit 41 will be described below with reference to fig. 5.

The pre-syndrome generating circuit 41 may be implemented in a form including a plurality of exclusive OR (exclusive OR) gates EXOR41, EXOR42, EXOR43, EXOR44, EXOR45, and a plurality of inverters IV41, IV 42.

As follows, the first through fourth pre-syndromes PS <1:4> may be generated during the first read operation according to one example.

The pre-syndrome generation circuit 41 may generate the first pre-syndrome PS <1> by performing a logical exclusive-or operation on the first bit data RD1<1>, the third bit data RD1<3>, and the fourth bit data RD1<4> contained in the first read data RD1<1:5> via the exclusive-or gates EXOR41, EXOR 42.

The pre-syndrome generation circuit 41 may generate the second pre-syndrome PS <2> by performing a logical exclusive-or operation on the second bit data RD1<2>, the third bit data RD1<3>, and the fifth bit data RD1<5> contained in the first read data RD1<1:5> via the exclusive-or gates EXOR43, EXOR 44.

The pre-syndrome generating circuit 41 may generate the third pre-syndrome PS <3> by performing a logical exclusive or operation on the fourth bit-data RD1<4> and the fifth bit-data RD1<5> contained in the first read data RD1<1:5> via the exclusive or gate EXOR 45.

Pre-syndrome generating circuit 41 may generate fourth pre-syndrome PS <4> by buffering fifth bit data RD1<5> of first read data RD1<1:5> via an even number of inverters (e.g., inverters IV41 and IV 42).

As follows, the first through fourth pre-syndromes PS <1:4> may be generated during the second read operation.

The pre-syndrome generating circuit 41 may generate the first pre-syndrome PS <1> by performing a logical exclusive or operation on the first bit-data RD2<1>, the third bit-data RD2<3>, and the fourth bit-data RD2<4> contained in the second read data RD2<1:5> via the exclusive or gates EXOR41, EXOR 42.

To generate second pre-syndrome PS <2>, pre-syndrome generating circuit 41 may perform a logical exclusive or operation on second bit data RD2<2>, third bit data RD2<3>, and fifth bit data RD2<5> contained in second read data RD2<1:5> via exclusive or gates EXOR43, EXOR 44.

Pre-syndrome generating circuit 41 may generate third pre-syndrome PS <3> by performing a logical exclusive or operation on fourth bit-data RD2<4> and fifth bit-data RD2<5> contained in second read data RD2<1:5> via exclusive or gate EXO 45.

Pre-syndrome generating circuit 41 may generate fourth pre-syndrome PS <4> by buffering fifth bit data RD2<5> of second read data RD2<1:5> through an even number of inverters (e.g., inverters IV41 and IV 42).

The configuration and operation of the logic circuit 42 will be described below with reference to fig. 6.

Logic circuitry 42 may include a select syndrome generating circuit 421 and a syndrome storing circuit 422.

In response to the selection signal SEL, the selection syndrome generation circuit 421 may output the first to fourth pre-syndromes PS <1:4> as the first to fourth selection syndromes SS <1:4>, respectively, or may change the array order of the first to fourth pre-syndromes PS <1:4> to output the first to fourth pre-syndromes PS <1:4> rearranged in the changed array order as the first to fourth selection syndromes SS <1:4>, respectively.

More specifically, when the selection signal SEL has a logic "low" level, the selection syndrome generation circuit 421 may output the first pre-syndrome PS <1> as a first selection syndrome SS <1>, output the second pre-syndrome PS <2> as a second selection syndrome SS <2>, output the third pre-syndrome PS <3> as a third selection syndrome SS <3>, and output the fourth pre-syndrome PS <4> as a fourth selection syndrome SS <4>. In addition, when the selection signal SEL has a logic "high" level, the selection syndrome generation circuit 421 may output the first pre-syndrome PS <1> as the fourth selection syndrome SS <4>, output the second pre-syndrome PS <2> as the third selection syndrome SS <3>, output the third pre-syndrome PS <3> as the second selection syndrome SS <2>, and output the fourth pre-syndrome PS <4> as the first selection syndrome SS <1>.

Syndrome storage circuit 422 may generate initialized first to fourth syndromes SYN <1:4> in response to reset signal RST. When the reset signal RST is enabled to have a logic "high" level, the first through fourth syndromes SYN <1:4> may be initialized to have a logic "low" level. Syndrome storage circuit 422 may store the first through fourth selected syndromes SS <1:4> generated during the first read operation as first through fourth syndromes SYN <1:4> in response to the column delay signal YID. Syndrome storage circuit 422 may generate first to fourth syndromes SYN <1:4> by performing logical operations on first to fourth syndromes SYN <1:4> stored during a first read operation in response to column delay signal YID and first to fourth selected syndromes SS <1:4> generated during a second read operation.

More specifically, when the column delay signal YID is generated to have a logic "high" level during the first read operation, syndrome storage circuit 422 may store a first selected syndrome SS <1> as a first syndrome SYN <1>, a second selected syndrome SS <2> as a second syndrome SYN <2>, a third selected syndrome SS <3> as a third syndrome SYN <3>, and a fourth selected syndrome SS <4> as a fourth syndrome SYN <4>.

When the column delay signal YID is generated to have a logic "high" level during the second read operation, the syndrome storage circuit 422 may generate the first syndrome SYN <1> by performing a logical exclusive-or operation on the first selected syndrome SS <1> and the first syndrome SYN <1> stored during the first read operation, generate the second syndrome SYN <2> by performing a logical exclusive-or operation on the second selected syndrome SS <2> and the second syndrome SYN <2> stored during the first read operation, generate the third syndrome SYN <3> by performing a logical exclusive-or operation on the third selected syndrome SS <3> and the third syndrome SYN <3> stored during the first read operation, and generate the fourth syndrome SYN <4> by performing a logical exclusive-or operation on the fourth selected syndrome SS <4> and the fourth syndrome SYN <4> stored during the first read operation.

Referring to fig. 7, another example of syndrome generating circuit 40a is provided. Syndrome generating circuit 40a may include a pre-syndrome generating circuit 43 and a logic circuit 44.

Pre-syndrome generation circuit 43 may perform a logical operation on data bits contained in first read data RD1<1:5> generated during the first read operation to generate first to fourth pre-syndromes PS <1:4>. Pre-syndrome generation circuit 43 may perform a logical operation on data bits contained in second read data RD2<1:5> generated during the second read operation to generate first to fourth pre-syndromes PS <1:4>. The first through fourth pre-syndromes PS <1:4> generated during the first read operation may be determined as the first pre-syndrome group. The first through fourth pre-syndromes PS <1:4> generated during the second read operation may be determined as the second pre-syndrome group. Pre-syndrome generating circuit 43 may be implemented using the same circuit as pre-syndrome generating circuit 41 shown in fig. 5. Therefore, a detailed description of the pre-syndrome generating circuit 43 will be omitted hereinafter.

Logic circuitry 44 may store first through fourth pre-syndromes PS <1:4> generated during the first read operation as first through fourth syndromes SYN <1:4>. To generate first through fourth syndromes SYN <1:4>, logic circuit 44 may change the array order of first through fourth syndromes SYN <1:4> stored during the first read operation and perform a logic operation on first through fourth syndromes SYN <1:4> rearranged according to the changed array order and first through fourth pre-syndromes PS <1:4> generated during the second read operation. Logic circuit 44 may generate initialized first through fourth syndromes SYN <1:4> in response to reset signal RST.

More specifically, referring to fig. 8, when the column delay signal YID is output to have a logic "high" level during the first read operation, the logic circuit 44 may store the first pre-syndrome PS <1> as the first syndrome SYN <1>, the second pre-syndrome PS <2> as the second syndrome SYN <2>, the third pre-syndrome PS <3> as the third syndrome SYN <3>, and the fourth pre-syndrome PS <4> as the fourth syndrome SYN <4>.

When the column delay signal YID is generated to have a logic "high" level during the second read operation, the logic circuit 44 may generate the first syndrome SYN <1> by performing a logical exclusive-or operation on the first pre-syndrome and the fourth syndrome SYN <4> -PS < -1 > stored during the first read operation, generate the second syndrome SYN <2> by performing a logical exclusive-or operation on the second pre-syndrome PS <2> and the third syndrome SYN <3> stored during the first read operation, generate the third syndrome SYN <3> by performing a logical exclusive-or operation on the third pre-syndrome PS <3> and the second syndrome SYN <2> stored during the first read operation, and generate the fourth syndrome SYN <4> by performing a logical exclusive-or operation on the fourth pre-syndrome PS <4> and the first syndrome SYN <1> stored during the first read operation.

A method of reducing the area of the circuit for extracting the matrix by two read operations performed in the semiconductor device according to one embodiment will be described below with reference to fig. 9. The matrix shown in fig. 9 may be established by the pre-syndrome generating circuit 41.

First, the full matrix shown in fig. 9 is a matrix for generating first to fourth syndromes SYN <1:4> for correcting errors of first to sixth data D1 to D6 of six bits. In the full matrix shown in fig. 9, the first to third data D1 to D3 may be regarded as first output data DO1<1:3> and the fourth to sixth data D4 to D6 may be regarded as second output data DO2<1:3>. Further, the parity-check codes P1 and P2 in the full matrix may correspond to the first and second bits of the first output parity-check code PO1<1:2>, respectively. Further, the parity-check codes P3 and P4 in the full matrix may correspond to the first bit and the second bit, respectively, of the second output parity-check code PO2<1:2>.

The row vector for generating the first syndrome SYN <1> may be determined to perform a logical exclusive or operation on the first parity P1, the first data D1, the second data D2, and the sixth data D6.

The row vector for generating the second syndrome SYN <2> may be determined to perform a logical exclusive or operation on the second parity P2, the first data D1, the third data D3, the fifth data D5, and the sixth data D6.

The row vector for generating the third syndrome SYN <3> may be determined to perform a logical exclusive or operation on the third parity P3, the second data D2, the third data D3, the fourth data D4, and the sixth data D6.

The row vector for generating the fourth syndrome SYN <4> may be determined to perform a logical exclusive or operation on the fourth parity P4, the third data D3, the fourth data D4, and the fifth data D5.

The logic level combination of the first through fourth syndromes SYN <1:4> may include information on whether erroneous bits are included in the first through sixth data D1 through D6 and the first through fourth parity codes P1 through P4. By way of example and not limitation, when the first through fourth syndromes SYN <1:4> are generated to have a logic level combination "1,1,0,0" corresponding to a logic level combination of the fifth column vector of the full matrix, it may be determined that the first data D1 is erroneous data.

Next, a first half matrix and a second half matrix for generating first to fourth syndromes SYN <1:4> for correcting errors of the six-bit data D1 to D6 in two read operations are also shown in fig. 9.

The row vector for generating the first syndrome SYN <1> may include a first parity P1, first data D1, second data D2, and sixth data D6. The row vectors used to generate the first syndrome SYN <1> may include a first row vector of the first half matrix associated with a first read operation and a first row vector of the second half matrix associated with a second read operation. In this case, the first row vector of the second half-matrix may be the same as the fourth row vector of the first half-matrix.

The row vector for generating the second syndrome SYN <2> may include the second parity P2, the first data D1, the third data D3, the fifth data D5, and the sixth data D6. The row vectors used to generate the second syndrome SYN <2> may include a second row vector of the first half matrix associated with the first read operation and a second row vector of the second half matrix associated with the second read operation. In this case, the second row vector of the second half-matrix may be the same as the third row vector of the first half-matrix.

The row vector for generating the third syndrome SYN <3> may include a third parity P3, second data D2, third data D3, fourth data D4, and sixth data D6. The row vectors used to generate the third syndrome SYN <3> may include a third row vector of the first half matrix associated with the first read operation and a third row vector of the second half matrix associated with the second read operation. In this case, the third row vector of the second half-matrix may be the same as the second row vector of the first half-matrix.

The row vector for generating the fourth syndrome SYN <4> may include a fourth parity P4, third data D3, fourth data D4, and fifth data D5. The row vectors used to generate fourth syndrome SYN <4> may include a fourth row vector of the first half matrix associated with the first read operation and a fourth row vector of the second half matrix associated with the second read operation. In this case, the fourth row vectors of the second half-matrix may be the same as the first row vectors of the first half-matrix.

According to the description, the column vectors of the first half-matrix may have a symmetrical configuration with respect to the column vectors of the second half-matrix. This may result in a reduction in the circuit area for setting the matrix used to generate the syndrome used in data error correction during two read operations.

A read operation of the semiconductor device will be described below with reference to fig. 10 in conjunction with an example in which two read operations (i.e., a first operation and a second operation) are used to generate a syndrome to correct error data.

The read operation according to one embodiment is as follows.

When the read signal RD is input to the storage area 20 at the time point "T1", the storage area 20 may output some of the input data DIN <1:6> stored therein (e.g., the input data DIN <1:3 >) as the first output data DO1<1:3> and may output some of the parity codes PI <1:4> (e.g., the parity codes PI <1:2 >) stored therein as the first output parity codes PO1<1:2> in response to the read signal RD.

The selection signal generation circuit 310 of the control circuit 31 may generate the selection signal SEL enabled to have a logic "low" level in response to the read signal RD.

At the second time T2, the reset signal generation circuit 320 of the control circuit 31 may generate the reset signal RST having a logic "high" level in response to the read signal RD and the selection signal SEL input at the first time T1.

Logic circuit 42 may generate first through fourth syndromes SYN <1:4> initialized to have a logic "low" level in response to reset signal RST having a logic "high" level.

At the third time T3, the column signal generation circuit 330 of the control circuit 31 may generate the first pulse of the column signal YI in response to the read signal RD input at the first time T1.

The data synthesis circuit 32 may generate the first read data RD1<1:5> from the first output data DO1<1:3> and the first output parity PO1<1:2> in response to the first pulse of the column signal YI.

At a fourth time T4, pre-syndrome generating circuit 41 may perform a logical operation on the data bits contained in first read data RD1<1:5> to generate first to fourth pre-syndromes PS <1:4>. The first through fourth pre-syndromes PS <1:4> generated during the first read operation may be determined as the first pre-syndrome group.

At the fifth time T5, the column signal generation circuit 330 of the control circuit 31 may delay the pulse of the column signal YI generated at the third time T3 to generate the first pulse of the column delay signal YID.

The logic circuit 42 may store the first to fourth pre-syndromes PS <1:4> as the first to fourth syndromes SYN <1:4> in response to the first pulse of the selection signal SEL and the column delay signal YID having a logic "low" level.

At the sixth time T6, the selection signal generation circuit 310 of the control circuit 31 may generate the selection signal SEL that is disabled to have a logic "high" level in response to the first pulse of the column delay signal YID generated at the fifth time T5.

At the seventh time T7, the column signal generation circuit 330 of the control circuit 31 may generate the second pulse of the column signal YI in response to the read signal RD input at the time point "T1".

The data synthesis circuit 32 may generate the second read data RD2<1:5> from the second output data DO2<1:3> and the second output parity PO2<1:2> in response to the second pulse of the column signal YI.

At eighth time T8, pre-syndrome generating circuit 41 may perform a logical operation on data bits included in second read data RD2<1:5> to generate first to fourth pre-syndromes PS <1:4>. The first through fourth pre-syndromes PS <1:4> generated during the second read operation may be determined as the second pre-syndrome group.

The logic circuit 42 may change the array order of the first to fourth pre-syndromes PS <1:4> in response to the selection signal SEL having a logic "high" level.

At the ninth time T9, the column signal generation circuit 330 of the control circuit 31 may delay the second pulse of the column signal YI generated at the seventh time T7 to generate the second pulse of the column delay signal YID.

In response to the second pulse of the column delay signal YID, the logic circuit 42 may generate the first to fourth syndromes SYN <1:4> by performing a logical operation on the first to fourth pre-syndromes PS <1:4> rearranged in the changed array order at the eighth time T8 and the first to fourth syndromes SYN <1:4> stored at the fifth time T5.

As described above, the semiconductor device may adjust the two half matrices generating the syndrome for correcting the data error during the two read operations such that the column vectors of the first half matrix of the two half matrices are symmetrical with respect to the column vectors of the second half matrix of the two half matrices. As a result, the area allocated for the circuit configured to establish the matrix can be reduced.

An error correction method according to one embodiment will be described below with reference to fig. 11.

The error correction method may include a first step S1, a second step S2, a third step S3, and a fourth step S4.

The first step S1 of the error correction method may comprise a step S11 of inputting the read signal RD and a step S12 of performing a first read operation.

Step S11 may be a step in which the read signal RD is input to generate the first pulse of the column signal YI.

Step S12 may be a step of generating first read data RD1<1:5> from first output data DO1<1:3> and first output parity PO1<1:2> output from the memory region 20 by a first pulse of the column signal YI during the first read operation.

The second step S2 may comprise a step S21 of generating a first pre-calibration subset and a step S22 of storing the first pre-calibration subset.

Step S21 may be a step of generating first through fourth pre-syndromes PS <1:4> including failure information about first read data RD1<1:5>. The first through fourth pre-syndromes PS <1:4> generated during the first read operation may be determined as the first pre-syndrome group.

Step S22 may be a step of storing the first to fourth pre-syndromes PS <1:4> as first to fourth syndromes SYN <1:4>.

The third step S3 may include a step S31 of performing a second read operation, a step S32 of generating a second pre-syndrome group, and a step S33 of generating a syndrome.

Step S31 may be a step of generating second read data RD2<1:5> from second output data DO2<1:3> output from the memory region 20 and a second output parity PO2<1:2> by a second pulse of the column signal YI during the second read operation.

Step S32 may include: the method includes generating first to fourth pre-syndromes PS <1:4> including failure information on second read data RD2<1:5>, and adjusting an array order of the first to fourth pre-syndromes PS <1:4> such that column vectors in a matrix are symmetrical to each other. The first through fourth pre-syndromes PS <1:4> generated during the second read operation may be determined as the second pre-syndrome group.

Step S33 may include performing a logical operation on the first to fourth syndromes SYN <1:4> stored at step S22 and the first to fourth pre-syndromes PS <1:4> rearranged according to the adjusted array order to generate the first to fourth syndromes SYN <1:4>.

The fourth step S4 may include a step S41 of generating correction data and a step S42 of outputting the correction data.

Step S41 may be a step of correcting error data of first output data DO1<1:3> and second output data DO2<1:3> based on first to fourth syndromes SYN <1:4> and synthesizing the corrected first output data DO1<1:3> and the corrected second output data DO2<1:3> to generate corrected data DC <1:6>.

Step S42 may be a step of outputting correction data DC <1:6>.

As described above, the error correction method according to one embodiment may adjust the array order of the column vectors in the matrix determined during the second read operation to generate the syndrome for correcting the data error, such that the column vectors in the matrix determined during the first read operation are symmetrical to the column vectors in the matrix determined during the second read operation. As a result, the area required for the circuit for building the matrix can be reduced.

As shown in fig. 12, the semiconductor device may include a storage region 60, a column signal generation circuit 70, a syndrome generation circuit 80, and a data correction circuit 90.

During a write operation, the storage area 60 may store input data DIN <1:6> and parity PI <1:4>. During a write operation, the storage area 60 may store input data DIN <1:6> and a parity PI <1:4> in response to a write signal WT input to the storage area 60. Storage area 60 may store input data DIN <1:3> of input data DIN <1:6> into a first storage area of storage area 60 in response to write signal WT. Storage area 60 may store input data DIN <4:6> of input data DIN <1:6> into a second storage area of storage area 60 in response to write signal WT. Input data DIN <1:3> may be determined as first input data, and input data DIN <4:6> may be determined as second input data. The first storage area and the second storage area may be arranged as two different storage spaces in the storage area 60. The first memory region and the second memory region may be regarded as memory regions storing data. The storage area 60 may store the parity code PI <1:2> of the parity codes PI <1:4> into the third storage area of the storage area 60 in response to the write signal WT. The storage area 60 may store the parity code PI <3:4> of the parity codes PI <1:4> into a fourth storage area of the storage area 60 in response to the write signal WT. The third storage area and the fourth storage area may occupy two different and independent storage spaces in the storage area 60. The third storage area and the fourth storage area may be determined as storage areas storing parity codes.

The storage area 60 may output the first input data DIN <1:3> stored in the first storage area as first output data DO1<1:3> during the first read operation. The storage area 60 may output the first input data DIN <1:3> stored in the first storage area as first output data DO1<1:3> in response to the read signal RD. The storage area 60 may output the second input data DIN <4:6> stored in the second storage area as second output data DO2<1:3> during the second read operation. The memory area 60 may output the second input data DIN <4:6> stored in the second memory area as second output data DO2<1:3> in response to the read signal RD. The storage area 60 may output the parity PI <1:4> stored therein as the output parity PO <1:4> in response to the read signal RD. The two read operations, i.e., the first read operation and the second read operation, may be sequentially performed by a single control signal (i.e., the read signal RD input to the memory region 60) that is activated or enabled only once.

The column signal generating circuit 70 may generate a column signal YI including a first pulse and a second pulse, which are sequentially generated in response to the write signal WT or the read signal RD. The column signal generation circuit 70 may generate a selection signal SEL that is enabled in response to the write signal WT or the read signal RD. The column signal generation circuit 70 may generate a reset signal RST that is enabled in response to the write signal WT or the read signal RD.

During a write operation, syndrome generation circuit 80 may generate a parity code PI <1:4> from input data DIN <1:6>. The syndrome generation circuit 80 may generate syndrome signals including first to fourth syndromes SYN <1:4> from the first output data DO1<1:3>, the second output data DO2<1:3>, and the output parity PO <1:4> during a read operation. The syndrome generating circuit 80 may generate the syndrome signal SYN <1:4> from the first output data DO1<1:3>, the second output data DO2<1:3>, and the output parity PO <1:4> using the first half matrix and the second half matrix shown in fig. 9. In response to the selection signal SEL and the reset signal RST, the syndrome generation circuit 80 may generate the syndrome signal SYN <1:4> by performing a logical operation on bit data of the first output data DO1<1:3>, bit data of the second output data DO2<1:3>, and bit data of the output parity code PO <1:4>. The syndrome signal SYN <1:4> may be generated by an Error Correction Code (ECC) circuit using a hamming code. The hamming code may be implemented by a matrix for correcting data errors. The syndrome signal SYN <1:4> may include position information about error bits in the first output data DO1<1:3> and the second output data DO2<1:3>.

During the second read operation, the data correction circuit 90 may correct errors of the first output data DO1<1:3> and the second output data DO2<1:3> using the syndrome signal SYN <1:4>. The data correction circuit 90 may combine the previously corrected first output data DO1<1:3> and the second output data DO2<1:3> to output the resultant data as corrected data DC <1:6>.

Referring to fig. 13, the column signal generating circuit 70 may include a write pulse generating circuit 71, a read pulse generating circuit 72, and a control circuit 73.

The write pulse generating circuit 71 may generate a write column signal WT _ YI including a first pulse and a second pulse, which are sequentially generated in response to the write signal WT. The write pulse generating circuit 71 may generate a write select signal WT _ SEL and a write reset signal WT _ RST that are enabled in response to the write signal WT. The write pulse generation circuit 71 may generate a write select signal WT _ SEL in response to the write signal WT and a write column delay signal (WT _ YID of fig. 14). The write pulse generating circuit 71 may generate a write select signal WT _ SEL that is enabled in response to the write signal WT and disabled in response to the write column delay signal WT _ YID. The write pulse generating circuit 71 may generate a write reset signal WT _ RST in response to the write signal WT and the write select signal WT _ SEL.

The read pulse generating circuit 72 may generate a read column signal RD _ YI including a first pulse and a second pulse sequentially generated in response to the read signal RD. The read pulse generating circuit 72 may generate a read select signal RD _ SEL and a read reset signal RD _ RST that are enabled in response to the read signal RD. The read pulse generating circuit 72 may generate a read select signal RD _ SEL in response to the read signal RD and the read column delay signal (RD _ YID of fig. 15). The read pulse generation circuit 72 may generate a read select signal RD _ SEL that is enabled in response to the read signal RD and disabled in response to the read column delay signal RD _ YID. The read pulse generating circuit 72 may generate a read reset signal RD _ RST in response to a read signal RD and a read select signal RD _ SEL.

The control circuit 73 may output one of the write column signal WT _ YI and the read column signal RD _ Y1 as the column signal YI in response to the write signal WT and the read signal RD. The control circuit 73 may output a write select signal WT _ SEL or a read select signal RD _ SEL as a select signal SEL in response to the write signal WT and the read signal RD. The control circuit 73 may generate the enabled reset signal RST in response to the write reset signal WT _ RST or the read reset signal RD _ RST. When the write reset signal WT _ RST or the read reset signal RD _ RST is enabled, the control circuit 73 may generate an enabled reset signal RST.

Referring to fig. 14, the write pulse generating circuit 71 may include a write select signal generating circuit 710, a write reset signal generating circuit 720, and a write column signal generating circuit 730.

The write select signal generation circuit 710 may generate a write select signal WT _ SEL in response to the write signal WT and the write column delay signal WT _ YID. The write select signal generation circuit 710 may generate a write select signal WT _ SEL having a logic "low" level at a time when the write signal WT having a logic "high" level is input to the write select signal generation circuit 710. The write select signal generation circuit 710 may generate the write select signal WT _ SEL having a logic "high" level at a time when the write column delay signal WT _ YID having a logic "high" level is input to the write select signal generation circuit 710.

The write reset signal generation circuit 720 may generate a write reset signal WT _ RST in response to a write select signal WT _ SEL and a write signal WT. When the write select signal WT _ SEL has a logic "low" level and the write signal WT has a logic "high" level, the write reset signal generation circuit 720 may generate the write reset signal WT _ RST having a logic "high" level.

The write column signal generation circuit 730 may include a first pulse signal generation circuit 731, a write column signal output circuit 732, and a first delay circuit 733.

The first pulse signal generating circuit 731 may generate a first write pulse signal WT _ YIP1 and a second write pulse signal WT _ YIP2 that are sequentially enabled in response to the write signal WT. When the write signal WT having a logic "high" level is input to the first pulse signal generating circuit 731, the first pulse signal generating circuit 731 may generate a first write pulse signal WT _ YIP1 that is enabled to have a logic "high" level during a predetermined period and a second write pulse signal WT _ YIP2 that is enabled to have a logic "high" level during another predetermined period after the first write pulse signal WT _ YIP1 is generated.

The write column signal output circuit 732 may generate a write column signal WT _ YI including a first pulse and a second pulse generated in response to the first write pulse signal WT _ YIP1 and the second write pulse signal WT _ YIP2. The write column signal output circuit 732 may perform a logical or operation on the first and second write pulse signals WT _ YIP1 and WT _ YIP2 to generate the write column signal WT _ YI. When the first write pulse signal WT _ YIP1 or the second write pulse signal WT _ YIP2 is generated to have a logic "high" level, the write column signal output circuit 732 may generate the write column signal WT _ YI having a logic "high" level. The write column signal output circuit 732 may output the first write pulse signal WT _ YIP1 as a first pulse of the write column signal WT _ YI. The write column signal output circuit 732 may output the second write pulse signal WT _ YIP2 as a second pulse of the write column signal WT _ YI.

The first delay circuit 733 may delay the write column signal WT _ YI to generate the write column delay signal WT _ YID. The delay time for which the first delay circuit 733 delays the write column signal WT _ YI may be variously determined according to an exemplary semiconductor device.

As described above, when the write signal WT has a logic "high" level, the write pulse generating circuit 71 may generate the write select signal WT _ SEL having a logic "low" level, and the write pulse generating circuit 71 may generate the write select signal WT _ SEL having a logic "high" level at a time when the write column delay signal WT _ YID has a logic "high" level. When the write select signal WT _ SEL has a logic "low" level and the write signal WT has a logic "high" level, the write pulse generation circuit 71 may generate the write reset signal WT _ RST having a logic "high" level. The write pulse generating circuit 71 may generate a write column signal WT _ YI including a first pulse and a second pulse sequentially generated when the write signal WT has a logic "high" level.

Referring to fig. 15, the read pulse generating circuit 72 may include a read select signal generating circuit 740, a read reset signal generating circuit 750, and a read column signal generating circuit 760.

The read select signal generation circuit 740 may generate a read select signal RD _ SEL in response to the read signal RD and the read column delay signal RD _ YID. The read select signal generation circuit 740 may generate the read select signal RD _ SEL having a logic "low" level at a time when the read signal RD having a logic "high" level is input to the read select signal generation circuit 740. The read select signal generation circuit 740 may generate the read select signal RD _ SEL having a logic "high" level at a time when the read column delay signal RD _ YID having a logic "high" level is input to the read select signal generation circuit 740.

The read reset signal generation circuit 750 may generate a read reset signal RD _ RST in response to a read select signal RD _ SEL and a read signal RD. When the read select signal RD _ SEL has a logic "low" level and the read signal RD has a logic "high" level, the read reset signal generation circuit 750 may generate the read reset signal RD _ RST having a logic "high" level.

The read column signal generation circuit 760 may include a second pulse signal generation circuit 761, a read column signal output circuit 762, and a second delay circuit 763.

The second pulse signal generation circuit 761 may generate the first read pulse signal RD _ YIP1 and the second read pulse signal RD _ YIP2 that are sequentially enabled in response to the read signal RD. When the read signal RD having a logic "high" level is input to the second pulse signal generation circuit 761, the second pulse signal generation circuit 761 may generate a first read pulse signal RD _ YIP1 and a second read pulse signal RD _ YIP2, the first read pulse signal RD _ YIP1 being enabled to have a logic "high" level during a predetermined period, the second read pulse signal RD _ YIP2 being enabled to have a logic "high" level during another predetermined period after the first read pulse signal RD _ YIP1 is generated.

The read column signal output circuit 762 may generate a read column signal RD _ YI including a first pulse and a second pulse generated in response to a first read pulse signal RD _ YIP1 and a second read pulse signal RD _ YIP2. The read column signal output circuit 762 may perform a logical or operation on the first read pulse signal RD _ YIP1 and the second read pulse signal RD _ YIP2 to generate the read column signal RD _ YI. The read column signal output circuit 762 may generate the read column signal RD _ YI having a logic "high" level when the first read pulse signal RD _ YIP1 or the second read pulse signal RD _ YIP2 is at the logic "high" level. The read column signal output circuit 762 may output the first read pulse signal RD _ YIP1 as a first pulse of the read column signal RD _ YI. The read column signal output circuit 762 may output the second read pulse signal RD _ YIP2 as a second pulse of the read column signal RD _ YI.

The second delay circuit 763 may delay the read column signal RD _ YI to generate a read column delay signal RD _ YID. The delay time for which the second delay circuit 763 delays the read column signal RD _ YI may be differently determined according to an exemplary semiconductor device.

As described above, when the read signal RD has a logic "high" level, the read pulse generating circuit 72 may generate the read select signal RD _ SEL having a logic "low" level, and the read pulse generating circuit 72 may generate the read select signal RD _ SEL having a logic "high" level at a time when the read column delay signal RD _ YID has a logic "high" level. When the read select signal RD _ SEL has a logic "low" level and the read signal RD has a logic "high" level, the read pulse generating circuit 72 may generate the read reset signal RD _ RST having a logic "high" level. The read pulse generating circuit 72 may generate a read column signal RD _ YI including a first pulse and a second pulse sequentially generated when the read signal RD has a logic "high" level.

Referring to fig. 16, the control circuit 73 may include a control signal generation circuit 770, a selection transmission circuit 780, and a reset signal generation circuit 790.

The control signal generation circuit 770 may generate the control signal CON that is enabled in response to the write signal WT and the read signal RD. The control signal generation circuit 770 may generate the control signal CON having a logic "high" level at a time when the write signal WT having a logic "high" level is input to the control signal generation circuit 770. The control signal generation circuit 770 may generate the control signal CON having a logic "low" level at a time when the read signal RD having a logic "high" level is input to the control signal generation circuit 770.

The selection transmission circuit 780 may output the write column signal WT _ YI or the read column signal RD _ YI as the column signal YI in response to the control signal CON. When the control signal CON has a logic "high" level, the selection transmission circuit 780 may output the write column signal WT _ YI as the column signal YI. When the control signal CON has a logic "low" level, the selective transmission circuit 780 may output the read column signal RD _ YI as the column signal YI. The selection transmission circuit 780 may output the write selection signal WT _ SEL or the read selection signal RD _ SEL as the selection signal SEL in response to the control signal CON. When the control signal CON has a logic "high" level, the selection transmission circuit 780 may output the write selection signal WT _ SEL as the selection signal SEL. When the control signal CON has a logic "low" level, the selection transmission circuit 780 may output the read selection signal RD _ SEL as the selection signal SEL.

The reset signal generation circuit 790 may generate an enabled reset signal RST in response to the write reset signal WT _ RST or the read reset signal RD _ RST. When any one of the write reset signal WT _ RST or the read reset signal RD _ RST has a logic "high" level, the reset signal generation circuit 790 may generate the reset signal RST enabled to have a logic "high" level.

Referring to fig. 17, the syndrome generating circuit 80 may include a pre-syndrome generating circuit 81 and a logic circuit 82.

The pre-syndrome generation circuit 81 may perform a logical operation on data bits contained in the first output data DO1<1:3> generated during the first read operation to generate the first to fourth pre-syndromes PS <1:4>. Pre-syndrome generating circuit 81 may perform a logical operation on data bits in second output data DO2<1:3> generated during the second read operation to generate first to fourth pre-syndromes PS <1:4>. The first through fourth pre-syndromes PS <1:4> generated during the first read operation may be determined as the first pre-syndrome group. The first through fourth pre-syndromes PS <1:4> generated during the second read operation may be determined as the second pre-syndrome group. The first through fourth pre-syndromes PS <1:4> may be considered column vectors of a matrix. Pre-syndrome generation circuitry 81 may provide a matrix to generate syndromes for use in the exemplary semiconductor device. Since the matrix used in the present embodiment is the same as the matrix shown in fig. 9, a detailed description of the matrix used in the present embodiment will be omitted hereinafter.

The logic circuit 82 may store the first through fourth pre-syndromes PS <1:4> generated during the first read operation as the first through fourth syndromes SYN <1:4> in response to the selection signal SEL. When the selection signal SEL has a logic "low" level, the logic circuit 82 may store the first through fourth pre-syndromes PS <1:4> generated during the first read operation as the first through fourth syndromes SYN <1:4>. The logic circuit 82 may change the array order of the first through fourth pre-syndromes PS <1:4> generated during the second read operation in response to the selection signal SEL. When the selection signal SEL has a logic "high" level, the logic circuit 82 may change the array order of the first to fourth pre-syndromes PS <1:4> generated during the second read operation. To generate the first through fourth syndromes SYN <1:4>, the logic circuit 82 may perform a logic operation on the parity codes PI <1:4> (including the first through fourth parity codes PI <1:4 >) generated during the first read operation and the output parity codes PO <1:4> (including the first through fourth output parity codes PO <1:4 >) generated during the second read operation. Logic circuit 82 may generate first through fourth syndromes SYN <1:4> that are initialized in response to reset signal RST.

The configuration and operation of the pre-syndrome generating circuit 81 will be described below with reference to fig. 18.

The pre-syndrome generating circuit 81 may be implemented with the formation of a plurality of exclusive or gates EXOR1, EXOR82, EXOR83 and a plurality of inverters IV81, VI 82.

As follows, during the first read operation, the first to fourth pre-syndromes PS <1:4> may be generated.

The pre-syndrome generating circuit 81 may perform a logical exclusive or operation on the first bit data DO1<1> and the second bit data DO1<2> in the first output data DO1<1:3> through the exclusive or gate EXOR81 to generate the first pre-syndrome PS <1>.

The pre-syndrome generating circuit 81 may perform a logical exclusive or operation on the first bit data DO1<1> and the third bit data DO1<3> in the first output data DO1<1:3> through the exclusive or gate EXOR82 to generate the second pre-syndrome PS <2>.

The pre-syndrome generating circuit 81 may perform a logical exclusive-or operation on the second bit data DO1<2> and the third bit data DO1<3> in the first output data DO1<1:3> through the exclusive-or gate EXOR83 to generate the third pre-syndrome PS <3>.

The pre-syndrome generating circuit 81 can generate the fourth pre-syndrome PS <4> by buffering the third bit data DO1<3> contained in the first output data DO1<1:3> using the inverters IV81, IV 82.

As follows, during the second read operation, the first through fourth pre-syndromes PS <1:4> may be generated.

The pre-syndrome generating circuit 81 may generate the first pre-syndrome PS <1> by performing a logical exclusive-or operation on the first bit data DO2<1> and the second bit data DO2<2> in the second output data DO2<1:3> via the exclusive-or gate EXOR 81.

The pre-syndrome generating circuit 81 may generate the second pre-syndrome PS <2> by performing a logical exclusive or operation on the first bit data DO2<1> and the third bit data DO2<3> in the second output data DO2<1:3> via the exclusive or gate EXOR 82.

The pre-syndrome generating circuit 81 may perform a logical exclusive-or operation on the second bit data DO2<2> and the third bit data DO2<3> in the second output data DO2<1:3> using the exclusive-or gate EXOR83 to generate the third pre-syndrome PS <3>.

The pre-syndrome generating circuit 81 can generate the pre-syndrome PS <4> by buffering the third bit data DO2<3> contained in the second output data DO2<1:3> using the inverters IV81, IV 82.

The configuration and operation of the logic circuit 82 will be described below with reference to fig. 19.

The logic circuit 82 may include a selection syndrome generating circuit 821, a parity code storing circuit 822, and a syndrome output circuit 823.

The selection syndrome generation circuit 821 may output the first to fourth pre-syndromes PS <1:4> as the first to fourth selection syndromes SS <1:4> or change the array order of the first to fourth pre-syndromes PS <1:4> respectively in response to the selection signal SEL, thereby outputting the first to fourth pre-syndromes PS <1:4> rearranged in the changed array order as the first to fourth selection syndromes SS <1:4> respectively.

More specifically, when the selection signal SEL is generated to have a logic "low" level, the selection syndrome generation circuit 821 may output the first pre-syndrome PS <1> as the first selection syndrome SS <1>, output the second pre-syndrome PS <2> as the second selection syndrome SS <2>, output the third pre-syndrome PS <3> as the third selection syndrome SS <3>, and output the fourth pre-syndrome PS <4> as the fourth selection syndrome SS <4>. Further, when the selection signal SEL is generated to have a logic "high" level, the selection syndrome generation circuit 821 may output the first pre-syndrome PS <1> as the fourth selection syndrome SS <4>, output the second pre-syndrome PS <2> as the third selection syndrome SS >3>, output the third pre-syndrome PS <3> as the second selection syndrome SS <2>, and output the fourth pre-syndrome PS <4> as the first selection syndrome SS <1>.

The parity storage circuit 822 may generate the first to fourth parity PI <1:4> initialized in response to the reset signal RST. When the reset signal RST has a logic "high" level, the parity storage circuit 822 may generate the first to fourth parity codes PI <1:4 initialized to have a logic "low" level. In response to the column signal YI, the parity storage circuit 822 may store the first through fourth selection syndromes SS <1:4> generated during the first read operation as the first through fourth parities PI <1:4>. The parity storage circuit 822 may generate the first to fourth parity codes PI <1:4 by performing a logical operation on the first to fourth parity codes PI <1:4> stored during the first read operation in response to the column signal YI and the first to fourth selection syndromes SS <1:4> generated during the second read operation.

More specifically, when the column signal YI has a logic "high" level during the first read operation, the parity storage circuit 822 may allocate the first selection syndrome SS <1> as the first parity PI <1>, allocate the second selection syndrome SS <2> as the second parity PI <2>, allocate the third selection syndrome SS <3> as the third parity PI <3>, and allocate the fourth selection syndrome SS <4> as the fourth parity PI <4>.

When the column signal YI is generated to have a logic "high" level during the second read operation, the parity storage circuit 822 may generate the first parity PI <1> by performing a logical exclusive-or operation on the first selector SS <1> and the first parity PI <1> stored during the first read operation, may generate the second parity PI <2> by performing a logical exclusive-or operation on the second selector SS <2> and the second parity PI <2> stored during the first read operation, may generate the third parity PI <3> by performing a logical exclusive-or operation on the third selector SS <3> and the third parity PI <3> stored during the first read operation, and may generate the fourth parity PI <4> by performing a logical exclusive-or operation on the fourth selector SS <4> and the fourth parity PI <4> stored during the first read operation.

Syndrome output circuitry 823 may perform a logical exclusive-or operation on first parity PI <1> and first output parity PO <1> to generate a first syndrome SYN <1>. Syndrome output circuitry 823 may generate a second syndrome SYN <2> by performing a logical XOR operation on the second parity PI <2> and the second output parity PO <2>. Syndrome output circuitry 823 may perform a logical exclusive-or operation on third parity PI <3> and third output parity PO <3> to generate a third syndrome SYN <3>. In addition, syndrome output circuit 823 may generate a fourth syndrome SYN <4> by performing a logical XOR operation on the fourth parity PI <4> and the fourth output parity PO <4>.

As described above, the semiconductor device according to another embodiment may adjust the two half matrices generating the syndrome for corrected data errors during two read operations such that a column vector of a first half matrix of the two half matrices is symmetrical to a column vector of a second half matrix of the two half matrices. As a result, the area allocated to the circuit for establishing the matrix can be reduced.

At least one of the semiconductor devices described with reference to fig. 1 to 19 may be applied to an electronic device including a memory system, a graphic system, a computing system, a mobile system, or the like. By way of example, and not limitation, as shown in FIG. 20, electronic system 1000 may include data storage circuitry 1001, memory controller 1002, buffer memory 1003, and input/output (I/O) interface 1004.

The data storage circuit 1001 may store data transferred from the memory controller 1002 in response to a control signal output from the memory controller 1002, or read and supply the stored data to the memory controller 1002. The data storage circuit 1001 may include at least one of the semiconductor devices shown in fig. 1 and 12. Meanwhile, the data storage circuit 1001 may include a nonvolatile memory that retains its stored data even when its power supply is interrupted or is not supplied. The nonvolatile memory may be a flash memory such as a NOR type flash memory or a NAND type flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a spin transfer torque random access memory (STRAM), a Magnetic Random Access Memory (MRAM), or the like.

The memory controller 1002 may receive a command transmitted from an external device (e.g., a host) through the I/O interface 1004 and decode the command output from the host to control an operation of inputting data into the data storage circuit 1001 or the buffer memory 1003 or an operation of outputting data stored in the data storage circuit 1001 or the buffer memory 1003. Although fig. 20 shows the memory controller 1002 as having a single unit or module, the memory controller 1002 may include a plurality of controllers, for example, one controller for controlling the data storage circuit 1001 including a nonvolatile memory and another controller for controlling the buffer memory 1003 including a volatile memory.

The buffer memory 1003 may temporarily store data processed by the memory controller 1002. That is, the buffer memory 1003 may temporarily store data output from the data storage circuit 1001 or data transferred into the data storage circuit 1001. The buffer memory 1003 may store data transferred from the memory controller 1002 according to the control signal. The buffer memory 1003 may read the stored data and output it to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a Dynamic Random Access Memory (DRAM), a mobile DRAM, or a Static Random Access Memory (SRAM), and the like.

The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., a host). Accordingly, the memory controller 1002 may receive control signals and/or data from an external device (i.e., a host) through the I/O interface 1004 and output data generated by the memory controller 1002 to the external device (i.e., the host) through the I/O interface 1004. That is, electronic system 1000 may communicate with a host through I/O interfaces 1004. The I/O interface 1004 may be designed or used for any of a variety of interface protocols, such as Universal Serial Bus (USB) drives, multiMediaCards (MMCs), peripheral component interconnect express (PCI-E), serial Attached SCSI (SAS), serial AT attachment (SATA), parallel AT attachment (PATA), small Computer System Interface (SCSI), enhanced Small Device Interface (ESDI), and Integrated Drive Electronics (IDE).

Electronic system 1000 may be used as a secondary storage device or an external storage device for a host. Electronic system 1000 may include a Solid State Disk (SSD), a USB drive, a Secure Digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (MicroSD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded multimedia card (EMMC), or a Compact Flash (CF) card, among others.

Referring to fig. 21, an electronic system 2000 according to another embodiment may include a host 2001, a memory controller 2002, and a data storage circuit 2003.

The host 2001 may output a request signal and data to the memory controller 2002 to access or exit the data storage circuit 2003. The memory controller 2002 may provide data, a data strobe signal, a command, an address, and a clock signal to the data storage circuit 2003 in response to the request signal, and the data storage circuit 2003 may perform a write operation or a read operation in response to the command. The host 2001 may transfer data to the memory controller 2002 to write data in the data storage circuit 2003. In addition, the host 2001 may receive data from the data storage circuit 2003 through the memory controller 2002. Host 2001 may include circuitry configured to correct errors of the data using an Error Correction Code (ECC) scheme.

The memory controller 2002 may serve as an interface for connecting the host 2001 to the data storage circuit 2003 for communication between the host 2001 and the data storage circuit 2003. The memory controller 2002 may receive request signals and data from the host 2001 and generate and provide data, data strobe signals, command, address and clock signals to the data storage circuitry 2003 in order to control the operation of the data storage circuitry 2003. In addition, the memory controller 2002 may supply data output from the data storage circuit 2003 to the host 2001.

The data storage circuit 2003 may include a plurality of memories. The data storage circuit 2003 may receive data, data strobe signals, commands, addresses, and clock signals from the memory controller 2002 to perform a write operation or a read operation. Each memory included in the data storage circuit 2003 may include a circuit that corrects an error of data using an Error Correction Code (ECC) scheme. The data storage circuit 2003 may include at least one of the semiconductor devices shown in fig. 1 to 12.

In some embodiments, the electronic system 2000 may be implemented to selectively operate one of the ECC circuits included in the host 2001 and the data storage circuit 2003. Alternatively, the electronic system 2000 may be implemented to operate all ECC circuits included in the host 2001 and the data storage circuit 2003 simultaneously. By way of example, and not limitation, host 2001 and memory controller 2002 may be implemented in a single chip. The memory controller 2002 and the data storage circuit 2003 may be implemented in a single chip.

While the disclosure has been described in connection with what is presently considered to be the most practical and preferred example, it is to be understood that the invention is not to be limited to the disclosed example, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.

Claims

1. A semiconductor device, comprising:

a read data generation circuit configured to: generating first read data from the first output data and the first output parity generated during the first read operation, and generating second read data from the second output data and the second output parity generated during the second read operation;

a syndrome generation circuit configured to generate a syndrome signal based on at least the first read data and the second read data,

wherein the syndrome generating circuit generates the syndrome signal such that a column vector of a first half matrix corresponding to the first read data is symmetrical to a column vector of a second half matrix corresponding to the second read data, an

Wherein the first read operation and the second read operation are sequentially performed by a single read signal having a single activation pulse input to the semiconductor device.

2. The semiconductor device as set forth in claim 1,

wherein the first output data is output from a first storage area,

the second output data is output from a second storage area,

the first output parity is output from a third storage area, an

The second output parity is output from a fourth storage area, an

Wherein the first storage area, the second storage area, the third storage area, and the fourth storage area are independent.

3. The semiconductor device according to claim 1, wherein the read data generation circuit comprises:

a control circuit configured to generate a column signal including a first pulse and a second pulse sequentially generated in response to a read signal; and configured to generate a select signal that is enabled in response to the read signal and disabled in response to a column delay signal;

a data synthesis circuit configured to generate the first read data from the first output data and the first output parity in response to the first pulse of the column signal, and configured to generate the second read data from the second output data and the second output parity in response to the second pulse of the column signal.

4. The semiconductor device of claim 3, wherein the control circuit comprises:

a select signal generation circuit configured to generate the select signal that is enabled in response to the read signal and disabled in response to the column delay signal;

a reset signal generation circuit configured to: generating a reset signal enabled during a predetermined period in response to the read signal when the select signal is enabled;

a column signal generation circuit configured to generate the column signal including the first pulse and the second pulse sequentially generated in response to the read signal.

5. The semiconductor device as set forth in claim 2,

wherein the syndrome signal includes first to fourth syndromes; and

wherein the syndrome generating circuit includes:

a pre-syndrome generation circuit configured to perform a logical operation on data bits included in the first read data generated during the first read operation to generate first to fourth pre-syndromes; and configured to perform a logical operation on data bits in the second read data generated during the second read operation to generate first through fourth pre-syndromes;

logic circuitry configured to store first through fourth pre-syndromes generated during the first read operation as the first through fourth syndromes in response to a selection signal, and configured to: the first through fourth syndromes are generated by changing an array order of the first through fourth pre-syndromes generated during the second read operation in response to a selection signal and by performing a logical operation on the first through fourth pre-syndromes rearranged according to the changed array order and the first through fourth syndromes generated during the first read operation.

6. The semiconductor device according to claim 5, wherein first to fourth syndromes are determined by a column vector of the first half matrix or the second half matrix.

7. The semiconductor device according to claim 5, wherein the logic circuit generates the first syndrome by performing a logic operation on a first pre-syndrome generated during the first read operation and a fourth pre-syndrome generated during the second read operation, generates a second syndrome by performing a logic operation on a second pre-syndrome generated during the first read operation and a third pre-syndrome generated during the second read operation, generates a third syndrome by performing a logic operation on a third pre-syndrome generated during the first read operation and a second pre-syndrome generated during the second read operation, and generates the fourth syndrome by performing a logic operation on a fourth pre-syndrome generated during the first read operation and a first pre-syndrome generated during the second read operation.

8. The semiconductor device according to claim 5, wherein the logic circuit comprises:

a selection syndrome generation circuit configured to output the first to fourth pre-syndromes as first to fourth selection syndromes when the selection signal is enabled; and configured to change an array order of the first through fourth pre-syndromes to output the first through fourth pre-syndromes rearranged according to the changed array order as first through fourth selection syndromes when the selection signal is disabled; and

a syndrome storage circuit configured to store first to fourth selected syndromes generated during the first read operation as first to fourth syndromes in response to a column latency signal, and configured to generate first to fourth syndromes by performing a logical operation on the first to fourth selected syndromes generated during the second read operation and the first to fourth syndromes stored in response to the column latency signal.

9. The semiconductor device as set forth in claim 1,

wherein the syndrome signal includes first to fourth syndromes; and

wherein the syndrome generating circuit includes:

a pre-syndrome generation circuit configured to perform a logical operation on data bits included in the first read data generated during the first read operation to generate first to fourth pre-syndromes; and configured to perform a logical operation on data bits contained in the second read data generated during the second read operation to generate first through fourth pre-syndromes;

a logic circuit configured to store the first through fourth pre-syndromes generated during the first read operation as first through fourth syndromes, and configured to generate the first through fourth syndromes by performing a logic operation on the first through fourth pre-syndromes generated during the second read operation and the first through fourth syndromes generated during the first read operation.

10. The semiconductor device according to claim 9, wherein the logic circuit is configured to generate the first through fourth syndromes by changing an array order of the first through fourth syndromes stored during the first read operation and performing a logic operation on the first through fourth syndromes rearranged according to the changed array order and the first through fourth pre-syndromes generated during the second read operation.

11. The semiconductor device of claim 1, further comprising:

a parity generation circuit configured to generate a parity including error information about input data during a write operation;

a storage area configured to store the input data and the parity during the write operation.

12. The semiconductor device as set forth in claim 11,

wherein the storage area is configured to: outputting a portion of the stored input data as the first output data and a portion of the stored parity code as the first output parity code during the first read operation; and

wherein the storage area is configured to: outputting a remaining portion of the stored input data as the second output data and outputting a remaining portion of the stored parity code as the second output parity code during the second read operation.

13. The semiconductor device according to claim 1, further comprising a data correction circuit configured to correct an error of the first output data and the second output data using the syndrome signal during the second read operation; and configured to combine the corrected first output data and the second output data to output the combined data as correction data.

14. A method of correcting data errors of a semiconductor device, the method comprising:

the first step is as follows: generating first read data from first output data and a first output parity provided during a first read operation;

the second step is as follows: generating a first pre-verify sub-group including error information on the first read data to store the first pre-verify sub-group; and

the third step: generating second read data from second output data and a second output parity provided during a second read operation, generating a second pre-syndrome group including error information on the second read data, and generating syndrome signals by performing a logical operation on the first pre-syndrome group and the second pre-syndrome group,

wherein the first and second pre-syndrome groups are generated to be symmetric, an

15. The method of claim 14, wherein the first and second light sources are selected from the group consisting of,

wherein the first output data is output from a first storage area,

the second output data is output from a second storage area,

the first output parity is output from a third storage area, an

The second output parity is output from a fourth storage area, an

16. The method as set forth in claim 14, wherein,

wherein the first pre-syndrome group includes first to fourth pre-syndromes generated during the first read operation, the second pre-syndrome group includes first to fourth pre-syndromes generated during the second read operation, and the syndrome signal includes first to fourth syndromes;

wherein the third step comprises:

a step of generating a first syndrome by performing a logical operation on a first pre-syndrome generated from the first read data during the first read operation and a fourth pre-syndrome generated from the second read data during the second read operation;

a step of generating a second syndrome by performing a logical operation on a second pre-syndrome generated from the first read data during the first read operation and a third pre-syndrome generated from the second read data during the second read operation;

a step of generating a third syndrome by comparing a third pre-syndrome generated from the first read data during the first read operation and a second pre-syndrome generated from the second read data during the second read operation; and

a step of generating a fourth syndrome by comparing a fourth syndrome generated from the first read data during the first read operation and a first syndrome generated from the second read data during the second read operation.

17. The method of claim 16, wherein the first through fourth syndromes are arranged by a column vector of a matrix for performing a logical operation on data bits contained in the first read data and the second read data.

18. The method of claim 14, further comprising:

a step of generating a parity including error information on input data during a write operation to store the input data and the parity;

and correcting an error of output data generated from the input data using the syndrome signal to output the corrected output data as corrected data.

19. The method of claim 18, wherein the first and second portions are selected from the group consisting of,

wherein, while the first read operation is being performed, a portion of the input data stored during the write operation is output as the first output data and a portion of the parity code stored during the write operation is output as the first output parity code; and

wherein while the second read operation is being performed, a remaining portion of the input data stored during the write operation is output as the second output data and a remaining portion of the parity code stored during the write operation is output as the second output parity code.

20. A semiconductor device, comprising:

a storage area configured to store input data and a parity during a write operation, configured to output first input data of the input data as first output data and the parity as an output parity during a first read operation, and configured to output second input data of the input data as second output data and the parity as an output parity during a second read operation; and

a syndrome generation circuit configured to generate the parity code from the input data during the write operation, configured to generate a parity code by performing a logical operation on the first output data and the output parity code during the first read operation, and configured to generate a syndrome signal by performing a logical operation on the parity code generated during the first read operation, the second output data, and the output parity code during the second read operation;

wherein the syndrome generating circuit generates the syndrome signal such that a column vector of a first half matrix corresponding to the first output data is symmetrical to a column vector of a second half matrix corresponding to the second output data,

21. The semiconductor device of claim 20, wherein the parity code is a signal including error information on the input data.

22. The semiconductor device according to claim 20, wherein the first output data and the second output data are output from a first storage region and a second storage region, respectively.

23. The semiconductor device as set forth in claim 20,

wherein the storage area is configured to: while performing the write operation, storing a portion of the input data as the first input data, storing a remaining portion of the input data as the second input data, and storing the parity;

wherein the storage area is configured to: outputting the stored first input data as the first output data and outputting the stored parity as an output parity while performing the first read operation; and

wherein the storage area is configured to: outputting the stored second input data as the second output data and outputting the stored parity as an output parity while performing the second read operation.

24. The semiconductor device of claim 20, further comprising:

a column signal generation circuit configured to generate a column signal including a first pulse and a second pulse which are sequentially generated in response to a write signal or a read signal; and configured to generate a select signal and a reset signal, the select signal and the reset signal being enabled in response to the write signal or the read signal; and

a data correction circuit configured to correct errors of the first output data and the second output data using the syndrome signal during the second read operation; and configured to combine the corrected first output data and the second output data to output the combined data as correction data.

25. The semiconductor device according to claim 24, wherein the column signal generation circuit comprises:

a write pulse generation circuit configured to generate a write column signal including a first pulse and a second pulse that are sequentially generated in response to the write signal; and configured to generate a write select signal and a write reset signal, the write select signal and the write reset signal being enabled in response to the write signal;

a read pulse generation circuit configured to generate a read column signal including a first pulse and a second pulse sequentially generated in response to the read signal; and configured to generate a read select signal and a read reset signal, the read select signal and the read reset signal being enabled in response to the read signal;

a control circuit configured to: outputting one of the write column signal and the read column signal as the column signal and one of the write select signal and the read select signal as the select signal in response to the write signal and the read signal; and configured to generate the reset signal that is enabled in response to the write reset signal or the read reset signal.

26. The semiconductor device as set forth in claim 20,

wherein the syndrome signal includes first to fourth syndromes;

wherein the output parity codes include first through fourth output parity codes; and

wherein the syndrome generating circuit includes:

a pre-syndrome generation circuit configured to perform a logical operation on data bits included in the first output data generated during the first read operation to generate first to fourth pre-syndromes; and configured to perform a logical operation on data bits contained in the second output data generated during the second read operation to generate first through fourth pre-syndromes; and

a logic circuit configured to store the first through fourth pre-syndromes generated during the first read operation as first through fourth parity codes included in a parity code in response to a selection signal; configured to change an array order of the first through fourth pre-syndromes generated during the second read operation to store the first through fourth pre-syndromes rearranged in the changed array order as first through fourth parity codes; and configured to generate the first through fourth syndromes by performing a logical operation on the first through fourth parity codes and the first through fourth output parity codes.

27. The semiconductor device according to claim 26, wherein the first to fourth syndromes are set by a column vector of the first half matrix or the second half matrix.

28. The semiconductor device of claim 26, wherein the logic circuit comprises:

a selection syndrome generation circuit configured to output the first to fourth pre-syndromes as first to fourth selection syndromes when the selection signal is enabled; and changing an array order of the first through fourth pre-syndromes to output the first through fourth pre-syndromes rearranged according to the changed array order as first through fourth selection syndromes when the selection signal is disabled;

a parity storage circuit configured to store the first through fourth selected syndromes generated during the first read operation as the first through fourth parity codes in response to a column signal, and configured to perform a logic operation on the first through fourth selected syndromes generated during the second read operation and the first through fourth parity codes stored in response to the column signal to generate and store the first through fourth parity codes; and

a syndrome output circuit configured to perform logical operations on the first through fourth output parity codes and the first through fourth parity codes stored in the parity storage circuit to generate the first through fourth syndromes.