CN106941011A - Semiconductor system - Google Patents

Semiconductor system Download PDF

Info

Publication number
CN106941011A
CN106941011A CN201610509570.2A CN201610509570A CN106941011A CN 106941011 A CN106941011 A CN 106941011A CN 201610509570 A CN201610509570 A CN 201610509570A CN 106941011 A CN106941011 A CN 106941011A
Authority
CN
China
Prior art keywords
signal
address
refresh
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610509570.2A
Other languages
Chinese (zh)
Other versions
CN106941011B (en
Inventor
金昌铉
李在真
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN106941011A publication Critical patent/CN106941011A/en
Application granted granted Critical
Publication of CN106941011B publication Critical patent/CN106941011B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4062—Parity or ECC in refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

A kind of semiconductor system can include the first semiconductor devices and the second semiconductor devices.First semiconductor devices can be configured as exporting command/address signal.Second semiconductor devices can be configured as in the read operation during refresh operation according to the combination of command/address signal come output data.Second semiconductor devices can be configured as extracting error message from data.Second semiconductor devices can be configured as using error message coming in the write operation during refresh operation the mistake of correction data, and calibrated data storage is stored in the second semiconductor devices in the second semiconductor devices and by error message.

Description

Semiconductor system
The cross reference of related application
The priority for the 10-2016-0001232 korean patent applications submitted this application claims on January 5th, 2016, It is by quoting overall be herein incorporated.
Technical field
Embodiment of the disclosure is related to a kind of semiconductor system in general, is used for correction number more particularly, to one kind According to the semiconductor system of mistake.
Background technology
Semiconductor devices can be designed and manufactured to the test pattern function of including being used to assess its operation.I.e., it is possible to Measure the various parameters of semiconductor devices in test mode in wafer scale or package level, and can according to test result come by The semiconductor devices of test is categorized as by chip or chip failing.
Each semiconductor devices can perform write operation and read operation many numbers are received and exported via pad According to, and can be sensed to assess each semiconductor devices by the logic level of the data to exporting from pad.
Due to becoming to be more highly integrated with the development semiconductor devices of manufacturing process technology, therefore the semiconductor of test The quantity of failed storage unit in device has increased.The increasing of the quantity of failed storage unit in the semiconductor devices of test Plus the product yield reduction of semiconductor devices can not be only resulted in, also result in the large storage capacity for being difficult to ensure that semiconductor devices. Therefore, widely used error-correcting code (ECC) circuit is solved as caused by failed storage unit in the semiconductor device Error in data.
Brief description of the drawings
Fig. 1 is the block diagram of the example representation for the configuration for illustrating semiconductor system in accordance with an embodiment of the present disclosure.
Fig. 2 is the block diagram of the example representation of command process circuit that includes of semiconductor system of pictorial image 1.
Fig. 3 be pictorial image 2 semiconductor system include row control circuit example representation block diagram.
Fig. 4 is the block diagram of the example representation for arranging the Error-Correcting Circuit that control circuit includes of pictorial image 3.
Fig. 5 is the electricity of the example representation of data link (repeater) that includes of Error-Correcting Circuit of pictorial image 4 Lu Tu.
Fig. 6 is the block diagram of the example representation for the configuration for illustrating semiconductor system in accordance with an embodiment of the present disclosure.
Fig. 7 is the block diagram of the example representation of command process circuit that includes of semiconductor system of pictorial image 6.
Fig. 8 is the example for arranging the Error-Correcting Circuit that control circuit includes of the semiconductor system shown in pictorial image 6 The block diagram of representative.
Fig. 9 is the block diagram of the example representation of error message storage circuit that includes of semiconductor system of pictorial image 6.
Figure 10 is the timing diagram of the example representation for the operation for illustrating semiconductor system in accordance with an embodiment of the present disclosure.
Figure 11 is the block diagram of the example representation for the configuration for illustrating semiconductor system in accordance with an embodiment of the present disclosure.
Figure 12 is diagram using Fig. 1 to the semiconductor devices shown in Figure 11 or the configuration of the electronic system of semiconductor system Example representation block diagram.
Embodiment
Various embodiments can be directed to a kind of semiconductor system of correction data mistake.
According to embodiment, a kind of semiconductor system can include the first semiconductor devices and the second semiconductor devices.First Semiconductor devices can export command/address signal.Second semiconductor devices can be in the read operation during refresh operation According to the combination of command/address signal come output data.Second semiconductor devices can extract error message from the data.The Two semiconductor devices can carry out the mistake of correction data in the write operation during refresh operation using error message, will be through The data storage of correction is stored therein in wherein and by error message.
According to embodiment, a kind of semiconductor system can include the first semiconductor devices and the second semiconductor devices.First Semiconductor devices can export command/address signal.Second semiconductor devices can be grasped in the reading during the first refresh operation According to the combination of command/address signal come output data in work, the error message on the data can be extracted with by mistake Information is stored therein in, and can be corrected and chosen according to error message in the write operation during the second refresh operation The data stored in memory cell mistake with by calibrated data storage wherein.
According to embodiment, a kind of semiconductor system can include the first semiconductor devices and the second semiconductor devices.First Semiconductor devices can export command/address signal.Second semiconductor devices can be in the read operation during refresh operation According to the combination of command/address signal come output data, error message, the write-in during refresh operation are extracted from the data Error message is stored therein in operation, and vicious data are had with the substitution selection of other addresses according to error message Row address and column address.
It hereinafter will be described with reference to the accompanying drawings the various embodiments of the disclosure.However, embodiment described herein is only It is for the purpose of illustration, and is not intended to limit the scope of the present disclosure.
Referring to Fig. 1, semiconductor system in accordance with an embodiment of the present disclosure can include the first semiconductor devices 1 and the second half Conductor device 2.Second semiconductor devices 2 can include command process circuit 10, bank selection signal and occur circuit 20, address Generation circuit 30, memory block 40, data latch circuit 50 and input/output (I/O) circuit 60.
First semiconductor devices 1 can export the first command/address signal to N command/address signals CA<1:N>, with And the first external data can be received or exported to J external datas DQ<1:J>.First command/address signal to N orders/ Address signal CA<1:N>With the first external data to J external datas DQ<1:J>Can be via transmission address, order and data In at least one set of circuit transmit.Alternatively, the first command/address signal is to N command/address signals CA<1:N>With First external data is to J external datas DQ<1:J>It can be sequentially transmitted via a circuit.First command/address is believed Number to N command/address signals CA<1:N>Number of bits and the first external data to J external datas DQ<1:J>Bit Digit can be set differently according to embodiment.First command/address signal is to N command/address signals CA<1:N>'s Digital " N " and the first external data are to J external datas DQ<1:J>Numeral " J " can be configured to natural number.
Command process circuit 10 can be to the first command/address signal to N command/address signals CA<1:N>Solved Code is to produce activation signal ACT, write signal WT, read signal RD, precharging signal PCG and refresh signal REF.Command process Circuit 10 can produce the first refresh address sequentially counted to M refresh addresses REF_ADD in response to refresh signal REF <1:M>Address ECC_ADD is corrected with the first correction address to K<1:K>.Activation signal ACT can be configured in write-in behaviour By the first command/address signal to N command/address signals CA in work, read operation and refresh operation<1:N>Enable.Write-in Signal WT can be configured in write operation by the first command/address signal to N command/address signals CA<1:N>Make Energy.Signal RD is read to can be configured in read operation by the first command/address signal to N command/address signals CA< 1:N>Enable.Refresh signal REF can be configured in refresh operation by the first command/address signal to N command/address Signal CA<1:N>Enable.Precharging signal PCG can be configured to since write operation, read operation or refresh operation Time point be enabled after elapse of a predetermined time.First refresh address is to M refresh addresses REF_ADD<1:M>Bit Number corrects address ECC_ADD with the first correction address to K<1:K>Number of bits can differently be set according to embodiment Put.First refresh address is to M refresh addresses REF_ADD<1:M>Numeral " M " and first correction address to K correct address ECC_ADD<1:K>Numeral " K " can be configured to natural number.First refresh address is to M refresh addresses REF_ADD<1:M> Numeral " M " and first correction address to K correct address ECC_ADD<1:K>Numeral " K " can be configured to than first life Order/address signal is to N command/address signals CA<1:N>The small natural number of numeral " N ".
Circuit 20, which occurs, for bank selection signal can produce in response to activation signal ACT, precharging signal PCG and refreshing Signal REF and the bank selection signal BS being enabled.Although Fig. 1 illustrates bank selection signal BS by individual signals circuit To represent, but the disclosure is not limited to this.If for example, memory block 40 includes multiple memory banks, bank selection signal BS can include the multiple memory banks for being used for selecting any one memory bank in multiple memory banks included in memory block 40 Selection signal.
Address generator circuit 30 can include row address and occur circuit 31 and column address generation circuit 32.
In response to write signal WT and reading signal RD, circuit 31 occurs for row address can be to the first command/address signal To N command/address signals CA<1:N>Decoded to produce the first row address to M row addresses RADD<1:M>, Huo Zheke To export the first refresh address to M refresh addresses REF_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M >。
In response to write signal WT and reading signal RD, circuit 32 occurs for column address can be to the first command/address signal To N command/address signals CA<1:N>Decoded to produce the first column address to K column address CADD<1:K>, Huo Zheke Address is corrected to K corrections address ECC_ADD to export first<1:K>It is used as the first column address to K column address CADD<1:K >。
That is, in write operation or read operation, address generator circuit 30 can be to the first command/address signal to N Command/address signal CA<1:N>Decoded to produce the first row address to M row addresses RADD<1:M>With the first column address To K column address CADD<1:K>.In refresh operation, address generator circuit 30 can export the first refresh address to M refreshings Address REF_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M>, and the first correction address can be exported extremely K corrects address ECC_ADD<1:K>It is used as the first column address to K column address CADD<1:K>.
Memory block 40 can include line control circuit 41, row control circuit 42 and cell array 43.Here, it is aforementioned Memory bank can be configured as including line control circuit 41, row control circuit 42 and cell array 43.Memory block 40 can by with It is set to including multiple memory banks.
Line control circuit 41 can be in response to bank selection signal BS according to the first row address to M row addresses RADD <1:M>Optionally to activate any one of the word lines in multiple wordline (not shown).
Row control circuit 42 can be in response to bank selection signal BS according to the first column address to K column address CADD <1:K>To select to be connected to multiple memory cell of the selected word line among multiple wordline (not shown), and can be from choosing The data stored in memory cell (not shown) extract error message.Row control circuit 42 can use the error message of extraction The mistake of correction data with by calibrated data storage in memory cell (not shown) is chosen, and can be by error message It is stored in parity elements (not shown).Row control circuit 42 can be via the first global lines to J global lines GIO<1:J >And receive or output data.Here, error message represents there is the retention time shorter than the retention time of normal memory cell (data for corresponding to memory cell can be tieed up after being written into memory cell in the case of without any refresh operation The maximum time held) memory cell positional information.Parity elements (not shown) can be with memory cell (not shown) With identical structure.
Cell array 43 can include the multiple memory cell (not shown) for being connected to multiple wordline (not shown) and multiple Parity elements (not shown).Data can be stored in memory cell (not shown), and error message can be stored in very In even parity check unit (not shown).
Data latch circuit 50, which can be latched, is loaded into the first global lines to J global lines GIO<1:J>On data, To give the first input/output (I/O) line to J input/output lines IO by the data output of latch<1:J>.Data latches electricity Road 50, which can be latched, is loaded into the first I/O lines to J I/O lines IO<1:J>On data, by the data output of latch to the One global lines are to J global lines GIO<1:J>.
I/O circuits 60 can export the first I/O lines to J I/O lines IO<1:J>On data be used as the first external data To J external datas DQ<1:J>.I/O circuits 60 can be by the first external data produced from the first semiconductor devices 1 to J External data DQ<1:J>Export to the first I/O lines to J I/O lines IO<1:J>.
Referring to Fig. 2, command process circuit 10 can include command decoder 11, delay and set circuit 12, logic circuit 13 With control circuit 14.
Command decoder 11 can be to the first command/address signal to N command/address signals CA<1:N>Decoded Believed with producing activation signal ACT, refresh signal REF, internal precharge signals IPCG, inside write signal IWT and internal read Number IRD.
Delay setting circuit 12 can include the first delay circuit 121, the second delay circuit 122 and the 3rd delay circuit 123。
First delay circuit 121 can postpone refresh signal REF the first time delay to produce refreshing reading signal RD_ REF.First time delay can be configured to row address strobe (RAS) to column address strobe (CAS) time delay (tRCD).
Second delay circuit 122, which will can refresh, to be read signal RD_REF the second time delays of delay to produce refreshing write-in Signal WT_REF.Second time delay can be configured to CAS to CAS time delay (tCCD).
3rd delay circuit 123 can will refresh write signal WT_REF and postpone for the 3rd time delay to produce refreshing preliminary filling Electric signal PCG_REF.3rd time delay can be configured to write-recovery time (tWR).
First time delay to the 3rd time delay can be set differently according to embodiment.
For example, delay setting circuit 12 can postpone refresh signal REF, read with producing the refreshing sequentially enabled Signal RD_REF, refreshing write signal WT_REF and refreshing precharging signal PCG_REF.
Logic circuit 13 can produce in response to internal precharge signals IPCG or refresh precharging signal PCG_REF and by The precharging signal PCG of enable.Logic circuit 13 can produce in response to internal write signal IWT or refresh write signal WT_ REF and the write signal WT being enabled.Logic circuit 13 can produce in response to internal read signal IRD or refresh reading signal RD_REF and the reading signal RD being enabled.
Control circuit 14 to include count signal and occur circuit 141, counter 142 and correction address generator circuit 143.
Circuit 141, which occurs, for count signal can produce count signal CNT, and count signal CNT is inputted from refresh signal REF It is enabled after the predetermined amount of time that the time point for occurring circuit 141 to count signal starts.
Counter 142 can produce the first refresh address sequentially counted to M refreshings in response to count signal CNT Address REF_ADD<1:M>.Counter 142 can produce counting controling signal RC, if the first refresh address to M refresh ground Location REF_ADD<1:M>Whole bits be all counted, then counting controling signal RC is enabled.
Correction address generator circuit 143 can produce the first correction sequentially counted in response to counting controling signal RC Address to K correct address ECC_ADD<1:K>.
That is, control circuit 14 can produce the first refresh address sequentially counted to M in response to refresh signal REF Refresh address REF_ADD<1:M>Address ECC_ADD is corrected with the first correction address to K<1:K>.
For example, control circuit 14 can produce the first correction address to K corrections address in response to refresh signal REF ECC_ADD<1:K>If, the first refresh address to M refresh addresses REF_ADD<1:M>Whole bits be all counted, then First corrects address to K corrections address ECC_ADD<1:K>Counted up a bit.
Referring to Fig. 3, row control circuit 42 can include Error-Correcting Circuit 420 and sensing amplifier 430.
Error-Correcting Circuit 420 can be deposited in response to reading signal RD from be connected to memory cell (not shown) first Body line is stored up to J memory bank lines BIO<1:J>On data extract error message, and error message can be used to carry out correction number According to mistake with by calibrated data output to the first global lines to J global lines GIO<1:J>.In response to write signal WT, Error-Correcting Circuit 420 can be by calibrated data output to the first memory bank line to J memory bank lines BIO<1:J>, and Error message can be exported to the first parity line to P parity lines PIO<1:P>.Here, the first parity line To P parity lines PIO<1:P>Quantity can be set differently according to embodiment.First parity line is to P Parity line PIO<1:P>Parity elements (not shown) can be connected to.
Sensing amplifier 430 can be sensed and amplified and be connected to by the first column address to K column address CADD<1:K>And First memory bank line of the memory cell chosen is to J memory bank lines BIO<1:J>On data, and can will sense and put Big data storage is wherein.Sensing amplifier 430, which can be stored in, to be connected to by the first column address to K column address CADD <1:K>And the first parity line of the parity elements chosen is to P parity lines PIO<1:P>The mistake of upper loading Information.
Referring to Fig. 4, Error-Correcting Circuit 420 can include pulse signal generation circuit 421, latch circuit 422, coding Generation circuit 423, data link 424 and even-odd check repeater 425.
Pulse signal generation circuit 421 can produce write pulse signal WTP, write pulse signal WTP include in response to Write signal WT and the pulse produced.Pulse signal generation circuit 421 can produce reading pulse signal RDP, read pulse letter Number RDP includes the pulse in response to reading signal RD and producing.
Latch circuit 422 can latch the first storage in response to write pulse signal WTP or reading pulse signal RDP Body line is to J memory bank lines BIO<1:J>On data, to produce the first internal data to J internal datas ID<1:J>.Latch Device circuit 422 can latch the first parity line to P parity lines PIO in response to reading pulse signal RDP<1:P> On error message, to produce the first parity signal to P parity signals PRT<1:P>.
The first internal data can be sensed to J internal datas ID by compiling code generating circuit 423<1:J>Logic level, with Producing includes the first error code of error message to J error codes ERC<1:J>With the first parity check code to P even-odd checks Code PC<1:P>.The first parity signal can be exported to P parity signals PRT by compiling code generating circuit 423<1:P>Make For the first parity check code to P parity check codes PC<1:P>.First error code is to J error codes ERC<1:J>It can include On the first internal data to J internal datas ID<1:J>Among error bit position positional information.If for example, first Error code ERC<1>It is generated as with logic high, it means the first internal data ID<1>With mistake.First is strange Even parity check code is to P parity check codes PC<1:P>It can be configured to include on the first internal data to J internal datas ID <1:J>Error message signal.Compiling code generating circuit 423 can use conventional ECC circuit to realize.
Data link 424 can be in response to write pulse signal WTP by the first global lines to J global lines GIO<1: J>On data output to the first memory bank line to J memory bank lines BIO<1:J>.In response to reading pulse signal RDP, data Repeater 424 can be according to the first error code to J error codes ERC<1:J>And by the first memory bank line to J memory bank lines BIO<1:J>On data logic level it is anti-phase, by anti-phase data output to the first global lines to J global lines GIO< 1:J>。
Even-odd check repeater 425 can be in response to write pulse signal WTP by the first parity check code to P odd evens Check code PC<1:P>Export to the first parity line to P parity lines PIO<1:P>.
Referring to Fig. 5, data link 424 can include the first repeater 4241 and the second repeater 4242.
First repeater 4241 can be in response to write pulse signal WTP to the first global lines GIO<1>On data it is anti- Mutually enter row buffering, the first memory bank line BIO is given by inverter buffer data output<1>.
If the first error code ERC<1>With logic high, then the second repeater 4242 can be in response to reading pulse Signal RDP and to the first memory bank line BIO<1>On data enter row buffering, buffered data is exported to the first global lines GIO <1>.If the first error code ERC<1>With logic low, then the second repeater 4242 can be in response to reading pulse signal RDP and to the first memory bank line BIO<1>On data inversion enter row buffering, by inverter buffer data output to first complete Exchange line GIO<1>.Here, if the first error code ERC<1>With logic high, then mean the first memory bank line BIO<1> On data there is mistake.If the first error code ERC<1>With logic low, then mean the first memory bank line BIO<1 >On data do not have mistake.
The data link 424 shown in Fig. 5 has such configuration：Data are via the first global lines GIO<1>Or first Memory bank line BIO<1>To input or export.However, data link 424 can be configured with via its input or export First global lines of multiple data are to J global lines GIO<1:J>With the first memory bank line to J memory bank lines BIO<1:J>. That is, data link 424 can be configured as including J the first repeaters and J the second repeaters.
Fig. 6 is the block diagram for the configuration for illustrating semiconductor system in accordance with an embodiment of the present disclosure.
Referring to Fig. 6, semiconductor system in accordance with an embodiment of the present disclosure can include the first semiconductor devices 3 and the second half Conductor device 4.Second semiconductor devices 4 can include command process circuit 100, bank selection signal occur circuit 200, Circuit 300, memory block 400, error message storage circuit 500, data latch circuit 600 and I/O circuits 700 occur for location.
First semiconductor devices 3 can export the first command/address signal to N command/address signals CA<1:N>, with And the first external data can be received or exported to J external datas DQ<1:J>.First command/address signal to N orders/ Address signal CA<1:N>With the first external data to J external datas DQ<1:J>Can be via transmission address, order and data In at least one set of circuit transmit.Alternatively, the first command/address signal is to N command/address signals CA<1:N>With First external data is to J external datas DQ<1:J>It can be continuously transmitted via a circuit.First command/address signal To N command/address signals CA<1:N>Number of bits and the first external data to J external datas DQ<1:J>Bit Number can be set differently according to embodiment.First command/address signal is to N command/address signals CA<1:N>Number Word " N " and the first external data are to J external datas DQ<1:J>Numeral " J " can be configured to natural number.
Command process circuit 100 can be to the first command/address signal to N command/address signals CA<1:N>Solved Code is to produce activation signal ACT, write signal WT, read signal RD, precharging signal PCG, refresh signal REF and control signal ESCTR.Command process circuit 100 may also respond to refresh signal REF and produce the first refresh address sequentially counted extremely M refresh addresses REF_ADD<1:M>Address ECC_ADD is corrected with the first correction address to K<1:K>.Command process circuit 100 can produce control signal ESCTR, if first corrects address to K corrections address ECC_ADD<1:K>Whole bits Position is counted, then control signal ESCTR is enabled.Activation signal ACT can be configured in write operation, read operation and brush By the first command/address signal to N command/address signals CA in new operation<1:N>Enable.Write signal WT can be set For in write operation by the first command/address signal to N command/address signals CA<1:N>Enable.Reading signal RD can be with It is arranged in read operation by the first command/address signal to N command/address signals CA<1:N>Enable.Refresh signal REF can be configured in refresh operation by the first command/address signal to N command/address signals CA<1:N>Enable. Precharging signal PCG can be configured to pre- since the time point write operation, read operation or refresh operation Fix time the signal being enabled afterwards.First refresh address is to M refresh addresses REF_ADD<1:M>Number of bits and first Address is corrected to K corrections address ECC_ADD<1:K>Number of bits can be set differently according to embodiment.First Refresh address is to M refresh addresses REF_ADD<1:M>Numeral " M " and first correction address to K correct address ECC_ADD< 1:K>Numeral " K " can be configured to natural number.First refresh address is to M refresh addresses REF_ADD<1:M>Numeral " M " and first corrects address to K corrections address ECC_ADD<1:K>Numeral " K " can be configured to than the first order/ground Location signal is to N command/address signals CA<1:N>The small natural number of numeral " N ".
Circuit 200, which occurs, for bank selection signal can produce in response to activation signal ACT, precharging signal PCG and brush New signal REF and the bank selection signal BS being enabled.Although bank selection signal BS is illustrated for convenience of description For a signal, but bank selection signal BS can be arranged to the multiple storages for selecting memory block 400 to include Multiple signals of any one memory bank in body.
Address generator circuit 300 can include row address and occur circuit 310 and column address generation circuit 320.
In response to write signal WT and reading signal RD, circuit 310 occurs for row address can be to the first command/address signal To N command/address signals CA<1:N>Decoded to produce the first row address to M row addresses RADD<1:M>, Huo Zheke To export the first refresh address to M refresh addresses REF_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M >.If control signal ESCTR is enabled, for example, then row address generation circuit 310 can export first object address to M mesh Mark address TG_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M>.
In response to write signal WT and reading signal RD, circuit 320 occurs for column address can be to the first command/address signal To N command/address signals CA<1:N>Decoded to produce the first column address to K column address CADD<1:K>, Huo Zheke Address is corrected to K corrections address ECC_ADD to export first<1:K>It is used as the first column address to K column address CADD<1:K >。
That is, address generator circuit 300 can be in write operation or read operation to the first command/address signal to N Command/address signal CA<1:N>Decoded, to produce the first row address to M row addresses RADD<1:M>With the first column address To K column address CADD<1:K>.In the first refresh operation, address generator circuit 300 can export the first refresh address to M refresh addresses REF_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M>, and the first correction can be exported Address to K correct address ECC_ADD<1:K>It is used as the first column address to K column address CADD<1:K>.Refresh behaviour second In work, address generator circuit 300 can export first object address to M destination addresses TG_ADD<1:M>As the first row Location is to M row addresses RADD<1:M>.Here, the second refresh operation can correspond to the volume performed after the first refresh operation Outer refresh operation.
Memory block 400 can include line control circuit 440, row control circuit 450 and cell array 460.Here, carried before And memory bank can be configured as including line control circuit 440, row control circuit 450 and cell array 460.Memory block 400 It can be configured as including multiple memory banks.
Line control circuit 440 can be in response to bank selection signal BS according to the first row address to M row addresses RADD<1:M>Optionally to activate any one in multiple wordline (not shown).
Row control circuit 450 can be in response to bank selection signal BS according to the first column address to K column address CADD<1:K>To select the multiple memory cell (not shown) for the selected word line being connected in multiple wordline (not shown), and The data that can be stored from the multiple memory cell (not shown) chosen extract error message.Row control circuit 450 can be produced Raw error pulse signal EP, if data have mistake, error pulse signal EP is enabled.Row control circuit 450 can make With the error message of extraction come the mistake of correction data, calibrated data storage (is not shown in the multiple memory cell Go out) in and error message is stored in parity elements (not shown).Row control circuit 450 can be global via first Line is to J global lines GIO<1:J>To receive or output data.Here, error message represents the guarantor with than normal memory cell Hold short retention time time and (correspond to the data of memory cell after memory cell is written into without any refresh operation In the case of the maximum time that can maintain) memory cell positional information.
In embodiment, in addition to error pulse signal EP, row control circuit 450 can be controlled with the row shown in Fig. 3 There is circuit 42 substantially the same configuration to perform substantially the same operation.Therefore, it will hereinafter omit to row control The detailed description of circuit 450 is to avoid repeat specification.
Cell array 460 can include the multiple memory cell (not shown) for being connected to multiple wordline (not shown) and multiple Parity elements (not shown).Data can be stored in memory cell (not shown), and error message can be stored in very In even parity check unit (not shown).
Error message storage circuit 500 can store the first row address to M rows in response to error pulse signal EP Location RADD<1:M>It is used as first object address to M destination addresses TG_ADD<1:M>, and can be in response to control signal ESCTR and export first object address to M destination addresses TG_ADD<1:M>.
Data latch circuit 600 can latch the first global lines to J global lines GIO<1:J>On data with will lock The data output deposited is to the first I/O lines to J I/O lines IO<1:J>.Data latch circuit 600 can latch the first I/O lines To J I/O lines IO<1:J>On data with by the data output of latch to the first global lines to J global lines GIO<1:J>.
I/O circuits 700 can export the first I/O lines to J I/O lines IO<1:J>On data be used as the first external data To J external datas DQ<1:J>.I/O circuits 700 can be by the first external data produced from the first semiconductor devices 3 to J External data DQ<1:J>Export to the first I/O lines to J I/O lines IO<1:J>.
Referring to Fig. 7, command process circuit 100 can include command decoder 110, delay and set circuit 120, logic circuit 130th, circuit 150 occurs for control circuit 140 and control signal.
Command decoder 110 can be to the first command/address signal to N command/address signals CA<1:N>Solved Code, to produce activation signal ACT, refresh signal REF, internal precharge signals IPCG, inside write signal IWT and internal reading Signal IRD.Command decoder 110 can produce refresh signal REF again in response to internal refresh signal IREF.
Delay setting circuit 120 can include the first delay circuit 124, the second delay circuit 125 and the 3rd delay circuit 126。
First delay circuit 124 can postpone refresh signal REF the first time delay to produce refreshing reading signal RD_ REF.First time delay can be configured to row address strobe (RAS) to column address strobe (CAS) time delay (tRCD).
Second delay circuit 125, which will can refresh, to be read signal RD_REF the second time delays of delay to produce refreshing write-in Signal WT_REF.Second time delay can be configured to CAS to CAS time delay (tCCD).
3rd delay circuit 126 can will refresh write signal WT_REF and postpone for the 3rd time delay to produce refreshing preliminary filling Electric signal PCG_REF.3rd time delay can be configured to write-recovery time (tWR).
First time delay to the 3rd time delay can be set differently according to embodiment.
For example, delay setting circuit 120 can postpone refresh signal REF, believed with producing the refreshing sequentially enabled and reading Number RD_REF, refresh write signal WT_REF and refresh precharging signal PCG_REF.
Logic circuit 130 can be produced in response to internal precharge signals IPCG or refreshing precharging signal PCG_REF The precharging signal PCG being enabled.Logic circuit 130 can produce in response to internal write signal IWT or refresh write signal WT_REF and the write signal WT being enabled.Logic circuit 130 can produce in response to internal read signal IRD or refresh reading Signal RD_REF and the reading signal RD being enabled.
Refresh control circuit 144, counter 145 and correction address generator circuit 146 can be included by controlling circuit 140.
Refresh control circuit 144 can produce count signal CNT, and count signal CNT is inputted to brush from refresh signal REF It is enabled after the predetermined amount of time that the time point of new control circuit 144 starts.Refresh control circuit 144 can produce inner brush New signal IREF, internal refresh signal IREF refresh pre- after refresh signal REF is enabled in response to control signal ESCTR Time point when charging signals PCG_REF is enabled is enabled.
Counter 145 can produce the first refresh address sequentially counted to M refreshings in response to count signal CNT Address REF_ADD<1:M>.Counter 145 can produce counting controling signal RC, if the first refresh address to M refresh ground Location REF_ADD<1:M>Whole bits be counted, then counting controling signal RC is enabled.
Correction address generator circuit 146 can produce the first correction sequentially counted in response to counting controling signal RC Address to K correct address ECC_ADD<1:K>.
For example, control circuit 140 can produce the first refresh address sequentially counted extremely in response to refresh signal REF M refresh addresses REF_ADD<1:M>Address ECC_ADD is corrected with the first correction address to K<1:K>.Control circuit 140 can To produce internal refresh signal IREF in response to control signal ESCTR, internal refresh signal IREF is inputted from refresh signal REF It is enabled after the predetermined amount of time started to time point during control circuit 140.Here, the predetermined amount of time is represented from brush Period of the time point that new signal REF is enabled until refreshing the time point that precharging signal PCG_REF is enabled.
For example, control circuit 140 can produce the first correction address to K corrections address in response to refresh signal REF ECC_ADD<1:K>If, the first refresh address to M refresh addresses REF_ADD<1:M>Whole bits be counted, then One corrects address to K corrections address ECC_ADD<1:K>Counted up a bit.
Circuit 150, which occurs, for control signal can produce control signal ESCTR, if the first correction address to K corrections ground Location ECC_ADD<1:K>Whole bits be counted, then control signal ESCTR is enabled.
Referring to Fig. 8, the Error-Correcting Circuit 4500 that row control circuit 450 includes can include pulse signal generation circuit 451st, latch circuit 452, volume code generating circuit 453, data link 454, even-odd check repeater 455 and bursts of error hair Raw circuit 456.
Pulse signal generation circuit 451 can produce write pulse signal WTP, write pulse signal WTP include in response to Write signal WT and the pulse produced.Pulse signal generation circuit 451 can produce reading pulse signal RDP, read pulse letter Number RDP includes the pulse in response to reading signal RD and producing.
Latch circuit 452 can latch the first storage in response to write pulse signal WTP or reading pulse signal RDP Body line is to J memory bank lines BIO<1:J>On data, to produce the first internal data to J internal datas ID<1:J>.Latch Device circuit 452 can latch the first parity line to P parity lines PIO in response to reading pulse signal RDP<1:P> On error message, to produce the first parity signal to P parity signals PRT<1:P>.
The first internal data can be sensed to J internal datas ID by compiling code generating circuit 453<1:J>Logic level, with Producing includes the first error code of error message to J error codes ERC<1:J>With the first parity check code to P even-odd checks Code PC<1:P>.The first parity signal can be exported to P parity signals PRT by compiling code generating circuit 453<1:P>Make For the first parity check code to P parity check codes PC<1:P>.First error code is to J error codes ERC<1:J>It can include On the first internal data to J internal datas ID<1:J>Among error bit position positional information.If for example, first Error code ERC<1>With logic high, it means the first internal data ID<1>With mistake.First parity check code To P parity check codes PC<1:P>It can be configured to include on the first internal data to J internal datas ID<1:J>'s The signal of error message.Compiling code generating circuit 453 can be realized by using conventional ECC circuit.
Data link 454 can be in response to write pulse signal WTP by the first global lines to J global lines GIO<1: J>On data output to the first memory bank line to J memory bank lines BIO<1:J>.In response to reading pulse signal RDP, data Repeater 454 can be according to the first error code to J error codes ERC<1:J>Come to the first memory bank line to J memory bank lines BIO<1:J>On data logic level carry out it is anti-phase, oppisite phase data is exported to the first global lines to J global lines GIO <1:J>.Data link 454, which to be had, configure with the identical of data link 424 shown in Fig. 5 to perform identical operation. Therefore, it will hereinafter omit to the detailed description of data link 454 to avoid repeat specification.
Even-odd check repeater 455 can be in response to write pulse signal WTP by the first parity check code to P odd evens Check code PC<1:P>Export to the first parity line to P parity lines PIO<1:P>.
Circuit 456, which occurs, for bursts of error to produce error pulse signal EP in response to reading pulse signal RDP, mistake If pulse signal EP includes the first error code to J error codes ERC<1:J>In at least one be enabled, the arteries and veins produced Punching.
Referring to Fig. 9, error message storage circuit 500 can include latch signal and occur circuit 510 and address latch circuit 520.Address latch circuit 520 can include the first address latch 521 to M address latch 523.
Circuit 510, which occurs, for latch signal to produce and be generated in error pulse signal EP in response to refresh signal REF When the first input and latch signal for being enabled of time point to M input and latch signals PI<1:M>, and can be in response to control Signal ESCTR and produce what is be enabled after the predetermined amount of time time point when refresh signal REF is inputted to its First output latch signal is to M output latch signals PO<1:M>.
First address latch 521 can be in response to the first input and latch signal PI<1>And latch the first row address RADD< 1>, and can be in response to the first output latch signal PO<1>And the first row address RADD of output latch<1>It is used as the first mesh Mark address TG_ADD<1>.
Second address latch 522 can be in response to the second input and latch signal PI<2>And latch the second row address RADD< 2>, and can be in response to the second output latch signal PO<2>And the second row address RADD of output latch<2>It is used as the second mesh Mark address TG_ADD<2>.
M address latch 523 can be in response to M input and latch signals PI<M>And latch M row addresses RADD<M>, And can be in response to M output latch signals PO<M>And the M row addresses RADD of output latch<M>It is used as M destination addresses TG_ADD<M>。
In addition to input signal and output signal, each into (M-1) address latch of the 3rd address latch can To match somebody with somebody with one in the first address latch 521, the second address latch 522 and M address latch 523 with identical Put.Therefore, it will hereinafter omit and repetition will be avoided to the detailed description of (M-1) address latch to the 3rd address latch Explanation.
For example, the time point when mistake occurs, error message storage circuit 500 can latch the first row address to M Row address RADD<1:M>, to produce the first object address for including the positional information on the memory cell with wrong data To M destination addresses TG_ADD<1:M>.
Hereinafter, it is incorporated into the first refresh operation and error in data occurs and the data are wrong in the second refresh operation The example that is corrected by mistake, reference picture 10 describe the operation of the semiconductor system with aforementioned arrangements.
In time point T1, the first semiconductor devices 3 can export the first command/address signal to N command/address signals CA<1:N>To start refresh operation.
The command decoder 110 of command process circuit 100 can be believed the first command/address signal to N command/address Number CA<1:N>Decoded, to produce the refresh signal REF with logic high.
In time point T2, the refresh control circuit 144 of command process circuit 100 can produce count signal CNT, count letter Number CNT is made after the predetermined amount of time time point T1 when refresh signal REF is inputted to refresh control circuit 144 Can be with logic high.
In time point T3, delay setting circuit 120 can postpone refresh signal REF and refresh precharging signal PCG_ to produce REF.Time from time point T2 to time point T3 can correspond to prolonging for the delay circuit 126 of the first delay circuit 124 to the 3rd The summation of slow time.That is, from time point T2 to time point T3 time can correspond to RAS to the CAS delay time (tRCD), CAS is to CAS delay time (tCCD) and the summation of write-recovery time (tWR).
In time point T4, control the counter 145 of circuit 140 can be in response to the count signal that is produced in time point T2 CNT comes to the first row address to M row addresses RADD<1:M>Counted.Control circuit 140 counter 145 can when Between after point T4 to the first row address to M row addresses RADD<1:M>Whole bits counted.Now, address is corrected Generation circuit 146 can correct address ECC_ADD to the first correction address to K<1:K>Whole bits counted.
In time point T5, circuit 150, which occurs, for control signal can produce control signal ESCTR, and control signal ESCTR passes through Address ECC_ADD is corrected to the first correction address to K<1:K>Whole bits counted and be enabled as with logic Low level.
In time point T6, the first semiconductor devices 3 can export the first command/address signal to N command/address signals CA<1:N>To start refresh operation.
The command decoder 110 of command process circuit 100 can be believed the first command/address signal to N command/address Number CA<1:N>Decoded to produce the refresh signal REF with logic high.Here, the first command/address signal is passed through To N command/address signals CA<1:N>And the refresh signal REF produced represents the signal for performing the first refresh operation.
In time point T7, the refresh control circuit 144 of command process circuit 100, which can be produced, to be enabled as with logically high The count signal CNT of level.That is, refresh control circuit 144 can produce count signal CNT, and count signal CNT is in refresh signal REF has logic high after inputting the predetermined amount of time started to time point T6 during refresh control circuit 144.
In time point T8, delay set circuit 120 can to postponing in the time point T6 refresh signal REF produced, Refresh precharging signal PCG_REF to produce.Time from time point T6 to time point T8 can correspond to the first delay circuit The summation of the time delay of 124 to the 3rd delay circuits 126.That is, it can be set to time point T8 time from time point T6 For RAS to CAS delay time (tRCD), CAS to CAS delay time (tCCD) and the summation of write-recovery time (tWR).
In time point T9, refresh control circuit 144 can produce internal refresh signal IREF, and internal refresh signal IREF rings Ying Yu has the control signal ESCTR of logic low and is enabled as with logic high.That is, internal refresh signal IREF It can be generated as after the predetermined amount of time time point T6 when refresh signal REF is inputted with logically high electricity It is flat.
In time point T10, the command decoder 110 of command process circuit 100 can be in response to internal refresh signal IREF And the refresh signal REF with logic high is produced again.The refresh signal REF produced by internal refresh signal IREF Represent the signal for performing the second refresh operation.
In response to control signal ESCTR and refresh signal REF, error message storage circuit 500 can export including on The first object address of the positional information of memory cell with wrong data is to M destination addresses TG_ADD<1:M>.
Circuit 310 occurs for row address can export first object address to M targets in response to control signal ESCTR Location TG_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M>.
Line control circuit 440 can be in response to bank selection signal BS according to the first row address to M row addresses RADD<1:M>To activate the wordline (not shown) for being connected to failed storage unit (not shown).
Row control circuit 450 can come in response to bank selection signal BS according to the first column address to K column address CADD<1:K>Selection is connected to the memory cell (not shown) for the wordline (not shown) chosen, and can be from the storage chosen The data stored in unit (not shown) extract error message.Row control circuit 450 can use the error message of extraction to come school The mistake of correction data is so that calibrated data storage in multiple memory cell (not shown), and can be stored up error message Exist in parity elements (not shown).Row control circuit 450 can be via the first global lines to J global lines GIO<1:J> To export the data stored in multiple memory cell.
Data-latching circuit 600 can latch the first global lines to J global lines GIO<1:J>On data with will latch Data output to the first I/O lines to J I/O lines IO<1:J>.
I/O circuits 700 can export the first I/O lines to J I/O lines IO<1:J>On data be used as the first external data To J external datas DQ<1:J>.
As described above, can be corrected according to the semiconductor system of embodiment in refresh operation with the short retention time The mistake of the data stored in failed storage unit is to prevent error in data.
Figure 11 is the block diagram for the configuration for illustrating semiconductor system in accordance with an embodiment of the present disclosure.
Referring to Figure 11, semiconductor system in accordance with an embodiment of the present disclosure can include the first semiconductor devices 5 and second Semiconductor devices 6.Second semiconductor devices 6 can include command process circuit 61, bank selection signal occur circuit 62, Circuit 63, memory block 64, repair control circuit 65, data-latching circuit 66 and I/O circuits 67 occur for location.
First semiconductor devices 5 can export the first command/address signal to N command/address signals CA<1:N>, with And the first external data can be received or exported to J external datas DQ<1:J>.
Command process circuit 61 can be to the first command/address signal to N command/address signals CA<1:N>Solved Code, to produce activation signal ACT, write signal WT, read signal RD, precharging signal PCG and refresh signal REF.At order Reason circuit 61 can also produce the first refresh address sequentially counted to M refresh addresses in response to refresh signal REF REF_ADD<1:M>Address ECC_ADD is corrected with the first correction address to K<1:K>.Command process circuit 61 can with Fig. 1 There is identical to configure to perform identical operation for shown command process circuit 10.Therefore, it will hereinafter omit to order The description of process circuit 61.
Circuit 62, which occurs, for bank selection signal can produce in response to activation signal ACT, precharging signal PCG and refreshing Signal REF and the bank selection signal BS being enabled.Although bank selection signal BS is illustrated as convenience One signal, but bank selection signal BS multiple depositing of being configured to select that memory block 64 includes by multiple signals Store up any one in body.Circuit 62, which occurs, for bank selection signal to occur with the bank selection signal shown in Fig. 1 Circuit 200, which occurs, for the bank selection signal shown in circuit 20 and Fig. 6 has identical configuration.
Address generator circuit 63 can in write operation or read operation to the first command/address signal to N orders/ Address signal CA<1:N>Decoded, to produce the first row address to M row addresses RADD<1:M>With the first column address to K Column address CADD<1:K>.In refresh operation, address generator circuit 63 can export the first refresh address to M refresh addresses REF_ADD<1:M>It is used as the first row address to M row addresses RADD<1:M>, and the first correction address can be exported to K Correct address ECC_ADD<1:K>It is used as the first column address to K column address CADD<1:K>.Address generator circuit 63 can be with figure There is identical to configure to perform identical operation for address generator circuit 30 shown in 1.Therefore, it will hereinafter omit over the ground The description of circuit 63 occurs for location to avoid repeat specification.
Memory block 64 can include memory bank 641, the first fuse circuit 642, first and repair circuit 643, the second fuse electricity Repair circuit 645 in road 644 and second.
Memory bank 641 can produce error pulse signal EP in the read operation during refresh operation, if according to A line address is to M row addresses RADD<1:M>With the first column address to K column address CADD<1:K>And the memory cell chosen The data stored in (not shown) have mistake, then error pulse signal EP is enabled, and memory bank 641 can also be in refresh operation The mistake of correction data in the write operation of period, by calibrated data storage in the memory cell chosen and by mistake False information is stored in parity elements.Here, memory bank 641 can be configured as including the row control described by reference picture 1 Circuit 41 processed, column address circuitry 42 and cell array 43.
If the first row address is to M row addresses RADD<1:M>There is the memory cell (not shown) of mistake with selection Combination, then that the first row fuse signal can be exported in response to row repair signal RPX is molten to X rows for the first fuse circuit 642 Silk signal RF<1:X>.Here, the first row fuse signal is to X row fuse signals RF<1:X>It can be configured to be used to replace the A line address is to M row addresses RADD<1:M>Address.First fuse circuit 642 can be used including multiple fuse cells Array of fuses is realized.
First, which repairs circuit 643, can include multiple reparation unit (not shown), and the multiple reparation unit is connected to sound Should be in bank selection signal BS according to the first row fuse signal to X row fuse signals RF<1:X>Carry out the redundancy word of selection Line.
If the first column address is to K column address CADD<1:K>There is the memory cell (not shown) of mistake with selection Combination, then that first row fuse signal can be exported in response to row repair signal RPY is molten to Y row for the second fuse circuit 644 Silk signal CF<1:Y>.Here, first row fuse signal is to Y row fuse signals CF<1:Y>It can be configured to be used to replace the One column address is to K column address CADD<1:K>Address.Second fuse circuit 644 can be used including multiple fuse cells Array of fuses is realized.
Second, which repairs circuit 645, can include multiple reparation unit (not shown), and the multiple reparation unit is connected to sound Should be in bank selection signal BS according to first row fuse signal to Y row fuse signals CF<1:Y>Carry out the redundant digit of selection Line.
Repair control circuit 65 can produce the row repair signal RPX and row being enabled in response to error pulse signal EP Repair signal RPY.
Data-latching circuit 66 can latch the first global lines to J global lines GIO<1:J>On data, will latch Data output to the first I/O lines to J I/O lines IO<1:J>.Data-latching circuit 66 can latch the first I/O lines to J I/O lines IO<1:J>On data, by the data output of latch to the first global lines to J global lines GIO<1:J>.Data are locked Depositing circuit 66 can configure with the data-latching circuit 50 shown in Fig. 1 with identical.
I/O circuits 67 can export the first I/O lines to J I/O lines IO<1:J>On data be used as the first external data To J external datas DQ<1:J>.I/O circuits 67 can be by the first external data produced from the first semiconductor devices 5 to J External data DQ<1:J>Export to the first I/O lines to J I/O lines IO<1:J>.I/O circuits 67 can be with the I/ shown in Fig. 1 O circuit 60 is configured with identical.
A kind of semiconductor system includes the first semiconductor devices and the second semiconductor devices, and the first semiconductor devices is configured For output command/address signal, the second semiconductor devices is configured as the combination according to command/address signal come in refresh operation Output data in the read operation of period, is configured as extracting error message from data, is configured as during refresh operation Error message is stored in the second semiconductor devices in write operation, and is configured as according to error message with other ground Location replaces row address and column address for selecting the vicious data of tool.
Wherein, error message is the failed storage unit with the retention time shorter than the retention time of normal memory cell Positional information.
Wherein, write operation is the operation for recovering calibrated data, and the calibrated data read behaviour by correcting The mistakes of the data exported in work is obtained.
Wherein, the second semiconductor devices includes：Command process circuit, is configured as decoding command/address signal To produce activation signal, write signal, read signal, precharging signal and refresh signal, and it is configured as based on refreshing letter Number come produce the refresh address sequentially counted and correction address；Address generator circuit, is configured as in read operation or write-in Command/address signal decoded in operation to produce row address and column address, and be configured as in refresh operation from Refresh address and correction address produce row address and column address；Memory block, is configured as producing in the read operation of refresh operation Raw error pulse signal, if the data stored in the memory cell chosen according to the combination of row address and column address have mistake By mistake, then error pulse signal is enabled, and memory block is configured as the mistake of the correction data in the write operation of refresh operation Miss calibrated data and error message being stored therein in；And repair control circuit, it is configured as being based on bursts of error Signal produces row repair signal and row repair signal.
Wherein, memory block is based on row repair signal and row repair signal and gone using error message to be replaced with other addresses Address and column address.
Wherein, precharging signal is made after the predetermined amount of time time point when refresh signal is enabled Energy.
Wherein, command process circuit includes：Command decoder, is configured as decoding command/address signal producing Raw activation signal, refresh signal, internal precharge signals, internal write signal and internal read signal；Delay sets circuit, quilt It is configured to postpone refreshing reading signal, refreshing write signal and refreshing preliminary filling telecommunications that refresh signal is sequentially enabled to produce Number；Logic circuit, is configured as producing precharging signal if internal precharge signals or refreshing precharging signal are enabled, It is configured as producing write signal if internal write signal or refreshing write signal are enabled, and if be configured as interior Portion reads signal or refreshing reading signal is enabled then to produce and reads signal；And control circuit, it is configured as based on refreshing letter Number come produce the refresh address sequentially counted and correction address.
Wherein, delay setting circuit includes：First delay circuit, is configured as refresh signal postponing for the first time delay Signal is read to produce to refresh based on refresh signal；Second delay circuit, is configured as refreshing and reads signal delay second Time delay is to produce refreshing write signal based on refresh signal；And the 3rd delay circuit, it is configured as that write-in will be refreshed The time delay of signal delay the 3rd is to produce refreshing precharging signal based on refresh signal.
Wherein, control circuit includes：Count signal occur circuit, be configured as produce count signal, count signal from It is enabled after the predetermined amount of time that time point when refresh signal is enabled starts；Counter, is configured as based on counting letter Number the refresh address of counting is produced, and be configured as producing counting controling signal, if whole bits of refresh address It is counted, then counting controling signal is enabled；And correction address generator circuit, it is configured as producing based on counting controling signal The correction address of livelihood number.
Wherein, correction address generator circuit is with being configured as producing the correction that sequentially counts based on counting controling signal Location.
Wherein, address generator circuit includes：Circuit occurs for row address, is configured as based on write signal and reads signal, Command/address signal is decoded to produce row address or output refresh address and be used as row address；And column address occurs Circuit, is configured as based on write signal and reads signal, command/address signal is decoded to produce column address or defeated Go out to correct address as column address.
Wherein, memory block includes：Memory bank, is configured as being extracted in read operation according to row address and column address The error message of the data stored in the memory cell for combining and choosing, is configured as the mistake of correction data with will be calibrated Data storage is in memory bank, and is configured as error message being stored in parity elements；First fuse circuit, quilt If being configured to the combination for the memory cell that there is row address selection there is mistake, capable reparation is exported based on row repair signal Signal；First repairs circuit, is configured as including each reparation wordline base in multiple reparation wordline, the multiple reparation wordline Selected in bank selection signal according to row repair signal；Second fuse circuit, if being configured as column address has choosing The combination of the memory cell in the presence of mistake is selected, then row repair signal is exported based on row repair signal；And second repair circuit, It is configured as including each being repaiied based on bank selection signal according to row in multiple reparation bit lines, the multiple reparation bit line Complex signal is selected.
Wherein, multiple fuse cells are each included in the first fuse circuit and the second fuse circuit.
As described above, semiconductor system in accordance with an embodiment of the present disclosure can be corrected with short during refresh operation Retention time memory cell in the mistake of data that stores, to prevent error in data.In addition, in accordance with an embodiment of the present disclosure Semiconductor system can replace the failed storage unit with the small retention time with reparation unit during refresh operation.
The second semiconductor devices or semiconductor system described referring to figs. 1 to Figure 11 can apply to include storage system The electronic system of system, graphics system, computing system, mobile system etc..For example, as shown in Figure 12, according to the electronics of embodiment System 1000 can include data storage circuit 1001, Memory Controller 1002, buffer storage 1003 and input/output (I/O) interface 1004.
According to the control signal produced from Memory Controller 1002, data storage circuit 1001 can be stored from memory The data that controller 1002 is exported, or the data of storage can be read and exported to Memory Controller 1002.Data storage Circuit 1001 can be included in the second semiconductor devices 2, the second semiconductor devices 4 shown in Fig. 6 or Figure 11 shown in Fig. 1 The second shown semiconductor devices 6.Even if data storage circuit 1001 remains to keep its storage when can be interrupted including its power supply The nonvolatile memory for the data deposited.Nonvolatile memory can for flash memory (such as NOR type flash memory or NAND type flash memory), phase change random access memory devices (PRAM), resistive random access memory (RRAM), spinning Move square random access memory (STTRAM), magnetic RAM (MRAM) etc..
Memory Controller 1002 can be received via I/O interfaces 1004 from external equipment (for example, host device) output Order, and can to from the order that host device is exported decoded with control enter data into data storage circuit 1001 or the operation in buffer storage 1003 or it will be stored in data storage circuit 1001 or buffer storage 1003 The operation of data output.Memory Controller 1002 can be including shown in the first semiconductor devices 1 shown in Fig. 1, Fig. 6 The first semiconductor devices 5 shown in first semiconductor devices 3 or Figure 11.Although Figure 12 illustrates memory control with individual module Device 1002 processed, but Memory Controller 1002, which can include one, to be used to control the data being made up of nonvolatile memory to store up Deposit the controller of circuit 1001 and the control of another buffer storage 1003 being made up of for control volatile memory Device.
Buffer storage 1003 can temporarily store the data handled by Memory Controller 1002.That is, buffer-stored Device 1003 can temporarily store the data exported from data storage circuit 1001 or input to data storage circuit 1001 Data.Buffer storage 1003 can store the data exported from Memory Controller 1002 according to control signal.Buffering is deposited Reservoir 1003 can read the data of storage and export to Memory Controller 1002.Buffer storage 1003 can be included such as The volatile memory of dynamic random access memory (DRAM), mobile DRAM or static RAM (SRAM).
I/O interfaces 1004 can physically and electrically externally connected equipment be (that is, main by Memory Controller 1002 Machine).Therefore, Memory Controller 1002 can receive the control supplied from external equipment (that is, main frame) via I/O interfaces 1004 Signal processed and data, and can give outer by the data output produced from Memory Controller 1002 via I/O interfaces 1004 Portion's equipment (that is, main frame).That is, electronic system 1000 can be via I/O interfaces 1004 and main-machine communication.I/O interfaces 1004 can With including various interface protocols (such as USB (USB), multimedia card (MMC), periphery component interconnection-quick (PCI- E), Serial Attached SCSI (SAS) (SAS), serial AT annexes (SATA), parallel AT annexes (PATA), small computer system interface (SCSI), enhanced gadget interface (ESDI) and integrated drive electronics (IDE)) in any one.
Electronic system 1000 may be used as the additional storage equipment or external storage device of main frame.Electronic system 1000 can be with It is (micro- including solid-state disk (SSD), USB storage, secure digital (SD) card, mini secure digital (mSD) card, miniature secure digital Type SD) it is card, secure digital Large Copacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded many Media card (eMMC), compact flash (CF) card etc..

Claims (27)

1. a kind of semiconductor system, including：
First semiconductor devices, is configured as exporting command/address signal；And
Second semiconductor devices, is configured as in the read operation during refresh operation according to the combination of command/address signal Carry out output data, be configured as extracting error message from data, and be configured as in the write operation during refresh operation Carry out the mistake of correction data using error message, by calibrated data storage in the second semiconductor devices and by mistake Information is stored in the second semiconductor devices.
2. the system as claimed in claim 1, wherein, error message is the positional information of following failed storage unit：It is described to lose Imitating memory cell has the retention time shorter than the retention time of normal memory cell.
3. the system as claimed in claim 1, wherein, write operation is the operation for recovering calibrated data, calibrated number Obtained according to by being corrected to the wrong data exported in read operation.
4. the system as claimed in claim 1, wherein, the second semiconductor devices includes：
Command process circuit, is configured as decoding command/address signal producing activation signal, write signal, reading Signal, precharging signal and refresh signal, and be configured as producing the refresh address sequentially counted based on refresh signal With correction address；
Address generator circuit, is configured as in read operation or write operation decoding command/address signal producing Row address and column address, and be configured as in refresh operation producing row address and row ground from refresh address and correction address Location；And
In memory block, the memory cell for being configured as extracting the combination according to row address and column address in read operation and choosing The error message of the data of storage, be configured as correction data mistake with by calibrated data storage wherein, and by It is configured to error message being stored in parity elements.
5. system as claimed in claim 4, wherein, precharging signal is time point when refresh signal is enabled It is enabled after predetermined amount of time.
6. system as claimed in claim 4, wherein, command process circuit includes：
Command decoder, is configured as decoding command/address signal producing activation signal, refresh signal, inside in advance Charging signals, internal write signal and internal read signal；
Delay sets circuit, is configured as postponing refreshing reading signal, the refreshing write-in that refresh signal is sequentially enabled to produce Signal and refreshing precharging signal；
Logic circuit, is configured as if internal precharge signals or refreshes generation preliminary filling telecommunications if precharging signal is enabled Number, be configured as if internal write signal or refresh write signal is produced if write signal is enabled, and be configured as Fruit internal read signal or refreshing reading signal are enabled then to produce and read signal；And
Circuit is controlled, is configured as producing the refresh address sequentially counted and correction address based on refresh signal.
7. system as claimed in claim 6, wherein, delay setting circuit includes：
First delay circuit, is configured as refresh signal postponing for the first time delay, to produce refreshing based on refresh signal Read signal；
Second delay circuit, is configured as refreshing and reads the time delay of signal delay second, to be produced based on refresh signal Refresh write signal；And
3rd delay circuit, is configured as that write signal the 3rd time delay of delay will be refreshed, to produce based on refresh signal Refresh precharging signal.
8. system as claimed in claim 6, wherein, control circuit includes：
Circuit occurs for count signal, is configured as producing count signal, time of the count signal when being enabled from refresh signal It is enabled after the predetermined amount of time that point starts；
Counter, is configured as producing the refresh address of counting based on count signal, and is configured as producing tally control Signal, if whole bits of refresh address are counted, counting controling signal is enabled；And
Address generator circuit is corrected, is configured as producing the correction address of counting based on counting controling signal.
9. system as claimed in claim 8, wherein, correction address generator circuit is configured as producing based on counting controling signal The raw correction address sequentially counted.
10. system as claimed in claim 4, wherein, address generator circuit includes：
Circuit occurs for row address, is configured as based on write signal and reads signal, command/address signal is decoded to produce Raw row address or output refresh address are used as row address；And
Circuit occurs for column address, is configured as based on write signal and reads signal, command/address signal is decoded to produce Raw column address or output calibration address are used as column address.
11. system as claimed in claim 4, wherein, memory block includes：
Line control circuit, is configured as being selected according to row address based on the bank selection signal being enabled in refresh operation Activate to selecting property a wordline in wordline；
Row control circuit, is configured as being selected to be connected to the wordline that is activated according to column address based on bank selection signal Memory cell, the data for being configured as storing from memory cell extract error message, are configured with error message and come school The mistake of correction data is so that calibrated data storage in the memory unit, and to be configured as error message being stored in odd even In verification unit；And
Cell array, is configured as including being connected to the memory cell of wordline and parity elements.
12. system as claimed in claim 11, wherein, row control circuit includes：
Error-Correcting Circuit, is configured as extracting from the data being connected on the memory bank line of memory cell based on signal is read Error message, be configured with error message come correction data mistake with by calibrated data output to global lines, quilt It is configured to write signal and memory bank line will be given with the wrong data output being corrected, and is configured as mistake Information output is to parity line；And
Sensing amplifier, is configured as sensing and amplifies and be connected on the memory bank line for the memory cell chosen by column address Data, by the data storage of amplification in sensing amplifier, and be configured as the error message on parity line It is stored in the parity elements chosen by column address.
13. system as claimed in claim 12, wherein, Error-Correcting Circuit includes：
Pulse signal generation circuit, is configured as producing write pulse signal based on write signal and is produced based on signal is read Read pulse signal；
Latch cicuit, is configured as based on write pulse signal or reads pulse signal come the data on latched memory banks line to produce Raw internal data, and believed based on pulse signal is read to latch the error message on parity line with producing even-odd check Number；
Code generating circuit is compiled, is configured as sensing the logic level of internal data to produce error code including error message and strange Even parity check code, and output parity signal are used as parity check code；
Data link, is configured as giving memory bank line by the data output in global lines based on write pulse signal；And
Even-odd check repeater, is configured as exporting parity check code to parity line based on write pulse signal.
14. a kind of semiconductor system, including：
First semiconductor devices, is configured as exporting command/address signal；And
Second semiconductor devices, is configured as in the read operation during the first refresh operation according to command/address signal Combination carrys out output data, is configured as extracting the error message of data so that error message is stored in the second semiconductor devices, And be configured as being corrected according to error message in the write operation during the second refresh operation in the memory cell chosen The mistake of the data of storage, by calibrated data storage in the second semiconductor devices.
15. system as claimed in claim 14, wherein, the first refresh operation is sequentially performed with the second refresh operation.
16. system as claimed in claim 14, wherein, error message is the positional information of following failed storage unit：It is described Failed storage unit has the retention time shorter than the retention time of normal memory cell.
17. system as claimed in claim 14, wherein, write operation is the operation for recovering calibrated data, calibrated Wrong data that data are exported by correcting in read operation and obtain.
18. system as claimed in claim 14, wherein, the second semiconductor devices includes：
Command process circuit, is configured as decoding command/address signal producing activation signal, write signal, reading Signal, precharging signal and refresh signal, are configured as producing the refresh address sequentially counted and school based on refresh signal Positive address, and be configured as producing the control signal being enabled in the second refresh operation；
Address generator circuit, is configured as in read operation or write operation decoding command/address signal producing Row address and column address, are configured as in the first refresh operation producing row address and row ground from refresh address and correction address Location, and it is configured as exporting the destination address including error message based on control signal as row address；
Memory block, is configured as producing error pulse signal in the read operation of the first refresh operation, if according to row address Combination with column address and there is mistake in the data that are stored in the memory cell chosen, then error pulse signal is enabled, by with The mistake of the correction data in the write operation of the second refresh operation is set to, and is configured as error message being stored in storage Qu Zhong；And
Error message storage circuit, is configured as that row address is saved as into destination address based on error pulse signal, and It is configured as exporting destination address based on control signal.
19. system as claimed in claim 18, wherein, precharging signal is time point when refresh signal is enabled Predetermined amount of time after be enabled.
20. system as claimed in claim 18, wherein, command process circuit includes：
Command decoder, is configured as decoding command/address signal producing activation signal, refresh signal, inside in advance Charging signals, internal write signal and internal read signal, and be configured as producing brush again based on internal refresh signal New signal；
Delay sets circuit, is configured as postponing refresh signal producing the refreshing sequentially enabled reading signal, refreshing write-in Signal and refreshing precharging signal；
Logic circuit, is configured as if internal precharge signals or refreshes generation preliminary filling telecommunications if precharging signal is enabled Number, be configured as if internal write signal or refresh write signal is produced if write signal is enabled, and be configured as Fruit internal read signal or refreshing reading signal are enabled then to produce and read signal；
Circuit is controlled, is configured as producing the refresh address sequentially counted and correction address based on refresh signal, and by It is configured to control signal and refreshes precharging signal to produce the internal refresh signal of enable；And
Circuit occurs for control signal, is configured as producing control signal, if whole bits of correction address are counted, controls Signal processed is enabled.
21. system as claimed in claim 20, wherein, delay setting circuit includes：
First delay circuit, is configured as refresh signal postponing for the first time delay, to produce refreshing based on refresh signal Read signal；
Second delay circuit, is configured as refreshing and reads the time delay of signal delay second, to be produced based on refresh signal Refresh write signal；And
3rd delay circuit, is configured as that write signal the 3rd time delay of delay will be refreshed, to produce based on refresh signal Refresh precharging signal.
22. system as claimed in claim 20, wherein, control circuit includes：
Refresh control circuit, is configured as producing after the predetermined amount of time time point when refresh signal is enabled The count signal being enabled, and be configured as producing the internal refresh of enable based on control signal and refreshing precharging signal Signal；
Counter, is configured as producing the refresh address of counting based on count signal, and is configured as producing tally control Signal, if whole bits of refresh address are counted, counting controling signal is enabled；And
Address generator circuit is corrected, is configured as producing the correction address of counting based on counting controling signal.
23. the system as claimed in claim 22, wherein, correction address generator circuit be configured as based on counting controling signal come Produce the correction address sequentially counted.
24. system as claimed in claim 18, wherein, address generator circuit includes：
Circuit occurs for row address, is configured as based on write signal and reads signal, command/address signal is decoded to produce Raw row address or output refresh address are as row address, and are configured as exporting destination address conduct based on control signal Row address；And
Circuit occurs for column address, is configured as based on write signal and reads signal, command/address signal is decoded to produce Raw column address or output calibration address are used as column address.
25. system as claimed in claim 18, wherein, memory block includes：
Line control circuit, is configured as based on the bank selection being enabled during the first refresh operation and the second refresh operation Signal and a wordline in wordline is optionally activated according to row address；
Row control circuit, is configured as being selected to be connected to depositing for selected word line according to column address based on bank selection signal Storage unit, the data for being configured as storing from memory cell extract error message, are configured with error message to correct Calibrated data storage in the memory unit, to be configured as error message being stored in even-odd check list by the mistake of data In member, and it is configured as producing the error pulse signal being then enabled if there is the mistake of data；And
Cell array, is configured as including being connected to the memory cell of wordline and parity elements.
26. system as claimed in claim 25, wherein, row control circuit includes：
Error-Correcting Circuit, is configured as extracting from the data being connected on the memory bank line of memory cell based on signal is read Error message, be configured with error message come correction data mistake with by calibrated data output to global lines, quilt Be configured to the data output that its mistake is corrected by write signal and give memory bank line, be configured as by error message export to Parity line, and it is configured as the wrong then output error pulse signal if there is data；And
Sensing amplifier, is configured as sensing and amplifies and be connected on the memory bank line for the memory cell chosen by column address Data so that the data storage of amplification wherein, and to be configured as the error message on parity line being stored in and passes through Column address and in the parity elements chosen.
27. system as claimed in claim 26, wherein, Error-Correcting Circuit includes：
Pulse signal generation circuit, is configured as producing write pulse signal based on write signal and produces reading based on signal is read Take pulse signal；
Latch cicuit, is configured as based on write pulse signal or reads pulse signal come the data on latched memory banks line to produce Raw internal data, and believed based on pulse signal is read to latch the error message on parity line with producing even-odd check Number；
Code generating circuit is compiled, is configured as sensing the logic level of internal data to produce error code including error message and strange Even parity check code, and output parity signal are used as parity check code；
Data link, is configured as giving memory bank line by the data output in global lines based on write pulse signal；
Even-odd check repeater, is configured as exporting parity check code to parity line based on write pulse signal；With And
Circuit occurs for bursts of error, if at least one being configured as in error code is enabled, based on reading pulse signal To produce error pulse signal.
CN201610509570.2A 2016-01-05 2016-06-30 Semiconductor system Active CN106941011B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160001232A KR20170082066A (en) 2016-01-05 2016-01-05 Semiconductor system
KR10-2016-0001232 2016-01-05

Publications (2)

Publication Number Publication Date
CN106941011A true CN106941011A (en) 2017-07-11
CN106941011B CN106941011B (en) 2020-10-16

Family

ID=59235590

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610509570.2A Active CN106941011B (en) 2016-01-05 2016-06-30 Semiconductor system

Country Status (3)

Country Link
US (1) US9990251B2 (en)
KR (1) KR20170082066A (en)
CN (1) CN106941011B (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109840161A (en) * 2017-11-24 2019-06-04 爱思开海力士有限公司 Scrub the method for mistake and the semiconductor module using this method
CN109935272A (en) * 2017-12-19 2019-06-25 爱思开海力士有限公司 Semiconductor devices and semiconductor system including it
CN109933453A (en) * 2017-12-15 2019-06-25 爱思开海力士有限公司 Error correcting method and the semiconductor devices for using it
CN109949852A (en) * 2017-12-20 2019-06-28 爱思开海力士有限公司 Semiconductor devices and semiconductor system including the semiconductor devices
CN110377453A (en) * 2018-04-12 2019-10-25 三星电子株式会社 Semiconductor memory system and storage system including semiconductor memory system
CN110415752A (en) * 2018-04-30 2019-11-05 爱思开海力士有限公司 For controlling the Memory Controller of refresh operation and including its storage system
CN110413544A (en) * 2018-04-27 2019-11-05 爱思开海力士有限公司 Semiconductor devices
CN110459251A (en) * 2018-05-08 2019-11-15 爱思开海力士有限公司 Semiconductor devices
CN111354413A (en) * 2018-12-24 2020-06-30 爱思开海力士有限公司 Semiconductor device and semiconductor system having training function
CN111435601A (en) * 2019-01-15 2020-07-21 爱思开海力士有限公司 Command generating method and semiconductor device related to command generating method
CN111666176A (en) * 2019-03-05 2020-09-15 爱思开海力士有限公司 Semiconductor device with a plurality of transistors
CN113157632A (en) * 2020-01-07 2021-07-23 爱思开海力士有限公司 In-memory processing device
CN113393890A (en) * 2020-03-11 2021-09-14 美光科技公司 Error checking and erasing for semiconductor memory device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104461986A (en) * 2015-01-10 2015-03-25 广东省农业机械试验鉴定站 Signal processing system for universal agricultural machine detection interface
JP2018156715A (en) * 2017-03-21 2018-10-04 東芝メモリ株式会社 Semiconductor memory
KR20190033387A (en) * 2017-09-21 2019-03-29 에스케이하이닉스 주식회사 Memory system and operating method thereof
KR102407184B1 (en) * 2017-10-31 2022-06-10 에스케이하이닉스 주식회사 Semiconductor memory apparatus and semiconductor system including the same
KR102533232B1 (en) 2017-11-13 2023-05-16 삼성전자주식회사 Memory device having global line groups which data input and output units are different from each other
KR20190068198A (en) * 2017-12-08 2019-06-18 에스케이하이닉스 주식회사 Memory device and test method thereof
KR102394727B1 (en) * 2017-12-12 2022-05-09 에스케이하이닉스 주식회사 Semiconductor system
KR20210026487A (en) * 2019-08-30 2021-03-10 삼성전자주식회사 Method of controlling repair of volatile memory device and storage device performing the same
KR20210149445A (en) * 2020-06-02 2021-12-09 삼성전자주식회사 Memory module and method for operating memory module
TW202318426A (en) * 2021-09-17 2023-05-01 南韓商三星電子股份有限公司 Operation method of memory controller configured to control memory device
KR20240009222A (en) * 2022-07-13 2024-01-22 에스케이하이닉스 주식회사 Error correction code circuit and semiconductor apparatus including the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060282755A1 (en) * 2005-05-31 2006-12-14 Jong-Hoon Oh Random access memory having ECC
US20110138251A1 (en) * 2006-10-11 2011-06-09 Pawlowski J Thomas Memory system and method using partial ecc to achieve low power refresh and fast access to data
CN103247347A (en) * 2012-02-11 2013-08-14 三星电子株式会社 Method and system for providing smart memory architecture
CN104335187A (en) * 2012-03-21 2015-02-04 戴尔产品有限公司 Memory controller-independent memory sparing
CN104900270A (en) * 2014-03-06 2015-09-09 爱思开海力士有限公司 Semiconductor device and method of operating the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6853602B2 (en) * 2003-05-09 2005-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Hiding error detecting/correcting latency in dynamic random access memory (DRAM)
US8438344B2 (en) 2010-03-12 2013-05-07 Texas Instruments Incorporated Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
KR20140126220A (en) 2013-04-18 2014-10-30 삼성전자주식회사 Semiconductor memory device having separated ECC (Error Correcting Code) circuit
JP2014241057A (en) * 2013-06-12 2014-12-25 ソニー株式会社 Interface control circuit, memory system, and method of controlling interface control circuit
US9274888B2 (en) * 2013-11-15 2016-03-01 Qualcomm Incorporated Method and apparatus for multiple-bit DRAM error recovery
US20160026524A1 (en) * 2014-07-25 2016-01-28 Kabushiki Kaisha Toshiba Memory device
US9606851B2 (en) * 2015-02-02 2017-03-28 International Business Machines Corporation Error monitoring of a memory device containing embedded error correction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060282755A1 (en) * 2005-05-31 2006-12-14 Jong-Hoon Oh Random access memory having ECC
US20110138251A1 (en) * 2006-10-11 2011-06-09 Pawlowski J Thomas Memory system and method using partial ecc to achieve low power refresh and fast access to data
CN103247347A (en) * 2012-02-11 2013-08-14 三星电子株式会社 Method and system for providing smart memory architecture
CN104335187A (en) * 2012-03-21 2015-02-04 戴尔产品有限公司 Memory controller-independent memory sparing
CN104900270A (en) * 2014-03-06 2015-09-09 爱思开海力士有限公司 Semiconductor device and method of operating the same

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109840161A (en) * 2017-11-24 2019-06-04 爱思开海力士有限公司 Scrub the method for mistake and the semiconductor module using this method
CN109933453B (en) * 2017-12-15 2023-03-10 爱思开海力士有限公司 Error correction method and semiconductor device using the same
CN109933453A (en) * 2017-12-15 2019-06-25 爱思开海力士有限公司 Error correcting method and the semiconductor devices for using it
CN109935272A (en) * 2017-12-19 2019-06-25 爱思开海力士有限公司 Semiconductor devices and semiconductor system including it
CN109949852A (en) * 2017-12-20 2019-06-28 爱思开海力士有限公司 Semiconductor devices and semiconductor system including the semiconductor devices
CN109949852B (en) * 2017-12-20 2023-04-04 爱思开海力士有限公司 Semiconductor device and semiconductor system including the same
CN110377453A (en) * 2018-04-12 2019-10-25 三星电子株式会社 Semiconductor memory system and storage system including semiconductor memory system
CN110413544A (en) * 2018-04-27 2019-11-05 爱思开海力士有限公司 Semiconductor devices
CN110413544B (en) * 2018-04-27 2023-07-07 爱思开海力士有限公司 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
CN110415752A (en) * 2018-04-30 2019-11-05 爱思开海力士有限公司 For controlling the Memory Controller of refresh operation and including its storage system
CN110415752B (en) * 2018-04-30 2024-02-06 爱思开海力士有限公司 Memory controller for controlling refresh operation and memory system including the same
CN110459251A (en) * 2018-05-08 2019-11-15 爱思开海力士有限公司 Semiconductor devices
CN111354413A (en) * 2018-12-24 2020-06-30 爱思开海力士有限公司 Semiconductor device and semiconductor system having training function
CN111354413B (en) * 2018-12-24 2023-08-25 爱思开海力士有限公司 Semiconductor device and semiconductor system having training function
CN111435601A (en) * 2019-01-15 2020-07-21 爱思开海力士有限公司 Command generating method and semiconductor device related to command generating method
CN111435601B (en) * 2019-01-15 2023-08-25 爱思开海力士有限公司 Command generation method and semiconductor device related to the same
CN111666176A (en) * 2019-03-05 2020-09-15 爱思开海力士有限公司 Semiconductor device with a plurality of transistors
CN111666176B (en) * 2019-03-05 2023-09-05 爱思开海力士有限公司 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
CN113157632A (en) * 2020-01-07 2021-07-23 爱思开海力士有限公司 In-memory processing device
CN113157632B (en) * 2020-01-07 2024-04-30 爱思开海力士有限公司 In-memory processing device
CN113393890A (en) * 2020-03-11 2021-09-14 美光科技公司 Error checking and erasing for semiconductor memory device

Also Published As

Publication number Publication date
US20170192845A1 (en) 2017-07-06
CN106941011B (en) 2020-10-16
US9990251B2 (en) 2018-06-05
KR20170082066A (en) 2017-07-13

Similar Documents

Publication Publication Date Title
CN106941011A (en) Semiconductor system
US10108512B2 (en) Validation of memory on-die error correction code
US10062427B2 (en) Semiconductor memory device for controlling having different refresh operation periods for different sets of memory cells
CN103811076B (en) Memory module, storage system and its reading/writing method with it
CN108694097B (en) Method and apparatus for using multiple codebooks of programming data in different memory regions of a memory device
CN107924349A (en) Error checking and correction code on storage arrangement tube core
KR20180060524A (en) Memory system and operating method thereof
CN110097913A (en) Memory Controller and its operating method
CN108122587A (en) The erasure controller and semiconductor memory system of semiconductor memory system
US10803919B2 (en) Memory controller for controlling refresh operation and memory system including the same
US10096345B2 (en) Semiconductor devices
CN109542666A (en) For supporting the device and its test method of error correcting code
US11663140B2 (en) Methods of memory address verification and memory devices employing the same
CN107919160B (en) Method of testing cell array and semiconductor device performing the same
CN107103934A (en) Semiconductor devices and its driving method
CN108604167A (en) Technology for writing Z-operation
US20170286218A1 (en) Semiconductor devices, and semiconductor systems
US10579472B2 (en) Semiconductor devices
CN107039087A (en) ECC coding methods and DRAM for DRAM
CN113535460A (en) Data storage device and operation method thereof
CN115938444A (en) Memory device and operation method thereof
US10153028B2 (en) Semiconductor devices
US20170344422A1 (en) Semiconductor devices and semiconductor systems
US20180018219A1 (en) Semiconductor devices and semiconductor systems
US10599562B2 (en) Nonvolatile memory device configured to be accessed without block address and method of operating the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant