CN109932997B - Programmable logic controller kernel system - Google Patents
Programmable logic controller kernel system Download PDFInfo
- Publication number
- CN109932997B CN109932997B CN201910155771.0A CN201910155771A CN109932997B CN 109932997 B CN109932997 B CN 109932997B CN 201910155771 A CN201910155771 A CN 201910155771A CN 109932997 B CN109932997 B CN 109932997B
- Authority
- CN
- China
- Prior art keywords
- program
- user program
- unit
- pointer
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a programmable logic controller kernel system, which comprises a PLC kernel, wherein the PLC kernel comprises a communication processing unit, a program execution unit, a storage unit and a hardware driving interface; the communication processing unit is used for setting authority management, uploading and downloading user programs and uploading and downloading variables; the program execution unit is used for executing the user program; the storage unit is used for storing the user program and maintaining the operation result, and the operation result is obtained by executing the user program through the program execution unit; the hardware driving interface is used for refreshing the operation result to new hardware equipment through a preset hardware driving program; the effect is as follows: the functional characteristics of the PLC kernel are completely encapsulated and highly abstracted, code compiling by professionals is not needed, relevant hardware parameters are filled like an operation form, a program can be automatically generated, and the program is compiled and output to new hardware equipment to complete PLC development, so that the PLC function development efficiency is greatly improved, and the maintenance cost is reduced.
Description
Technical Field
The invention relates to the technical field of programmable logic controllers, in particular to a programmable logic controller kernel system.
Background
A Programmable Logic Controller (PLC) is a Controller widely used in an automatic control system, and has a hardware structure substantially the same as that of a microcomputer. Wherein, the Central Processing Unit (CPU) is the control center of the PLC. The PLC also has a PLC compiler for converting a serial automatic control program (hereinafter, referred to as a user program) described in a programming language into a machine code executable by the CPU, and the CPU is then able to execute each instruction in the control program.
However, in the prior art, to complete the development of the PLC, a professional technician is required to develop the PLC for a long time, which results in high development cost and slow development progress.
Disclosure of Invention
The invention aims to provide a programmable logic controller kernel system which reduces the cost of PLC development and reduces the dependence on professional technicians.
The technical scheme adopted by the embodiment of the invention is as follows: a programmable logic controller kernel system comprises a PLC kernel, wherein the PLC kernel comprises a communication processing unit, a program execution unit, a storage unit and a hardware driving interface;
the communication processing unit is used for setting authority management, uploading and downloading user programs and uploading and downloading variables;
the program execution unit is used for executing the user program;
the storage unit is used for storing the user program and maintaining an operation result, and the operation result is obtained by executing the user program through the program execution unit;
and the hardware driving interface is used for refreshing the operation result to new hardware equipment through a preset hardware driving program.
As a preferred technical solution of the present invention, the storage unit includes a user program memory unit, an I/O memory mapping unit, and a permanent storage unit;
the permanent storage unit is used for storing the user program;
the I/O memory mapping unit is used for keeping the operation result;
and the user program memory unit is used for reading and storing the user program from the permanent storage unit when the user program is executed, and simultaneously recording the memory address generated when each section of program in the user program is stored.
As a preferred technical solution of the present invention, the persistent storage unit specifically includes: a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, and a fifth memory cell;
the first memory unit is used for storing specification information of hardware equipment in a user program, namely the model of the controller, the size of a storage space, the number of I/O points and user permission information;
the second memory unit is used for storing variables in the user program, and the variables are divided into two types: one is a memory variable, and a hardware I/O point information table is not used; another variable is mapped with the hardware I/O point information table, and accessing the variable is accessing the hardware I/O point information table. The I/O information table of the hardware module, namely the mapping table of the number of hardware I/O points, each I/O point has alias that facilitates the use of user program, and the relation table between alias and hardware I/O is the I/O information table of the hardware module;
the third memory unit is used for reserving the user in the user program, so that the expansion and the use are convenient;
the fourth memory unit is used for storing code segment information of tasks with different priorities in the user program;
and the fifth memory unit is used for storing code segment information of an event processing task in the user program.
As a preferred technical solution of the present invention, the program execution unit includes a core processor, a code segment pointer, a data segment pointer, and an offset pointer;
when the user program is executed, the code segment pointer takes out the instruction of the corresponding code segment from the address of the offset pointer;
the core processor enters a corresponding execution task according to the instruction of the code segment, judges whether parameters exist in the instruction of the code segment, and judges whether the user program is finished if the parameters do not exist; if the instruction exists, the instruction operation is carried out according to the parameters, the address of the offset pointer is modified after the operation, and the execution of the user program is stopped and the recording of the task stopping mark and the time information is carried out after the last instruction is executed.
As a preferred technical solution of the present invention, when the core processor executes the user tasks, the tasks are switched according to the descending order of the priority tasks, and any priority task cannot be put into execution again within a preset time after being executed.
As a preferred technical solution of the present invention, when a task is switched, the core processor stores all values in a code segment pointer, a data segment pointer, and an offset pointer of a current task, and a stop task flag and time information in a preset address pointed by the code segment pointer.
As a preferred technical solution of the present invention, the data segment pointer includes a first data segment pointer and a second data segment pointer;
the first data segment pointer is used for pointing to a data segment related to hardware in the code segment pointer;
the second data segment pointer is used to point to a hardware-independent data segment in the code segment pointer.
By adopting the technical scheme, the method has the following advantages: according to the programmable logic controller kernel system provided by the invention, the functional characteristics of the PLC kernel are completely encapsulated and highly abstracted through the system, so that the PLC can be refreshed to new hardware equipment to complete the development of the PLC without knowing what the PLC is, and only the filling of a hardware driver is required, so that the development cost of the PLC is reduced, the dependence on professional technicians is reduced, and the development progress can be greatly improved.
Drawings
FIG. 1 is a schematic diagram of a system configuration according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for executing a user program according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a memory address in an embodiment of the invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific examples, which are used for illustrating the present invention and are not intended to limit the scope of the present invention.
Referring to fig. 1, a programmable logic controller core system includes a PLC core including a communication processing unit, a program execution unit, a storage unit, and a hardware driver interface.
The communication processing unit is used for setting authority management, uploading and downloading user programs and uploading and downloading variables.
Specifically, the communication processing unit communicates with the PLC compiler, and the user sets the password through the PLC compiler, and establishes the connection and has the corresponding authority only when the password matches.
The program execution unit is used for executing the user program.
Specifically, the program execution unit comprises a core processor, a code segment pointer, a data segment pointer and an offset pointer, wherein the data segment pointer comprises a first data segment pointer and a second data segment pointer;
the first data segment pointer is used for pointing to a data segment related to hardware in the code segment pointer;
the second data segment pointer is used to point to a hardware-independent data segment in the code segment pointer.
When the user program is executed, as shown in fig. 2, the code segment pointer fetches an instruction of a corresponding code segment from the address of the offset pointer;
the core processor enters a corresponding execution task according to the instruction of the code segment, judges whether parameters exist in the instruction of the code segment, and judges whether the user program is finished if the parameters do not exist; if the instruction exists, the instruction operation is carried out according to the parameters, the address of the offset pointer is modified after the operation, and the execution of the user program is stopped and the recording of the task stopping mark and the time information is carried out after the last instruction is executed.
That is to say, the execution process of the whole user program is to take out an instruction from the code segment pointer, then take out a parameter according to the instruction content, modify the value of the code segment pointer according to the parameter, stop the execution of the user program and record the stop task flag and the time information until the program of the code segment is executed to the last instruction, and when the program is judged to be finished, enter the task switching and save the running environment.
The storage unit is used for storing the user program and maintaining the operation result, and the operation result is obtained by executing the user program through the program execution unit.
Specifically, the storage unit includes a user program memory unit, an I/O memory mapping unit, and a permanent storage unit.
The permanent storage unit is used for storing the user program; wherein, the permanent memory cell specifically includes: a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, and a fifth memory cell;
the first memory unit is used for storing specification information and user permission information of hardware equipment in a user program;
the second memory unit is used for storing an information table of variables and hardware modules in a user program;
the third memory unit is used for reserving the user in the user program, so that the expansion and the use are convenient;
the fourth memory unit is used for storing code segment information of tasks with different priorities in the user program;
the fifth memory unit is used for storing code segment information of an event processing task in a user program; this exploits the ability to manage user programs in segments so that they support concurrent execution of multiple tasks.
The I/O memory mapping unit is used for keeping the operation result.
Specifically, when a PLC core executes a user program (i.e., a PLC program), it first obtains an intermediate instruction code, calls a process function corresponding to the instruction code according to the content of the instruction code, determines the number of parameters following an instruction and the bit width occupied by the parameters in the function call, accordingly, the PLC core completes the execution of the intermediate instruction, and stores the result of the instruction operation in the I/O memory mapping unit.
And the user program memory unit is used for reading and storing the user program from the permanent storage unit when the user program is executed, and simultaneously recording the memory address generated when each section of program in the user program is stored.
The structure of the memory address is shown in fig. 3, that is, the memory address is obtained by hashing each segment of program in the user program.
And the hardware driving interface is used for refreshing the operation result to new hardware equipment through a preset hardware driving program.
Specifically, the hardware driver is a series of interface functions, the interface functions are links between the PLC kernel and the hardware platform, the PLC kernel is linked with new hardware equipment through the hardware driver, and in order to enable the PLC kernel to normally operate, the development of the PLC can be completed only by filling in the appropriate hardware driver, so that the development cost of the PLC is reduced, the dependence on professional technicians is reduced, and the development progress can be greatly improved.
Through the embodiment, the functional characteristics of the PLC kernel are completely encapsulated and highly abstracted, so that the PLC kernel can be refreshed to new hardware equipment to complete the development of the PLC without knowing what the PLC is, and only a hardware driver and a specification description file are required to be filled, thereby reducing the cost of the PLC development, reducing the dependence on professional technicians and greatly improving the development progress.
It should be noted that, the specification description file is a file in an Execl format, and the specification description file can be generated only by filling a form according to the description in the form file, and then the specification description file is transmitted to the PLC core, which is equivalent to providing the specification description file.
Further, when the core processor executes the user tasks, task switching is performed according to descending order of the priority tasks, and any priority task cannot be put into execution again within preset time after being executed.
Specifically, the PLC core includes a 10ms interrupt, the priority of the user task is checked every 10ms, and after a high-priority task is executed, the user task cannot be executed again within 20ms, so that a low-priority task can be executed, that is, after each task is executed, the user task must wait for 20ms to be executed again to ensure that the low-priority task has an opportunity to be executed. For example, event task priority > task 0 priority > task 1 priority > task 2 priority > task 3 priority > task 4 priority in the priority list. And the PLC kernel only checks whether the task with higher priority than the PLC kernel can be executed or not when the PLC kernel is interrupted every 10ms, and searches from high to low according to the priority after the current task is executed to determine the next task to be executed.
Further, when the task is switched, the core processor stores all values in the code segment pointer, the data segment pointer and the offset pointer of the current task, and the stop task flag and the time information into a preset address pointed by the code segment pointer.
Specifically, after searching executable code segments, the PLC kernel directly puts the executable code segments into execution; if the executable code segment can not be found, the code stop scheduling mark and the stop scheduling time of the highest priority code are released, so that the code segment with the highest priority is put into execution, and the PLC kernel ensures that the priority cannot be discontinuous, namely when only one code segment exists, the priority of the code segment must be the highest; when there are two tasks, one of which is the highest priority and the other of which must be the next highest priority, it should be noted that the predetermined address, i.e. the position of the pointer to the code segment 0 in fig. 3, is set.
Finally, it should be noted that the above description is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (6)
1. The programmable logic controller kernel system is characterized by comprising a PLC kernel, wherein the PLC kernel comprises a communication processing unit, a program execution unit, a storage unit and a hardware driving interface;
the communication processing unit is used for setting authority management, uploading and downloading user programs and uploading and downloading variables;
the program execution unit is used for executing the user program;
the storage unit is used for storing the user program and maintaining an operation result, and the operation result is obtained by executing the user program through the program execution unit;
the hardware driving interface is used for refreshing the operation result to new hardware equipment through a preset hardware driving program;
the program execution unit comprises a core processor, a code segment pointer, a data segment pointer and an offset pointer;
when the user program is executed, the code segment pointer takes out the instruction of the corresponding code segment from the address of the offset pointer;
the core processor enters a corresponding execution task according to the instruction of the code segment, judges whether parameters exist in the instruction of the code segment, and judges whether the user program is finished if the parameters do not exist; if the instruction exists, the instruction operation is carried out according to the parameters, the address of the offset pointer is modified after the operation, and the execution of the user program is stopped and the recording of the task stopping mark and the time information is carried out after the last instruction is executed.
2. The programmable logic controller kernel system of claim 1, wherein said storage units comprise a user program memory unit, an I/O memory mapping unit, and a persistent storage unit;
the permanent storage unit is used for storing the user program;
the I/O memory mapping unit is used for keeping the operation result;
and the user program memory unit is used for reading and storing the user program from the permanent storage unit when the user program is executed, and simultaneously recording the memory address generated when each section of program in the user program is stored.
3. The programmable logic controller kernel system according to claim 2, wherein the persistent storage unit specifically comprises: a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, and a fifth memory cell;
the first memory unit is used for storing specification information and user permission information of hardware equipment in a user program;
the second memory unit is used for storing an information table of variables and hardware modules in a user program;
the third memory unit is used for reserving the user in the user program, so that the expansion and the use are convenient;
the fourth memory unit is used for storing code segment information of tasks with different priorities in the user program;
and the fifth memory unit is used for storing code segment information of an event processing task in the user program.
4. The PLC kernel system according to claim 1, wherein when the kernel processor executes the user tasks, the tasks are switched according to the descending order of the priority tasks, and any priority task cannot be put into execution again within a preset time after being executed.
5. The PLC core system of claim 4, wherein when a task is switched, the core processor stores all the values in the code segment pointer, the data segment pointer and the offset pointer of the current task and the stop task flag and the time information in the preset address pointed by the code segment pointer.
6. The programmable logic controller core system of claim 5, wherein the data segment pointer comprises a first data segment pointer and a second data segment pointer;
the first data segment pointer is used for pointing to a data segment related to hardware in the code segment pointer;
the second data segment pointer is used to point to a hardware-independent data segment in the code segment pointer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910155771.0A CN109932997B (en) | 2019-03-01 | 2019-03-01 | Programmable logic controller kernel system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910155771.0A CN109932997B (en) | 2019-03-01 | 2019-03-01 | Programmable logic controller kernel system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109932997A CN109932997A (en) | 2019-06-25 |
| CN109932997B true CN109932997B (en) | 2021-09-28 |
Family
ID=66986219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910155771.0A Active CN109932997B (en) | 2019-03-01 | 2019-03-01 | Programmable logic controller kernel system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109932997B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114363323A (en) * | 2022-01-06 | 2022-04-15 | 东莞市云雀科技有限公司 | Intelligent data uploading method for PLC |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218567A (en) * | 1996-03-13 | 1999-06-02 | 钻石多媒体系统公司 | Multiple parallel digital data stream channel controller architecture |
| CN103984603A (en) * | 2012-03-31 | 2014-08-13 | 华为技术有限公司 | Method and device for detecting memory unit |
| CN104898546A (en) * | 2015-05-06 | 2015-09-09 | 浙江中控研究院有限公司 | PLC (Programmable Logic Controller) on-line debugging system and method based on SOC (System On Chip) |
| CN106125664A (en) * | 2016-08-12 | 2016-11-16 | 绵阳市维博电子有限责任公司 | A kind of Embedded PLC control system |
| CN106843127A (en) * | 2017-02-28 | 2017-06-13 | 深圳市麦格米特控制技术有限公司 | A kind of Medium PLC system |
-
2019
- 2019-03-01 CN CN201910155771.0A patent/CN109932997B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218567A (en) * | 1996-03-13 | 1999-06-02 | 钻石多媒体系统公司 | Multiple parallel digital data stream channel controller architecture |
| CN103984603A (en) * | 2012-03-31 | 2014-08-13 | 华为技术有限公司 | Method and device for detecting memory unit |
| CN104898546A (en) * | 2015-05-06 | 2015-09-09 | 浙江中控研究院有限公司 | PLC (Programmable Logic Controller) on-line debugging system and method based on SOC (System On Chip) |
| CN106125664A (en) * | 2016-08-12 | 2016-11-16 | 绵阳市维博电子有限责任公司 | A kind of Embedded PLC control system |
| CN106843127A (en) * | 2017-02-28 | 2017-06-13 | 深圳市麦格米特控制技术有限公司 | A kind of Medium PLC system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109932997A (en) | 2019-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3712767B1 (en) | Control device | |
| CN110427258B (en) | Resource scheduling control method and device based on cloud platform | |
| EP2733613B1 (en) | Controller and program | |
| CN109117203A (en) | A kind of Android APP starting velocity optimization method and system | |
| CN103329102A (en) | Multiprocessor system | |
| CN106155730A (en) | Operating system loading method and device | |
| US9910418B2 (en) | Method and programming system for programming an automation component | |
| CN112650539A (en) | Dynamic link operation supporting method for heterogeneous many-core processor | |
| CN109932997B (en) | Programmable logic controller kernel system | |
| EP3252595A1 (en) | Method and device for running process | |
| CN117075930A (en) | Computing framework management system | |
| US8464016B2 (en) | Method and device for switching over in a memory for a control device | |
| JP7085305B2 (en) | Control system and control method | |
| EP0766156A1 (en) | Programmable logic controller | |
| WO2020075351A1 (en) | Control device | |
| TW201401169A (en) | Integrated-circuit radio | |
| CN115453967A (en) | Scheduling execution method of PLCopen single-axis motion control function block | |
| CN1287287C (en) | Method for realizing on-line renewing data based on control system | |
| JP2009009444A (en) | Programmable controller, programmable controller support apparatus, and programmable controller system | |
| CN100492299C (en) | Embedded software developing method and system | |
| US10936357B2 (en) | Semiconductor device | |
| CN111221535B (en) | Thread allocation method, server and computer readable storage medium | |
| CN117311990B (en) | Resource adjustment method and device, electronic equipment, storage medium and training platform | |
| CN113094170B (en) | Memory bus allocation method and terminal for 5G communication virtualization network element | |
| CN108776594B (en) | Software programming suitable for real-time control of processor and assembly linking method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |