CN109922341A - The advanced entropy coder implementation method of AVS2 and device - Google Patents
The advanced entropy coder implementation method of AVS2 and device Download PDFInfo
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- CN109922341A CN109922341A CN201711325015.5A CN201711325015A CN109922341A CN 109922341 A CN109922341 A CN 109922341A CN 201711325015 A CN201711325015 A CN 201711325015A CN 109922341 A CN109922341 A CN 109922341A
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Abstract
The present invention provides the advanced entropy coder implementation method of AVS2 and device.The encoder is mainly made of binarization block, context model module, arithmetic coding module.When carrying out advanced entropy coding, context model module is split into context model selecting module and context model update module, arithmetic coding module is split into coder state update module and bit generation module.Above-mentioned module uses flowing structure, improves entropy coder throughput.The method that context model directly uses register to store is realized, makes context model achieve the purpose that quickly to access, and reduce hard-wired complexity.Binarization block and the parallel processing of context model selecting module, context model update module and the parallel processing of coder state update module, improve the process performance of entropy coder.Data buffer storage is carried out using asynchronous FIFO in hardware circuit realization device and realizes that the cross clock domain of front stage module operates.
Description
Technical field
The present invention relates to a kind of advanced entropy coder implementation method of AVS2 and devices.
Background technique
AVS2 national standard is the standard of a new generation after AVS1, including three video, audio and system parts.AVS2
The target of Video coding is at least encoded than AVS1 under high definition or higher resolution while guaranteeing Subjective video quality
Performance improves 1 times.The advanced entropy coder of AVS2 is core coding module in AVS2 video coding system, mainly do not lose appoint
Compressed encoding is carried out to video sequence in the case where what information.
The advanced entropy coding of AVS2 is mainly made of binarization block, context model module, arithmetic coding module.In order to keep away
Exempt to introduce multiplication and division arithmetic in arithmetic coding process, AVS2 is transformed into pair operand from real number field during coding
Number field, the multiplication and division arithmetic of such real number field only need to can be completed by addition and subtraction in log-domain.Due to
Arithmetic coding module needs the corresponding probabilistic model of the numerical value, therefore context mould in the numerical value after coding binaryzation
Pattern block mainly adaptively goes to calculate corresponding syntactic element corresponding conditional probability when coding.
AVS2 entropy coder itself includes coding dependence closely, and video sequence is low to advanced entropy coder to be gulped down
When spitting rate output, the advanced Entropy Coder Design of AVS2 is simultaneously uncomplicated, but when high-throughput output, AVS2 video
Encoder just needs to optimize advanced entropy coder processing, reduces the scramble time of AVS2 entropy coder list bit coding, mentions
The coding throughput of high AVS2 entropy coder.
Summary of the invention
The purpose of the present invention is to provide a kind of advanced entropy coder implementation method of AVS2 and devices, make advanced entropy coder
Each clock cycle exports the encoding code stream of a bit, and then improves the throughput of binary encoding module.
The present invention provides a kind of advanced entropy coder of AVS2, is mainly compiled by binarization block, context model module, arithmetic
Code module composition；Binarization block is mainly to carry out binarization operation to the syntactic element for needing to carry out binarization operation；Up and down
Literary module mainly stores probability value corresponding to different syntactic element respective binary values；Entropy coding is completed to different grammer members
Plain binary value selects corresponding probabilistic model, then carries out compressed encoding to it.
The present invention provides a kind of advanced entropy coder implementation method of AVS2, entropy coder throughput is improved, by context
Model module splits into the context model selecting module and context model update module of functional independence, by arithmetic coding module
Split into the coder state update module and bit generation module of functional independence；Binarization block and context model select mould
Block parallel processing improves the processing capacity of entropy coder；Context model is accessed by the way of register, simplifies design
Complexity facilitates hardware realization, reaches quickly access purpose, and context model update is located parallel with coder state update module
Reason；Use asynchronous FIFO to buffer as front stage flowing water intermediate variable, realizes coding module Continually coding；It reduces on the whole high
Grade entropy coder handles the time required for every bit is encoded, and improves the process performance of entire entropy coder, enhanced encoder gulps down
Spit rate.
The present invention also provides a kind of advanced entropy coder devices of AVS2, for realizing the advanced entropy coding of AVS2 of the invention
Device implementation method, the realization device are 7 road hardware circuit realization devices.
Preferably, which is divided into following 7 parts:
Part 1 is that syntactic element inputs FIFO, and storage needs to carry out the syntactic element of entropy coding, can be directly using different
FIFO is walked to realize the modular circuit；
Part 2 is binaryzation and context model selecting module, which mainly completes syntactic element binaryzation and correspondence
The context model of binary value selects；
Part 3 is FIFO1, which is directly realized using asynchronous FIFO, the relevant parameter of different asynchronous FIFOs according to
Actual demand is selected；
Part 4 is that context model updates and coder state update module, the circuit store context using register
Model, convenient for the realization of hardware circuit；
Part 5 is FIFO2, which is directly realized using asynchronous FIFO, the relevant parameter of different asynchronous FIFOs according to
Actual demand is selected；
Part 6 is bit generation module, which is used for the generation of encoder output bit stream；
Part 7 is code stream output module, which realizes the code stream by single bit data of coding output according to actual demand
Bit wide carries out serioparallel exchange output.
Cached using asynchronous FIFO, front and back module can be made not interfere with each other independently of each other, avoid data because overflow, under
Loss of data caused by overflowing avoids the waste of clock cycle caused by front stage module interaction handshake, improves entropy coder
Process performance.
The advanced entropy coder of AVS2 proposed by the present invention, it is ensured that each clock cycle exports the coding code of a bit
Stream improves the throughput of binary encoding module.Meanwhile the coding module is easily understood, hardware design is easily achieved.
Detailed description of the invention
Fig. 1 is the basic schematic diagram of the advanced entropy coder of AVS2 according to the present invention；
Fig. 2 is the hardware circuit realization device figure of the advanced entropy coder of AVS2 according to the present invention.
Specific embodiment
Illustrate the principle of the present invention and illustrative embodiments with reference to the accompanying drawings.
As described above, AVS2 entropy coder itself includes coding dependence closely, in exploitation environment on an equal basis
In the case of, for demand high-throughput export when, the data dependency of AVS2 entropy coder itself make hardware design at
For a big bottleneck.In order to make AVS2 each clock cycle of advanced entropy coder export the encoding code stream of a bit, and then improve whole
The throughput of body coding module, the invention proposes a kind of advanced entropy coder implementation method of AVS2 and devices.
As depicted in figs. 1 and 2, the advanced entropy coder of AVS2 proposed by the present invention mainly includes binarization block, context
Model module, arithmetic coding module.Binarization block is completed to carry out binarization operation to the syntactic element for needing binarization operation.
Context model module stores the probabilistic model of numerical value after corresponding syntactic element binaryzation；It is high general after syntactic element binaryzation
When the probability of rate code stream and low probability code stream is equal, select probability model is not needed at this time, directly carries out bypass coding；Grammer member
When the probability of high probability code stream and low probability code stream is unequal after plain binaryzation, need select probability model at this time, directly into
Line discipline coding.The present invention is based on implementing below to hardware circuit, the process performance of entropy coder is improved, is being developed on an equal basis
Under environment, the throughput of enhanced encoder.
1. splitting arithmetic coding module
Just as previously outlined, AVS2 entropy coder itself includes coding dependence closely, leads to hardware flow
Water is designed to a big bottleneck.
In order to optimize the coding dependence inside AVS2 entropy coder, reduce ancillary cost in internal module coding etc.
To the time, hardware module grade flowing water being facilitated to design, the module of different function is subjected to deconsolidation process, each functions of modules is independent,
And flowing structure is used, improve the throughput of entropy coding.
Arithmetic coding module splits into the coder state update module and bit generation module of functional independence；By context
Module splits into context model selecting module and context model update module.
Module is split, the runing time of individual module is reduced, using flowing structure, improves the processing of entropy coder
Performance.
2. using register access context model
In order to save context model update need time, using register store probabilistic model by the way of, reach with
It deposits with taking the purpose updated at any time, and hardware realization is fairly simple, does not need additional logic and removes maintaining context model
It updates, avoids the waste of clock cycle caused by due to judging whether context has been updated.
3. internal module parallel processing
By functional independence, the module of correlation does not carry out parallel processing between each other.Serial processing mode is changed to simultaneously
Row processing mode reduces the runing time of half, so that the process performance of module is improved.
Binarization block and context model selecting module carry out parallel processing, context model update module and encoder
State update module carries out parallel processing.
4. being cached between module using asynchronous FIFO, stream treatment is done between each module
Intermediate variable between module is cached using asynchronous FIFO, is kept front and back module mutually indepedent, is independent of each other, side
Just the cross clock domain operation between module, can make front and back module carry out water operation at different frequencies.
The place of the advanced entropy coder of AVS2 can be improved under exploitation environment on an equal basis in 4 kinds of hardware configurations proposed by the present invention
Rationality energy, the throughput of enhanced encoder；Functional module is split, and shortens critical path depth inside individual module；Module carries out
Parallel processing；Front stage module intermediate variable is cached using asynchronous FIFO and does stream treatment；It is stored using register
Hereafter model；Hardware logic is easily understood, and hardware circuit is easily achieved, and design is simple regular.
As shown in Figure 1, carrying out binaryzation for the syntactic element for needing to carry out binaryzation.For not needing to carry out binaryzation
The syntactic element of operation, without binaryzation.
Above with reference to Detailed description of the invention implementation method of the invention, it is understood, however, that above description is only exemplary
's.Those skilled in the art can make various repair to the present invention under the premise without departing from the spirit and scope of the present invention
Change and modification.Protection scope of the present invention is limited by the accompanying claims.
Claims (8)
1. a kind of advanced entropy coder implementation method of AVS2, which is characterized in that the advanced entropy coder include binarization block, on
Hereafter model module, arithmetic coding module；The context model module is split into the context model selection of functional independence
Module and context model update module；The arithmetic coding module is split into the coder state update module of functional independence
With bit generation module；The binarization block and the context model selecting module parallel processing；The context model is more
New module and the coder state update module parallel processing.
2. the advanced entropy coder implementation method of AVS2 according to claim 1, which is characterized in that the context model is adopted
It is accessed with the mode of register.
3. the advanced entropy coder implementation method of AVS2 according to claim 1, which is characterized in that make the context model
Selecting module and the context model update module do stream treatment；Make the coder state update module and the bit
Generation module does stream treatment.
4. the advanced entropy coder implementation method of AVS2 according to claim 1, which is characterized in that use asynchronous FIFO as
Front stage flowing water intermediate variable buffering, realizes the asynchronous operation of front stage module；Make on the whole the advanced entropy coder each
Clock cycle exports the encoding code stream of a bit.
5. a kind of advanced entropy coder realization device of AVS2, which is characterized in that the encoder hardware circuit is divided into following 7 portions
Point:
Part 1 is that syntactic element inputs FIFO, and storage needs to carry out the syntactic element of entropy coding；
Part 2 is binaryzation and context model selecting module, which mainly completes syntactic element binaryzation and corresponding two-value
The context model of change value selects；
Part 3 is FIFO1；
Part 4 is that context model updates and coder state update module, the circuit store context model using register,
Convenient for the realization of hardware circuit；The binaryzation data that coder state update module exports part 2 are in corresponding context mould
It is calculated under type, updates intermediate variable, and corresponding variate-value is exported to next module；
Part 5 is FIFO2；
Part 6 is bit generation module, which is used for the generation of encoder output bit stream；
Part 7 is code stream output module, which realizes the code stream bit wide by single bit data of coding output according to actual demand
Carry out serioparallel exchange output.
6. the advanced entropy coder realization device of AVS2 according to claim 5, which is characterized in that the input of institute's syntax elements
FIFO, the FIFO1 and the FIFO2 realize that the relevant parameter of different asynchronous FIFOs is according to reality using asynchronous FIFO
Border demand is selected.
7. the advanced entropy coder realization device of AVS2 according to claim 5 or 6, which is characterized in that institute's syntax elements
FIFO is inputted, realizes the asynchronous operation of 1 front stage module of part；The intermediate variable of the FIFO1 storage section 2 simultaneously realizes part
2 with the asynchronous operation of part 4；The intermediate variable of the FIFO2 storage section 4 and the asynchronous operation for realizing part 4 Yu part 6.
8. the advanced entropy coder realization device of AVS2 according to claim 5 or 6, which is characterized in that it is for realizing root
According to the advanced entropy coder implementation method of AVS2 described in any one of Claims 1-4.
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| CN112911314A (en) * | 2021-01-14 | 2021-06-04 | 北京博雅慧视智能技术研究院有限公司 | Coding method of entropy coder and entropy coder |
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