CN109918256A - A kind of register testing method and system - Google Patents
A kind of register testing method and system Download PDFInfo
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- CN109918256A CN109918256A CN201910181369.XA CN201910181369A CN109918256A CN 109918256 A CN109918256 A CN 109918256A CN 201910181369 A CN201910181369 A CN 201910181369A CN 109918256 A CN109918256 A CN 109918256A
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Abstract
The present invention relates to chip register functional test technical fields, and in particular to a kind of register testing method and system.The register testing method is specifically includes the following steps: determining the bit field information of register and the attribute register information of each bit field being arranged；The register information of tested register is obtained, the register information includes the bit field information of register and the attribute register information of each bit field；According to the register information of acquisition, the attribute register of the tested each bit field of register is successively judged by the bit field of tested register；It is successively carried out and its test that respectively attribute register matches according to the bit field attribute register of tested register.The register testing system includes: bit field setup module, obtains module, judgment module and test module.The register testing method and system can realize automatic test to the specified register with a variety of attributes.
Description
Technical field
The present invention relates to chip register functional test technical fields, and in particular to a kind of register testing method and is
System.
Background technique
The realization of chip functions is completed by carrying out different configurations to register.During chip checking,
It is also a most important task that register verifying, which is most basic, and the correctness of register functions is to guarantee that chip functions are realized
Most basic premise.
Register is generally divided into readable writeable register, read-only register, and write-only register writes 1 clear 0 register.
It is general to be tested by the way of write-in, reading, comparison for readable writeable register.I.e. to register write
Enter fixed numbers or random number, read the register, write-in value and reading value are compared, it is no by test if consistent
It then tests and does not pass through.
It is general using mode is directly read for read-only register, test its readability.
Its writability is tested generally by the way of writing direct fixed value or random value for write-only register.
It is general using writing 1 to the register mask for writing 1 clear 0 register, it waits for a period of time, then read the deposit
Device judges whether mask is 0, passes through if it is 0 test, otherwise tests and do not pass through.
These test methods can only be tested for the register of standard, constantly be increased however as chip-scale, at
This requirement is increasingly stringenter, and in order to save register space, many registers have no longer been the deposits of simple above-mentioned attribute
Device, but different attribute is set by the different positions of register.Such as 32 bit registers, its low 16 are readable writeable
Attribute, its high 16 are to write 1 clear 0 attribute.Or 32 bit registers, although it is readable writeable, write-in is one corresponding
Function, reading another corresponding function to save space will should be that two registers that are read-only and only writing are made into
One register, if this register is written, reads, alignments are tested, the value of write-in and the value of reading must
It is so different, the result tested in this way is necessarily wrong.
Since this kind of register with a variety of attributes occurs, being badly in need of a kind of automatic test approach can be for having a variety of categories
The register of property is tested.
Summary of the invention
In order to solve the deficiencies in the prior art, the present invention provides a kind of register testing method and system, described
Register testing method and system can realize automatic test to the specified register with a variety of attributes.
The technical solution provided according to the present invention provides a kind of register testing method as the first aspect of the present invention,
The register testing method specifically includes the following steps:
S100: determining the bit field information of register and the attribute register information of each bit field is arranged；
S200: obtaining the register information of tested register, and the register information includes the bit field information of register and each
The attribute register information of a bit field；
S300: according to the register information of acquisition, the tested each bit field of register is successively judged by the bit field of tested register
Attribute register；
S400: it is successively carried out and its survey that respectively attribute register matches according to the bit field attribute register of tested register
Examination.
Further, the S100 specifically includes the following steps:
S110: the attribute register of the current tested bit field of setting and mask Mask value corresponding with the attribute；
S120: input reset test parameter；
S130: mask Mask value described in the reset test parameter and S110 is subjected to operation, to generate reset
Preset value；
S140: successively carrying out S110, S120 and S130 step to next bit field, until the register of all bit fields is arranged
Attribute, mask Mask value and reset preset value.
Further, wherein the attribute register reset values for also carrying out bit field before S300 after the S200 are compared and surveyed
Examination, the steps include:
The value deposited in each bit field in register is read, by its mask Mask corresponding with the attribute register of each bit field
Value carries out with operation, obtains reset test value, the reset test value is compared with preset value is resetted, if consistent
Reset values contrastive test passes through, and does not otherwise pass through.
Further, the S400 is specifically included:
S410: if currently the attribute register of tested bit field is readable writeable register, basic readwrite tests is carried out；
S420: if currently the attribute register of tested bit field is read-only register, read-only test is carried out；
S430: if currently the attribute register of tested bit field is write-only register, test is only write；
S440: it if currently the attribute register of tested bit field is to write 1 clear 0 register, carries out writing 1 clear 0 test；
S450: if currently the attribute register of tested bit field is reserved bit, without test.
Further, basic readwrite tests described in the S410 specifically includes:
S411: reading the value deposited in register, and the value deposited in current tested bit field is carried out the first modification logical operation, institute
State the operation result of the first modification logical operation are as follows: equal with the value on the current tested each bit in bit field corresponding position
" 1 " in binary system；Currently tested bit field is currently tested bit field
S412: being sequentially written in register by bit for the numerical value obtained by the first modification logical operation, current at this time tested
The value that each bit is deposited in bit field is " 1 "；
S413: the value deposited in register is read again, whether is the value that each bit is deposited in the current tested bit field of judgement
It is " 1 ", it is current tested if judging result indicates that the value that each bit is deposited in current tested bit field is not " 1 "
It is incorrect that bit field deposits function；
S414: reading the value deposited in register, carries out the second modification to the value deposited in read current tested bit field and patrols
Collect operation, the operation result of the second modification logical operation are as follows: with the currently tested each bit in bit field corresponding position
" 0 " in the equal binary system of value on position；
S415: being sequentially written in register by bit for the numerical value obtained by the second modification logical operation, current at this time tested
The value that each bit is deposited in bit field is " 0 "；
S416: reading the value deposited in register, judge each bit is deposited in current tested bit field value whether be
" 0 ", currently tested bit field deposit function is correct if being " 0 " if the value that each bit is deposited in current tested bit field, no
It is then incorrect.
Further, it also needs to carry out random read-write test after basic readwrite tests process in the S410, carry out
The test to match with its attribute register is carried out to next bit field after random read-write test.
The random read-write test is specifically includes the following steps: to covering in the attribute register information of current tested bit field
Code Mask value carries out repeatedly being revised as 1 or 0 operation at random.
As second aspect of the present invention, a kind of register testing system is provided, the register testing system includes:
Bit field setup module, the setup module are used to determine the bit field information of register and the register category of each bit field are arranged
Property information；
Module is obtained, the register information for obtaining module and being used to obtain tested register, the register information includes posting
The bit field information of storage and the attribute register information of each bit field；
Judgment module, the judgment module are used for the register information according to acquisition, successively judge by the bit field of tested register
The attribute register of the tested each bit field of register；
Test module, the test module according to the bit field attribute register of tested register for successively carrying out respectively posting with it
The test that storage attribute matches.
Further, the bit field setup module include: attribute setting unit, it is corresponding with the attribute setting unit
Mask Mask value setting unit and reset preset value generation unit；The attribute setting unit is for being arranged currently tested bit field
Attribute register；
The mask Mask value setting unit is tested the corresponding mask Mask of the attribute register of bit field with current for be arranged
Value；The reset preset value generation unit for inputting reset test parameter, and by the reset test parameter inputted with covering
The mask Mask value being arranged in code Mask value setting unit carries out with operation, to generate reset preset value.
Further, the register testing system further include: reset values test module, the reset values test module packet
It includes:
Bit field value reading unit, the bit field value reading unit are used to be successively read the value of each bit field；
Reset values comparing unit, the reset values comparing unit are read with each bit field by the bit field value reading unit
Value carries out with operation with its respective mask Mask value, obtains reset test value, by the reset test value and resets default
Value is compared, and reset values contrastive test passes through if consistent, does not otherwise pass through.
Further, the test module includes: basic readwrite tests unit, random read-write test cell, read-only test
Unit only writes test cell and writes 1 clear 0 test cell.
From described above as can be seen that one's duty invents the register testing method and system provided, compared with prior art
Have following advantages: the present invention include it is readable it is writeable, read-only, only write, write 1 clear 0 any a variety of attributes, any position (different attribute
Corresponding position can be overlapped) automated testing method, can realize automatic test to the specified register with a variety of attributes.When
When different bit fields in register have different attribute registers, each bit field accurately can be judged by bit field by the present invention
Attribute register function correctness, avoid accidentally survey situation.
Detailed description of the invention
Fig. 1 is the flow chart of first aspect present invention.
Fig. 2 is the specific flow chart of S100 in first aspect present invention.
Fig. 3 is basic readwrite tests flow chart in first aspect present invention.
Fig. 4 is the system structure diagram of second aspect of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
As the first aspect of the present invention, a kind of register testing method is provided, as shown in Fig. 1 ~ Fig. 3, the storage is surveyed
Method for testing specifically includes the following steps:
S100: determining the bit field information of register and the attribute register information of each bit field is arranged, the attribute register letter
Breath includes attribute register, mask Mask value corresponding with the attribute；
S200: obtaining the register information of tested register, and the register information includes the bit field information of register and each
The attribute register information of a bit field；
S300: according to the register information of acquisition, the tested each bit field of register is successively judged by the bit field of tested register
Attribute register；
S400: it is successively carried out and its survey that respectively attribute register matches according to the bit field attribute register of tested register
Examination.
It is understood that when the different bit fields in register have different attribute registers, it can by the present invention
The correctness that the attribute register function of each bit field is accurately judged by bit field avoids accidentally surveying situation.
Wherein, for the S100 specifically includes the following steps:
S110: the attribute register of the current tested bit field of setting and mask Mask value corresponding with the attribute；
S120: input reset test parameter；
S130: mask Mask value described in the reset test parameter and S110 is subjected to operation, to generate reset
Preset value；
S140: successively carrying out S110, S120 and S130 step to next bit field, until the register of all bit fields is arranged
Attribute, mask Mask value and reset preset value.
Specific embodiment are as follows: there are one 32 registers, its address is 0x00000000, the 0 ~ 7 of the register
Bit be the first bit field, 8 ~ 15 bits be the second bit field, 16 ~ 23 bits be third bit field, 24 ~ 31 bits the 4th
Domain；The attribute register of first bit field is readable writeable attribute, and the attribute register of second bit field is read only attribute,
The attribute register of the third bit field is reserved bit (invalid bit), and the attribute register of the 4th bit field is to write 1 clear 0 to belong to
Property.
The address of each bit field of register is disposed as 0x00000000, and the attribute register of the first bit field is set as
Readable writeable, the mask Mask value of the first bit field is set as 0xFF, and the reset values of the mask Mask value are set as (reset test
Parameter & 0xFF)；
The attribute register of second bit field is set as read-only, and the mask Mask value of the second bit field is set as 0xFF00, the mask
The reset values of Mask value are set as (reset test parameter & 0xFF00)；
The attribute register of 4th bit field is set as writing 1 clear 0, and the mask Mask value of the second bit field is set as 0xFF000000, institute
The reset values for stating mask Mask value are set as (reset test parameter & 0xFF000000).
In order to which whether determination is normal to register reset function, wherein also carrying out bit field before S300 after the S200
Attribute register reset values contrastive test, the steps include:
The value of each bit field is successively read by bit field, by its mask Mask value corresponding with the attribute register of each bit field into
Row with operation obtains reset test value, and the reset test value is compared with preset value is resetted, is resetted if consistent
Value contrastive test passes through, and does not otherwise pass through.
The S400 is specifically included:
S410: if currently the attribute register of tested bit field is readable writeable register, basic readwrite tests, the base are carried out
This readwrite tests specifically includes:
S411: reading the value deposited in register, and the value deposited in current tested bit field is carried out the first modification logical operation, institute
State the operation result of the first modification logical operation are as follows: equal with the value on the current tested each bit in bit field corresponding position
" 1 " in binary system；By taking above-mentioned specific embodiment as an example, the value that 32 bit registers are read is 0x00000000, currently quilt
Location domain is least-significant byte, and currently tested bit field mask mask value is set as 0xFF, then the first modification logical operation is
{(0x00000000) & ~(0xFF)} | { (0xFFFFFFFF) & (0xFF)}。
S412: the numerical value obtained by the first modification logical operation is sequentially written in register by bit, currently at this time
The value that each bit is deposited in tested bit field is " 1 ", by taking above-mentioned specific embodiment as an example, by the first modification logic
Operation obtains and the value deposited in register is written are as follows: 0x000000FF.
S413: reading again the value deposited in register, judges the value that each bit is deposited in current tested bit field
It whether is " 1 ", it is current if judging result indicates that the value that each bit is deposited in current tested bit field is not " 1 "
Tested bit field deposit function is incorrect；By taking above-mentioned specific embodiment as an example, will first it be posted in the current tested bit field read again
The value deposited carries out decision logic operation, and currently tested bit field mask mask value is set as 0xFF, the decision logic arithmetic expression are as follows:
{ (0x000000FF) (0xFF) }, and the result of the decision logic operation is tested bit field mask mask value with current
Whether 0xFF is compared identical, if identical, the value that each bit is deposited in current tested bit field is " 1 ".
S414: reading the value deposited in register, carries out second to the value deposited in read current tested bit field and repairs
Change logical operation, the operation result of the second modification logical operation are as follows: each with the currently tested bit field corresponding position
" 0 " in the equal binary system of value on bit；It is current to be tested the value deposited in bit field by taking above-mentioned specific embodiment as an example are as follows:
0x000000FF, currently tested bit field mask mask value is set as 0xFF, then the second modification logical operation is { (0x000000FF)
& ~(0xFF)} | {(0x00000000) & (0xFF)}。
S415: the numerical value obtained by the second modification logical operation is sequentially written in register by bit, currently at this time
The value that each bit is deposited in tested bit field is " 0 "；By taking above-mentioned specific embodiment as an example, by the second modification logic fortune
The value deposited in first bit field after calculation are as follows: 0x00000000.
S416: the value deposited in register is read, whether is the value that each bit is deposited in the current tested bit field of judgement
It is " 0 ", is currently being tested bit field deposit function just if being " 0 " if the value that each bit is deposited in current tested bit field
Really, otherwise incorrect.By taking above-mentioned specific embodiment as an example, first the value deposited in the current tested bit field read again is carried out
Decision logic operation, currently tested bit field mask mask value is set as 0xFF, the decision logic arithmetic expression are as follows:
{ (0x00000000) & (0xFF) }, and the result of the decision logic operation is compared with 0x00000000 whether phase
Together, if identical, the value that each bit is deposited in current tested bit field is " 0 ".
It also needs to carry out random read-write test after basic readwrite tests process in the S410, is carrying out random read-write survey
The test to match with its attribute register is carried out to next bit field after examination.
The random read-write test is specifically includes the following steps: to covering in the attribute register information of current tested bit field
Code Mask value carries out repeatedly being revised as 1 or 0 operation at random, and repeats the random read-write and test 100 times.
S420: if currently the attribute register of tested bit field is read-only register, read-only test, the read-only survey are carried out
Examination specifically includes: reading the attribute register information of current tested bit field, judges covering in read attribute register information
Whether code Mask value is correct, and the register functions of current tested bit field are normal if correct, deposit with it to next bit field
The test that device attribute matches；Otherwise abnormal.
S430: if currently the attribute register of tested bit field is write-only register, test is only write, described is write survey
Examination specifically includes: the attribute register information of the current tested bit field of modification, will be in the attribute register information of current tested bit field
Mask Mask value be revised as 1 or 0；Modified bit field attribute register information is written in the bit field；If write-in is correct
The register functions of the bit field are normal, and the test to match with its attribute register is carried out to next bit field；Otherwise abnormal.
S440: it if currently the attribute register of tested bit field is to write 1 clear 0 register, carries out writing 1 clear 0 test；Modification is worked as
Mask Mask value in the attribute register information of current tested bit field is revised as by the attribute register information of preceding tested bit field
1；Modified bit field attribute register information is written in the bit field, and is waited for a period of time；Read current tested bit field
Attribute register information judges whether the mask Mask value in read attribute register information is 0, if the mask Mask
Value is that 0 test passes through, and the test to match with its attribute register is carried out to next bit field；Otherwise do not pass through；
S450: if currently the attribute register of tested bit field is reserved bit, without test.
It is understood that successively being carried out and its respective attribute register according to the bit field attribute register of tested register
The test to match can accurately judge whether the register functions of each bit field in tested register are normal.
As a second aspect of the invention, a kind of register testing system is provided, as shown in figure 4, the register testing
System includes:
Bit field setup module 100, the setup module are used to determine the bit field information of register and the deposit of each bit field are arranged
Device attribute information；
Obtain module 200, the register information for obtaining module 200 and being used to obtain tested register, the register information
The attribute register information of bit field information and each bit field including register；
Judgment module 300, the judgment module 300 are used for according to the register information of acquisition, by tested register bit field according to
The secondary attribute register for judging the tested each bit field of register；
Test module 400, the test module 400 is used to successively carry out according to the bit field attribute register of tested register and it
The test that respective attribute register matches.
It is understood that when the different bit fields in register have different attribute registers, it can by the present invention
The correctness that the attribute register function of each bit field is accurately judged by bit field avoids accidentally surveying situation.
The bit field setup module 100 includes: attribute setting unit 110, corresponding with the attribute setting unit 110
Mask Mask value setting unit 120 and reset preset value generation unit 130；The attribute setting unit 110 is worked as being arranged
The attribute register of preceding tested bit field；The mask Mask value setting unit 120 is used to be arranged the deposit with current tested bit field
The corresponding mask Mask value of device attribute；The reset preset value generation unit 130 is for inputting reset test parameter, and by institute
The reset test parameter of input carries out with operation with the mask Mask value being arranged in mask Mask value setting unit 120, from
And it generates and resets preset value.
The register testing system further include: reset values test module 500, the reset values test module 500 include:
Bit field value reading unit 510, the bit field value reading unit 510 are used to be successively read the value of each bit field；
Reset values comparing unit 520, the reset values comparing unit 520 by the bit field value reading unit 510 it is read with
The value of each bit field and its respective mask Mask value carry out with operation, reset test value are obtained, by the reset test value
It is compared with preset value is resetted, reset values contrastive test passes through if consistent, does not otherwise pass through.
The test module 400 includes: basic readwrite tests unit 410, random read-write test cell 420, read-only test
Unit 430 only writes test cell 440 and writes 1 clear 0 test cell 450；
The basic readwrite tests unit 410 is used to modify the attribute register information of current tested bit field, by current measured position
Mask Mask value in the attribute register information in domain is revised as 1；Then modified bit field attribute register information is written
In the bit field；The attribute register information for reading current tested bit field, judges the mask in read attribute register information
Whether Mask value is 1, tests if not being 1 if the mask Mask value and does not pass through；Read the attribute register of current tested bit field
Information judges whether the mask Mask value in read attribute register information is 1, if the mask Mask value is not 1
Test does not pass through；Modified bit field attribute register information is written in the bit field；Read the register of current tested bit field
Attribute information judges whether the mask Mask value in read attribute register information is 0, if the mask Mask value is 0
Then test passes through, and does not otherwise pass through.
The random read-write test cell 420, for the mask in the attribute register information to current tested bit field
Mask value carries out repeatedly being revised as 1 or 0 operation at random, and repeats the random read-write and test 100 times.
The read-only test cell 430 judges read for reading the attribute register information of current tested bit field
Whether the mask Mask value in attribute register information is correct, and the register functions of current tested bit field are normal if correct, right
Next bit field carries out the test to match with its attribute register；Otherwise abnormal.
Described is write test cell 440, for modifying the attribute register information of current tested bit field, by current measured position
Mask Mask value in the attribute register information in domain is revised as 1 or 0；It should by the write-in of modified bit field attribute register information
In bit field；The register functions of the bit field are normal if write-in is correct, match with its attribute register to next bit field
Test；Otherwise abnormal.
It is described to write 1 clear 0 test cell 450, if currently the attribute register of tested bit field is to write 1 clear 0 register, carry out
Write 1 clear 0 test；The attribute register information of the current tested bit field of modification, will be in the attribute register information of current tested bit field
Mask Mask value be revised as 1；Modified bit field attribute register information is written in the bit field, and is waited for a period of time；
The attribute register information for reading current tested bit field judges whether is mask Mask value in read attribute register information
It is 0, tests and pass through if the mask Mask value is 0, the test to match with its attribute register is carried out to next bit field；It is no
Do not pass through then.
It is understood that the test module 400 according to the bit field attribute register of tested register successively carry out with
Its test that respectively attribute register matches can accurately judge the register functions of each bit field in tested register
It is whether normal.
It should be understood by those ordinary skilled in the art that: the above is only a specific embodiment of the present invention, and
It is not used in the limitation present invention, all any modification, equivalent substitution, improvement and etc. within purport of the invention, done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of register testing method, which is characterized in that the register testing method specifically includes the following steps:
S100: determining the bit field information of register and the attribute register information of each bit field is arranged；
S200: obtaining the register information of tested register, and the register information includes the bit field information of register and each
The attribute register information of a bit field；
S300: according to the register information of acquisition, the tested each bit field of register is successively judged by the bit field of tested register
Attribute register；
S400: it is successively carried out and its survey that respectively attribute register matches according to the bit field attribute register of tested register
Examination.
2. register testing method as described in claim 1, which is characterized in that the S100 specifically includes the following steps:
S110: the attribute register of the current tested bit field of setting and mask Mask value corresponding with the attribute；
S120: input reset test parameter；
S130: mask Mask value described in the reset test parameter and S110 is subjected to operation, to generate reset
Preset value；
S140: successively carrying out S110, S120 and S130 step to next bit field, until the register of all bit fields is arranged
Attribute, mask Mask value and reset preset value.
3. register testing method as claimed in claim 2, which is characterized in that wherein before S300 after the S200 also
The attribute register reset values contrastive test for carrying out bit field, the steps include:
The value deposited in each bit field in register is read, by its mask Mask corresponding with the attribute register of each bit field
Value carries out with operation, obtains reset test value, the reset test value is compared with preset value is resetted, if consistent
Reset values contrastive test passes through, and does not otherwise pass through.
4. register testing method as described in claim 1, which is characterized in that the S400 is specifically included:
S410: if currently the attribute register of tested bit field is readable writeable register, basic readwrite tests is carried out；
S420: if currently the attribute register of tested bit field is read-only register, read-only test is carried out；
S430: if currently the attribute register of tested bit field is write-only register, test is only write；
S440: it if currently the attribute register of tested bit field is to write 1 clear 0 register, carries out writing 1 clear 0 test；
S450: if currently the attribute register of tested bit field is reserved bit, reserved bit is without test.
5. register testing method as claimed in claim 4, which is characterized in that basic readwrite tests tool described in the S410
Body includes:
S411: reading the value deposited in register, and the value deposited in current tested bit field is carried out the first modification logical operation, institute
State the operation result of the first modification logical operation are as follows: equal with the value on the current tested each bit in bit field corresponding position
" 1 " in binary system；
S412: will be sequentially written in register by the first obtained numerical value of modification logical operation by bit, at this time current quilt
The value that each bit is deposited in location domain is " 1 "；
S413: reading again the value deposited in register and be currently tested bit field, judges each bit institute in currently tested bit field
Whether the value of deposit is " 1 ", if the value that judging result indicates that each bit is deposited in current tested bit field is not
" 1 " then currently tested bit field deposit function is incorrect；
S414: reading the value deposited in register, carries out the second modification to the value deposited in read current tested bit field and patrols
Collect operation, the operation result of the second modification logical operation are as follows: with the currently tested each bit in bit field corresponding position
" 0 " in the equal binary system of value on position；
S415: being sequentially written in register by bit for the numerical value obtained by the second modification logical operation, current at this time tested
The value that each bit is deposited in bit field is " 0 "；
S416: reading the value deposited in register, judge each bit is deposited in current tested bit field value whether be
" 0 ", currently tested bit field deposit function is correct if being " 0 " if the value that each bit is deposited in current tested bit field, no
It is then incorrect.
6. register testing method as claimed in claim 4, which is characterized in that the basic readwrite tests process in the S410
It also needs to carry out random read-write test later, next bit field is carried out and its attribute register phase after carrying out random read-write test
Matched test；
The random read-write test is specifically includes the following steps: to the mask in the attribute register information of current tested bit field
Mask value carries out repeatedly being revised as 1 or 0 operation at random.
7. a kind of register testing system, which is characterized in that the register testing system includes:
Bit field setup module (100), the setup module are used to determine the bit field information of register and posting for each bit field are arranged
Storage attribute information；
It obtains module (200), the register information for obtaining module (200) and being used to obtain tested register, the register
Information includes the bit field information of register and the attribute register information of each bit field；
Judgment module (300), the judgment module (300) is used for the register information according to acquisition, by the position of tested register
Domain successively judges the attribute register of the tested each bit field of register；
Test module (400), the test module (400) according to the bit field attribute register of tested register for successively carrying out
With its test that respectively attribute register matches.
8. register testing system as claimed in claim 7, which is characterized in that the bit field setup module (100) includes: to belong to
Property setting unit (110), mask Mask value setting unit (120) corresponding with attribute setting unit (110) and multiple
Position preset value generation unit (130)；The attribute setting unit (110) is used to be arranged the attribute register of current tested bit field；
The mask Mask value setting unit (120) is tested the corresponding mask of the attribute register of bit field with current for be arranged
Mask value；The reset preset value generation unit (130) is joined for inputting reset test parameter, and by the reset test inputted
Number carries out with operation with the mask Mask value being arranged in mask Mask value setting unit (120), so that it is default to generate reset
Value.
9. register testing system as claimed in claim 7, which is characterized in that the register testing system further include: multiple
Place value test module (500), the reset values test module (500) include:
Bit field value reading unit (510), the bit field value reading unit (510) are used to be successively read the value of each bit field；
Reset values comparing unit (520), the reset values comparing unit (520) are read the bit field value reading unit (510)
It is taking to carry out with operation with each bit field value and its respective mask Mask value, reset test value is obtained, by the reset
Test value is compared with preset value is resetted, and reset values contrastive test passes through if consistent, does not otherwise pass through.
10. register testing system as claimed in claim 7, which is characterized in that the test module (400) includes: basic
Readwrite tests unit (410), random read-write test cell (420), read-only test cell (430), only write test cell (440) and
Write 1 clear 0 test cell (450).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN111861858A (en) * | 2020-07-10 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Method and device for starting image compression function verification and related equipment |
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Application publication date: 20190621 |