CN109917277A - Virtual measuring method, device, equipment and storage medium - Google Patents
Virtual measuring method, device, equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of virtual measuring method, device, equipment and storage mediums, this method includes that current test pattern is arranged as virtual test mode, in the virtual test mode, associated control signal is taken over and tested by virtual test register；Transmission clock is generated by the virtual test register, test link is carried out and loads；After test link loads, capture clock is generated by the virtual test register, carries out the capture of test result, this programme improves chip testing efficiency, has saved hardware resource.
Description
Technical field
The present embodiments relate to computer technologies more particularly to a kind of virtual measuring method, device, equipment and storage to be situated between
Matter.
Background technique
Current SOC(System on Chip, system on chip) chip is usually made of the embedded identical kernel of dozens of,
According to the different SOC of application program can also include multiple duplications high-speed physical body for mold and external storage, memory it
Between communication.
As the scale of chip is gradually expanded, the sum of the scanning channel for test greatly exceeds reusable and scans
The quantity of the functional GPIO in channel.In the prior art, usual way is the pin for increasing dedicated ATPG and using, but meeting
It is additional to increase chip area and packing cost, and as the design of this exclusive test pin is developed in the encapsulation of 2.5D and 3D
Degree of difficulty is higher and higher.
Summary of the invention
The embodiment of the present invention provides a kind of virtual measuring method, device, equipment and storage medium, improves chip testing effect
Rate has saved hardware resource.
In a first aspect, the embodiment of the invention provides a kind of virtual measuring methods, this method comprises:
It is that virtual test mode is connect in the virtual test mode by virtual test register that current test pattern, which is arranged,
Manage and test associated control signal；
Transmission clock is generated by the virtual test register, test link is carried out and loads；
After test link loads, capture clock is generated by the virtual test register, carries out catching for test result
It obtains.
Second aspect, the embodiment of the invention also provides a kind of virtual test device, which includes:
Mode setting module is that virtual test mode passes through in the virtual test mode for current test pattern to be arranged
Associated control signal is taken over and tested to virtual test register；
Clock control module is transmitted, for generating transmission clock by the virtual test register, test link is carried out and loads；
Clock control module is captured, for generating and capturing by the virtual test register after test link loads
Clock carries out the capture of test result.
The third aspect, the embodiment of the invention also provides a kind of equipment, which includes:
One or more processors；
Storage device, for storing one or more programs,
When one or more of programs are executed by one or more of processors, so that one or more of processors are real
Virtual measuring method described in the existing embodiment of the present invention.
Fourth aspect, it is described the embodiment of the invention also provides a kind of storage medium comprising computer executable instructions
Computer executable instructions as computer processor when being executed for executing virtual measuring method described in the embodiment of the present invention.
In the embodiment of the present invention, it is virtual test mode that current test pattern, which is arranged, in the virtual test mode, is led to
It crosses virtual test register adapter tube and tests associated control signal, transmission clock is generated by the virtual test register,
It carries out test link to load, after test link loads, capture clock is generated by the virtual test register, is carried out
The capture of test result, this programme are not necessarily to design exclusive test pin for chip, reduce hardware development cost, save
Hardware resource is converted to serial test input simultaneously simultaneously because carrying out control signal imitation using virtual test register
Capable close beta channel, improves chip testing efficiency.
Detailed description of the invention
Fig. 1 is a kind of flow chart of virtual measuring method provided in an embodiment of the present invention；
Fig. 2 is the flow chart of another virtual measuring method provided in an embodiment of the present invention；
Fig. 3 is the flow chart of another virtual measuring method provided in an embodiment of the present invention；
Fig. 4 is the flow chart of another virtual measuring method provided in an embodiment of the present invention；
Fig. 5 is the flow chart of another virtual measuring method provided in an embodiment of the present invention；
Fig. 6 is a kind of structural block diagram of virtual test device provided in an embodiment of the present invention；
Fig. 7 is a kind of structural schematic diagram of equipment provided in an embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this
Locate described specific embodiment and is used only for explaining the embodiment of the present invention, rather than the restriction to the embodiment of the present invention.In addition also
It should be noted that only parts related to embodiments of the present invention are shown rather than entire infrastructure for ease of description, in attached drawing.
Fig. 1 is a kind of flow chart of virtual measuring method provided in an embodiment of the present invention, and the present embodiment is applicable to virtually
Test, this method can be executed by equipment such as computer, be specifically comprised the following steps:
Step S101, it is that virtual test mode passes through virtual test in the virtual test mode that current test pattern, which is arranged,
Associated control signal is taken over and tested to register.
Chip is in factory or using needing to carry out dependence test preceding to ensure that chip functions meet design requirement.The application side
In case, associated control signal is simulated and tests by virtual test register to carry out functional test to chip, cancellation is adopted
With original in such a way that pin is tested, which can encapsulate design in SOC(System on
Chip, systems-on-a-chip) on piece is to substitute original test pin.
Illustratively, by taking jtag boundary sweep test as an example, the test pin definition that each chip needs to be separately provided is such as
Under:
TCK: test clock input；
TDI: test data input, data input JTAG mouthfuls by TDI；
TDO: test data output, data are exported by TDO from JTAG mouthfuls；
TMS: test pattern selection, TMS are used to be arranged JTAG mouthfuls in certain specific test pattern.
TRST: test reset, input pin, low level are effective.
Wherein, JTAG(Joint Test Action Group, combined testing action group) it is a kind of international standard test
Agreement is mainly used for chip interior test, and present most of high-grade devices all support JTAG protocol, such as DSP, FPGA device,
Basic principle are as follows: define a TAP(Test Access Port, test access port in device inside) pass through dedicated JTAG
Testing tool tests internal node, is tested by virtual test register mode in this programme, jtag test
Multiple devices are allowed to be cascaded to form a JTAG chain by jtag interface, each device is tested in realization respectively.
Wherein, boundary scan technique refers to increases a shift register cell on the input and output pin close to chip,
Since these shift register cells are distributed on the boundary of chip, therefore it is called boundary scan register.When chip is in test
When state, boundary scan register the input and output of chip and periphery can be isolated, and pass through these boundary scan register lists
Observation and control to chip input/output signal may be implemented in member.It, can be by being attached thereto for the input pin of chip
Boundary scan register unit signal (data) is loaded into the pin, for the output pin of chip, can by with
Connected boundary scan register " capture " pin output.Boundary scan register improves a kind of convenient and fast as a result,
Mode is to carry out chip testing, wherein the boundary scan register of chip input and output pin can connect in chip
Surrounding forms a boundary scan chain, and general chip can all provide several independent boundary scan chains and be used to completely be surveyed
Examination.
In the present solution, the pin that outputs and inputs of i.e. chip connects by virtual test register adapter tube TCK, TMS, TRST
It is connected on the virtual test register of setting, virtual test register is used to bearing test input signal, test output signal, control
Signal processed and transmission clock, the generation selection signal for capturing clock, only need setting TDI and TDO for SOC.Wherein, and
Associated control signal is tested illustratively such as ATPG(Automatic Test Pattern Generation, test automatically to
Amount generates) control signal, wherein one object in known state of ATPG test direction applies determining input stimulus, capture
Its output response determined is simultaneously compared with the expectation of " ideal " response, and then judges measurand with the presence or absence of fault test
Mode.
Step S102, transmission clock is generated by the virtual test register, carries out test link and loads.
Wherein, which loads for carrying out test link.It is driven by TCK, each clock cycle is connected
Data register between TDI and TDO will receive a data from TDI, while export a data by TDO, it is assumed that when
The length of the data register of preceding tested chip is 4, then after 4 tck clock periods, original 4 in the data register
Data will export out from TDO, and test data (such as ATPG test vector) is accordingly loaded.
Step S103, after test link loads, capture clock is generated by the virtual test register, is carried out
The capture of test result.
Wherein, capture clock is used to carry out the capture of test result.In the rising edge of tck clock, it is tested chip output
Signal on pin is " trapped " in corresponding data register.
By above scheme it is found that it is virtual test mode that current test pattern, which is arranged, in the virtual test mode, lead to
It crosses the control of virtual test register and tests associated signal；Transmission clock is generated by the virtual test register, is carried out
Link is tested to load；After test link loads, capture clock is generated by the virtual test register, is tested
As a result capture, this programme improve chip testing efficiency, have saved hardware resource.
Fig. 2 is the flow chart of another virtual measuring method provided in an embodiment of the present invention, optionally, the transmission clock
It is generated according to tck signal, test mode signal, transmission enable signal, idle state signal and fictitious order signal.It is described virtual
Scratchpad register, which is also used to be arranged, obtains the delay of transmission clock by idle state signal.As shown in Fig. 2, technical solution is specifically such as
Under:
Step S201, it is that virtual test mode passes through virtual test in the virtual test mode that current test pattern, which is arranged,
Associated control signal is taken over and tested to register.
Step S202, by the virtual test register analog tck signal, test mode signal, transmission enable signal,
Idle state signal and fictitious order signal generate transmission clock, carry out test link and load.
Illustratively, tck signal is test clock (JTAG clock), and mode is that (high level is virtual to test mode signal
Test pattern), clock_en is transmission enable signal (high level is transmission), and Run_Test Idel is idle state signal,
The rising edge of the signal carrys out temporal delay certain time (the configurable setting of specific delay time value) and obtains transmission clock, is transmitting
Rising edge clock triggers the loading of loop test vector (cycle_vector), which passes through TDR(scan_in)
Characterization.
Step S203, after test link loads, capture clock is generated by the virtual test register, is carried out
The capture of test result.
By above scheme it is found that generating transmission clock by the virtual test register, carries out test link and load, mention
High testing efficiency, reduces test pin convenient for chip design, encapsulation.
Fig. 3 is the flow chart of another virtual measuring method provided in an embodiment of the present invention, optionally, the capture clock
It is generated according to tck signal, test mode signal, capture enable signal, idle state signal and fictitious order signal.Such as Fig. 3 institute
Show, technical solution is specific as follows:
Step S301, it is that virtual test mode passes through virtual test in the virtual test mode that current test pattern, which is arranged,
Associated control signal is taken over and tested to register.
Step S302, by the virtual test register analog tck signal, test mode signal, transmission enable signal,
Idle state signal and fictitious order signal generate transmission clock, carry out test link and load.
Step S303, after test link loads, pass through the virtual test register analog tck signal, test
Mode signal, capture enable signal, idle state signal and fictitious order signal generate capture clock, carry out catching for test result
It obtains.
It is similar with the transmission generating mode of clock, it is logical state virtual test register analog tck signal, test mode signal,
Enable signal, idle state signal and fictitious order signal are captured to generate capture clock, which believes in TCK
Number, test mode signal, capture enable signal, idle state signal and fictitious order signal rising edge temporarily trigger.
By above scheme it is found that being made by the virtual test register analog tck signal, test mode signal, capture
Energy signal, idle state signal and fictitious order signal generate the capture that capture clock carries out test result, improve test and imitate
Rate reduces test pin convenient for chip design, encapsulation.
Fig. 4 is the flow chart of another virtual measuring method provided in an embodiment of the present invention, optionally, described to be tested
It includes: the loading for carrying out the first test link that link, which loads,；Correspondingly, after the capture for carrying out test result, further includes: into
Row second tests the loading of link, after the second test link loads, is generated and is captured by the virtual test register
Clock carries out the capture of test result.After the second test link loads, caught by virtual test register generation
Clock is obtained, after the capture for carrying out test result, further includes: data refresh clock is generated by the virtual test register.
As shown in figure 4, technical solution is specific as follows:
Step S401, it is that virtual test mode passes through virtual test in the virtual test mode that current test pattern, which is arranged,
Associated control signal is taken over and tested to register.
Step S402, by the virtual test register analog tck signal, test mode signal, transmission enable signal,
Idle state signal and fictitious order signal generate transmission clock, carry out the loading of the first test link.
Step S403, after test link loads, pass through the virtual test register analog tck signal, test
Mode signal, capture enable signal, idle state signal and fictitious order signal generate capture clock, carry out catching for test result
It obtains.
Step S404, the loading for carrying out the second test link, after the second test link loads, by described virtual
Scratchpad register generates capture clock, carries out the capture of test result.
Wherein, the first test link and the second test link are respectively used to the different function or different cores of test chip
Piece, the capture for passing through a plurality of loading for testing link and carrying out test result, improves testing efficiency, saves the testing time.
Step S405, data refresh clock is generated by the virtual test register.
Wherein, which is driven by TCK rising edge, and the data in data register will be loaded into accordingly
Chip pin on.
By above scheme it is found that being tested by the series connection to a plurality of test link, testing efficiency is improved, test is saved
Time.
Fig. 5 is the flow chart of another virtual measuring method provided in an embodiment of the present invention, optionally, in the current survey of setting
Before die trial formula is virtual test mode, further includes: carry out chip initiation；Correspondingly, carry out test result capture it
Afterwards, further includes: determine whether the chip meets test condition according to the test result of capture.As shown in figure 5, technical solution has
Body is as follows:
Step S501, chip initiation is carried out.
Illustratively, chip initiation process, which can be, resets test logic circuit by reset signal, makes core
Piece enters test mode.
Step S502, current test pattern is arranged is virtual test mode, in the virtual test mode, by virtual
Associated control signal is taken over and tested to scratchpad register.
Step S503, by the virtual test register analog tck signal, test mode signal, transmission enable signal,
Idle state signal and fictitious order signal generate transmission clock, carry out the loading of the first test link.
Step S504, after test link loads, pass through the virtual test register analog tck signal, test
Mode signal, capture enable signal, idle state signal and fictitious order signal generate capture clock, carry out catching for test result
It obtains.
Step S505, the loading for carrying out the second test link, after the second test link loads, by described virtual
Scratchpad register generates capture clock, carries out the capture of test result.
Step S506, data refresh clock is generated by the virtual test register.
Step S507, determine whether the chip meets test condition according to the test result of capture.
Wherein, it can be compared according to the test result and expected test result of capture, if the comparison results are consistent, then recognizes
Meet test condition for it, i.e. chip functions are normal, and if the comparison results are inconsistent, then test crash, and that there are functions is different for chip
Often.
By above scheme it is found that realizing the complete test of chip by virtual test register, chip testing effect is improved
Rate has saved hardware resource.
Fig. 6 is a kind of structural block diagram of virtual test device provided in an embodiment of the present invention, and the device is above-mentioned for executing
The virtual measuring method that embodiment provides, has the corresponding functional module of execution method and beneficial effect.As shown in fig. 6, the dress
It sets and specifically includes: mode setting module 101, transmission clock control module 102 and capture clock control module 103, wherein
Mode setting module 101 is virtual test mode for current test pattern to be arranged, in the virtual test mode,
Associated control signal is taken over and tested by virtual test register；
Clock control module 102 is transmitted, for generating transmission clock by the virtual test register, carries out test link dress
It carries；
Clock control module 103 is captured, for being caught after test link loads by virtual test register generation
Clock is obtained, the capture of test result is carried out.
By above scheme it is found that being virtual test mode by the way that current test pattern is arranged, in the virtual test mode
In, associated control signal is taken over and tested by virtual test register, is generated and is transmitted by the virtual test register
Clock carries out test link and loads, after test link loads, when being captured by virtual test register generation
Clock carries out the technical solution of the capture of test result, improves chip testing efficiency, saved hardware resource.
In a possible embodiment, the transmission clock is according to tck signal, test mode signal, the enabled letter of transmission
Number, idle state signal and fictitious order signal generate.
In a possible embodiment, the virtual test register is also used to be arranged and be passed by idle state signal
The delay of defeated clock.
In a possible embodiment, the capture clock is according to tck signal, test mode signal, the enabled letter of capture
Number, idle state signal and fictitious order signal generate.
In a possible embodiment, the transmission clock control module 102 is specifically used for:
Carry out the loading of the first test link；And
The loading for carrying out the second test link, after the second test link loads, the capture clock control module 103 has
Body is used for:
Capture clock is generated by the virtual test register, carries out the capture of test result.
In a possible embodiment, refresh clock control module 104, is used for:
After the second test link loads, capture clock is generated by the virtual test register, carries out test result
Capture after, pass through the virtual test register generate data refresh clock.
In a possible embodiment, further include initialization module 105, be used for:
Before current test pattern is set and is virtual test mode, chip initiation is carried out；
Test result processing module 106, is specifically used for:
Determine whether the chip meets test condition according to the test result of capture.
Fig. 7 is a kind of structural schematic diagram of equipment provided in an embodiment of the present invention, as shown in fig. 7, the equipment includes processing
Device 201, memory 202, input unit 203 and output device 204；The quantity of processor 201 can be one or more in equipment
It is a, in Fig. 7 by taking a processor 201 as an example；Processor 201, memory 202, input unit 203 and output device in equipment
204 can be connected by bus or other modes, in Fig. 7 for being connected by bus.
Memory 202 is used as a kind of computer readable storage medium, can be used for storing software program, journey can be performed in computer
Sequence and module, if the corresponding program instruction/module of the virtual measuring method in the embodiment of the present invention is (for example, virtual test fills
Dimension information determining module 101, storage position determination module 102 and control instruction output module 103 in setting).Processor 201
By running the software program, instruction and the module that are stored in memory 202, thereby executing equipment various function application with
And data processing, that is, realize above-mentioned virtual measuring method.
Memory 202 can mainly include storing program area and storage data area, wherein storing program area can store operation system
Application program needed for system, at least one function；Storage data area, which can be stored, uses created data etc. according to terminal.This
Outside, memory 202 may include high-speed random access memory, can also include nonvolatile memory, for example, at least one
Disk memory, flush memory device or other non-volatile solid state memory parts.In some instances, memory 202 can be into one
Step includes the memory remotely located relative to processor 201, these remote memories can pass through network connection to equipment.On
The example for stating network includes but is not limited to internet, intranet, local area network, mobile radio communication and combinations thereof.
Input unit 203 can be used for receiving the number or character information of input, and generate with the user setting of equipment with
And the related key signals input of function control.Output device 204 may include that display screen etc. shows equipment.
The embodiment of the present invention also provides a kind of storage medium comprising computer executable instructions, and the computer is executable
Instruction is used to execute a kind of virtual measuring method when being executed by computer processor, this method comprises:
It is that virtual test mode is connect in the virtual test mode by virtual test register that current test pattern, which is arranged,
Manage and test associated control signal；
Transmission clock is generated by the virtual test register, test link is carried out and loads；
After test link loads, capture clock is generated by the virtual test register, carries out catching for test result
It obtains.
In a possible embodiment, the transmission clock is according to tck signal, test mode signal, the enabled letter of transmission
Number, idle state signal and fictitious order signal generate.
In a possible embodiment, the virtual test register is also used to be arranged and be passed by idle state signal
The delay of defeated clock.
In a possible embodiment, the capture clock is according to tck signal, test mode signal, the enabled letter of capture
Number, idle state signal and fictitious order signal generate.
In a possible embodiment, the test link loading that carries out includes:
Carry out the loading of the first test link；
Correspondingly, after the capture for carrying out test result, further includes:
The loading for carrying out the second test link, it is raw by the virtual test register after the second test link loads
At capture clock, the capture of test result is carried out.
In a possible embodiment, after the second test link loads, pass through the virtual test register
Capture clock is generated, after the capture for carrying out test result, further includes:
Data refresh clock is generated by the virtual test register.
In a possible embodiment, before current test pattern is set and is virtual test mode, further includes:
Carry out chip initiation；
Correspondingly, after the capture for carrying out test result, further includes:
Determine whether the chip meets test condition according to the test result of capture.
Certainly, a kind of storage medium comprising computer executable instructions, computer provided by the embodiment of the present invention
The method operation that executable instruction is not limited to the described above, can also be performed void provided by any embodiment of the embodiment of the present invention
Relevant operation in quasi- test method.
By the description above with respect to embodiment, it is apparent to those skilled in the art that, the present invention
Embodiment can be realized by software and required common hardware, naturally it is also possible to by hardware realization, but in many cases before
Person is more preferably embodiment.Based on this understanding, the technical solution of the embodiment of the present invention is substantially in other words to existing skill
The part that art contributes can be embodied in the form of software products, which can store in computer
Floppy disk, read-only memory (Read-Only Memory, ROM), random access memory in readable storage medium storing program for executing, such as computer
Device (Random Access Memory, RAM), flash memory (FLASH), hard disk or CD etc., including some instructions are used so that one
Platform computer equipment (can be personal computer, server or the network equipment etc.) executes each implementation of the embodiment of the present invention
Method described in example.
It is worth noting that, included each unit and module are only pressed in the embodiment of above-mentioned virtual test device
It is divided, but is not limited to the above division according to function logic, as long as corresponding functions can be realized；In addition,
The specific name of each functional unit is also only for convenience of distinguishing each other, and is not intended to restrict the invention the protection model of embodiment
It encloses.
Note that above are only the preferred embodiment and institute's application technology principle of the embodiment of the present invention.Those skilled in the art
It will be appreciated that the embodiment of the present invention is not limited to specific embodiment described here, it is able to carry out for a person skilled in the art each
The apparent variation of kind, readjustment and the protection scope substituted without departing from the embodiment of the present invention.Therefore, although more than passing through
Embodiment is described in further detail the embodiment of the present invention, but the embodiment of the present invention is not limited only to the above implementation
Example can also include more other equivalent embodiments in the case where not departing from design of the embodiment of the present invention, and the present invention is implemented
The range of example is determined by the scope of the appended claims.
Claims (10)
1. virtual measuring method characterized by comprising
It is that virtual test mode is connect in the virtual test mode by virtual test register that current test pattern, which is arranged,
Manage and test associated control signal；
Transmission clock is generated by the virtual test register, test link is carried out and loads；
After test link loads, capture clock is generated by the virtual test register, carries out catching for test result
It obtains.
2. the method according to claim 1, wherein the transmission clock is believed according to tck signal, test pattern
Number, transmission enable signal, idle state signal and fictitious order signal generate.
3. according to the method described in claim 2, it is characterized in that, the virtual test register is also used to be arranged by idle shape
State signal obtains the delay of transmission clock.
4. the method according to claim 1, wherein the capture clock is believed according to tck signal, test pattern
Number, capture enable signal, idle state signal and fictitious order signal generate.
5. method according to any of claims 1-4, which is characterized in that it is described carry out test link loading include:
Carry out the loading of the first test link；
Correspondingly, after the capture for carrying out test result, further includes:
The loading for carrying out the second test link, it is raw by the virtual test register after the second test link loads
At capture clock, the capture of test result is carried out.
6. according to the method described in claim 5, it is characterized in that, passing through the void after the second test link loads
Quasi- scratchpad register generates capture clock, after the capture for carrying out test result, further includes:
Data refresh clock is generated by the virtual test register.
7. according to the method described in claim 6, it is characterized in that, be arranged current test pattern be virtual test mode it
Before, further includes:
Carry out chip initiation；
Correspondingly, after the capture for carrying out test result, further includes:
Determine whether the chip meets test condition according to the test result of capture.
8. virtual test device characterized by comprising
Mode setting module is that virtual test mode passes through in the virtual test mode for current test pattern to be arranged
Associated control signal is taken over and tested to virtual test register；
Clock control module is transmitted, for generating transmission clock by the virtual test register, test link is carried out and loads；
Clock control module is captured, for generating and capturing by the virtual test register after test link loads
Clock carries out the capture of test result.
9. a kind of equipment, comprising: processor, memory and storage are on a memory and the computer that can run on a processor
Program, which is characterized in that the processor is realized when executing the computer program as of any of claims 1-7
Virtual measuring method.
10. a kind of storage medium comprising machine executable instructions, which is characterized in that the machine executable instructions are by equipment
For executing such as virtual measuring method of any of claims 1-7 when processor executes.
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| CN114416608A (en) * | 2021-12-06 | 2022-04-29 | 埃夫特智能装备股份有限公司 | External equipment simulation platform based on virtual robot controller bus structure and simulation method thereof |
| CN114610557A (en) * | 2022-05-11 | 2022-06-10 | 宏晶微电子科技股份有限公司 | Method and device for testing equipment driving unit |
| CN115756996A (en) * | 2023-01-09 | 2023-03-07 | 苏州浪潮智能科技有限公司 | Chip testing method, device and equipment and readable storage medium |
| CN115952026A (en) * | 2023-03-15 | 2023-04-11 | 燧原智能科技(成都)有限公司 | Method, device, equipment and storage medium for positioning abnormity of virtual chip |
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| CN115952026A (en) * | 2023-03-15 | 2023-04-11 | 燧原智能科技(成都)有限公司 | Method, device, equipment and storage medium for positioning abnormity of virtual chip |
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