CN109905709B

CN109905709B - Block-removing filtering method based on pipeline recombination mode

Info

Publication number: CN109905709B
Application number: CN201910217621.8A
Authority: CN
Inventors: 顾先军; 胡彦多
Original assignee: Nanjing Weixiang Science And Technology Co ltd
Current assignee: Nanjing Weixiang Science And Technology Co ltd
Priority date: 2019-03-21
Filing date: 2019-03-21
Publication date: 2021-05-07
Anticipated expiration: 2039-03-21
Also published as: CN109905709A

Abstract

The invention discloses a square block removing filtering method based on a pipeline recombination mode, which belongs to the technical field of image processing and comprises the steps of establishing a filtering module in an FPGA (field programmable gate array), inputting image data into the FPGA, processing the image data by the FPGA according to frames, wherein each frame image is a rectangular image square block with the size of m multiplied by n, transmitting all the rectangular image square blocks to the filtering module by the FPGA for filtering, and vertically filtering two O units at the lower left corners of all the rectangular image square blocks by the filtering module to solve the technical problem that the vertical filtering and the horizontal filtering share one same module.

Description

Block-removing filtering method based on pipeline recombination mode

Technical Field

The invention belongs to the technical field of image processing, and particularly relates to a deblocking filtering method based on a pipeline recombination mode.

Background

As a next generation Video coding standard, hevc (high Efficiency Video coding) was proposed in 2013 by the organization JCTVC in which the International Telecommunication Union (ITU) and the Moving Picture Experts Group (MPEG) are jointly established. Compared with the previous generation standard H.264/AVC, the bit rate is reduced by 50 percent and is currently universal on the premise of the same visual effect.

In HEVC, a frame of picture is divided into Largest Coding Units (LCUs), which may be 64x64 in size, and then the LCUs are divided into smaller Coding Units (CUs), which range in size from 8x8 to 32x 32. Like h.264/AVC, HEVC uses block-based predictive transform coding. This approach may cause discontinuity of boundary pixel values of the blocks, i.e., blocking artifacts, thereby affecting the image quality of the video and increasing the codestream. When quantization is at a low bit rate and the coding scale becomes large, blocking artifacts are a serious problem.

Different from h.264/AVC, HEVC only uses deblocking filtering on the boundary of a 4x4 pixel block, and the former only uses deblocking filtering on the boundary of luminance and chrominance of an 8x8 pixel block, so from the viewpoint of operation, HEVC reduces the computational complexity while ensuring the image quality, and improves the parallel processing efficiency.

The deblocking filter strength control parameter is similar to H.264/AVC, but the number of the parameters is reduced from 5 to 3, P and Q are two adjacent pixel blocks of 8x8, and when one of the adjacent pixel blocks is an intra-frame prediction image block, the filter strength is selected to be 2.

The filtering strength is selected to be 1 when either of the following conditions is satisfied: (1) p and Q have at least one non-zero transform coefficient; (2) the reference indices of P and Q are not equal; (3) the Motion Variables (MVs) of P and Q are not equal; (4) the difference between the MV components of P and Q is greater than or equal to one integer pixel. If none of the preceding conditions is true, the filtering strength is 0, meaning that no deblocking filtering process is required.

From the filter strength and the average quantization parameter of P, Q, two thresholds can be determined in a predefined table: tc and beta; for luminance pixels, different choices represent different filtering strengths, respectively: no filtering, strong filtering, weak filtering. Note that this option can be shared across four luminance rows and columns, in the first and last row or column, as in fig. 1, to reduce computational complexity. For chroma pixels, there are only two cases of no filtering and normal filtering; normal filtering is only used when the filtering strength is greater than 1, and the filtering process is handled using the control variables tc and beta.

In the standard reference software HM16.14, the deblocking filter processes the 8x8 block vertical boundaries of each LCU until after a frame is vertically filtered, and then processes the horizontal boundaries of a frame. Therefore, firstly, the processing delay is increased in the DBF processing process, which is contrary to the low-delay index of project design; secondly, if the flow is carried on the hardware, the logic resource and the off-chip storage resource of the hardware can be wasted, and the resource can not be effectively saved for other functional modules.

Disclosure of Invention

The invention aims to provide a deblocking filtering method based on a pipeline recombination mode, which solves the technical problem that vertical filtering and horizontal filtering share the same module.

In order to achieve the purpose, the invention adopts the following technical scheme:

a deblocking filtering method based on a pipeline recombination mode comprises the following steps:

step 1: establishing a filtering module in the FPGA, inputting image data into the FPGA, processing the image data by the FPGA according to frames, wherein each frame of image is a rectangular image square with the size of m multiplied by n;

the FPGA divides a rectangular image square into 4 coding units, wherein the 4 coding units comprise a V unit and 3O units, the length of the V unit is m, the width of the V unit is n1, n1 is smaller than n, the length of the O unit is n2, n2 is n-n1, the width of the O unit is m1, and m1 is m/3;

in the image P1, the V2 unit, the V3 unit and the O4 unit are all positioned at the lower side of the V1 unit, and the V2 unit, the V3 unit and the O4 unit are arranged from left to right in sequence;

in the image P2, the V6 unit, the V7 unit and the O8 unit are all positioned at the lower side of the V5 unit, and the V6 unit, the V7 unit and the O8 unit are arranged from left to right in sequence;

the 3O units are all positioned at the lower side of the V unit, and the 3O units are sequentially arranged from left to right;

step 2: the FPGA transmits all the rectangular image squares to a filtering module for filtering, and the filtering module vertically filters two O units at the lower left corner of all the rectangular image squares;

and step 3: setting two adjacent frame images as an image P1 and an image P2 respectively, wherein the image P1 is temporally positioned before the image P2, and after filtering by the method of step 2, the image P2 comprises a V5 unit, a V6 unit, a V7 unit and an O8 unit, the image P1 comprises a V1 unit, a V2 unit, a V3 unit and an O4 unit, wherein the V6 unit, the V7 unit, the V2 unit and the V3 unit are all vertically filtered O units;

the FPGA replaced the O4 cells in image P1 with V6 cells and produced a new image P3;

and 4, step 4: rotating the image P3 by 90 degrees to obtain an image P4;

and 5: cropping the left n3 × m sized rectangular elements of image P4 to the right of image P4, where n3 is n ÷ 3, producing a new image P5 after re-stitching;

step 6: setting the region of m4 × n4 in the lower left corner of the image P5 as VH cells, m4 being equal to two thirds of m in size, and n4 being equal to two thirds of n in size;

vertical filtering of the VH unit to produce a new image P6;

and 7: cutting a right n3 × m rectangular unit in the image P6 to the left of the image P6, and re-splicing to produce a new image P7;

and 8: carrying out reverse rotation of 90 degrees on the image P7 to obtain an image P8;

and step 9: the FPGA outputs the image P8 as a final output result.

Preferably, when step 1 is performed, n1 ═ n ÷ 3, and m and n are both pixel sizes.

Preferably, the vertical filtering is performed by performing filtering calculation processing using only pixels of each line in the image, and the result is valid only for the line.

The invention relates to a deblocking filtering method based on a pipeline recombination mode, which solves the technical problem that vertical filtering and horizontal filtering share the same module; the invention adopts the design idea of a production line, so that the written calculation result can be output at each moment on the premise of fixed delay of the de-blocking filtering, and the system delay is greatly reduced; the processing mode of rotating the square block is adopted, so that the vertical filtering and the horizontal filtering share the same module, and the reusability of the design is improved; the invention adopts the FPGA hardware realization mode, fully exerts the powerful capacity of FPGA matrix conversion and parallelism, occupies less resources than the common design and is beneficial to the combination with other coding and decoding modules.

Drawings

FIG. 1 is a filtering flow diagram of the present invention;

FIG. 2 is a schematic diagram of the reorganization of two frame images according to the present invention;

FIG. 3 is a schematic representation of the results of step 4 of the present invention;

FIG. 4 is a schematic representation of the results of step 5 of the present invention;

FIG. 5 is a schematic representation of the results of step 6 of the present invention;

FIG. 6 is a schematic representation of the results of step 7 of the present invention;

FIG. 7 is a schematic representation of the results of step 8 of the present invention.

Detailed Description

1-7, a deblocking filtering method based on pipeline reorganization method includes the following steps:

and 4, step 4: rotating the image P3 by 90 degrees to obtain an image P4;

vertical filtering of the VH unit to produce a new image P6;

and step 9: the FPGA outputs the image P8 as a final output result.

Claims

1. A deblocking filtering method based on a pipeline recombination mode is characterized in that: the method comprises the following steps:

and 4, step 4: rotating the image P3 by 90 degrees to obtain an image P4;

vertical filtering of the VH unit to produce a new image P6;

and step 9: the FPGA outputs the image P8 as a final output result.

2. The deblocking filtering method based on pipeline reorganization as claimed in claim 1, wherein: in performing step 1, n1 ═ n ÷ 3, and m and n are pixel sizes.

3. The deblocking filtering method based on pipeline reorganization as claimed in claim 1, wherein: the vertical filtering is performed by performing filtering calculation processing using only pixels of each line in the image, and the result is valid only for the line.