CN109904233B - Method for adjusting work function of metal gate and method for preparing MOSFET (Metal-oxide-semiconductor field Effect transistor) - Google Patents
Method for adjusting work function of metal gate and method for preparing MOSFET (Metal-oxide-semiconductor field Effect transistor) Download PDFInfo
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Abstract
The invention provides a method for adjusting a work function of a metal gate and a method for preparing an MOSFET. The adjusting method comprises the following steps: s1, providing a substrate with a first gate dielectric layer and a second gate dielectric layer on the surface, wherein the first gate dielectric layer and the second gate dielectric layer are positioned on different areas of the substrate; s2, sequentially forming a TaN layer and a TiN layer on the first gate dielectric layer and the second gate dielectric layer along the direction far away from the substrate, and then removing the TiN layer on the first gate dielectric layer, wherein the TaN layer on the first gate dielectric layer has a first surface far away from the substrate, and the TiN layer on the second gate dielectric layer has a second surface far away from the substrate; and S3, respectively forming TiAl layers on the first surface and the second surface, and then removing the TiAl layers. The work function metal TiAl in the NMOS can be removed, and the work function of the NMOS can be kept unchanged after adjustment, so that the thickness of a grid electrode is obviously reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for adjusting a work function of a metal gate and a method for preparing an MOSFET.
Background
For MOSFETs manufactured using HKMG techniques, changing the threshold voltage requires changing the gate metal work function, i.e.
For MOSFETs, one conventional method of changing the work function of the gate metal is to increase the thickness of the gate metal. This relationship between thickness and gate work function may be considered approximately linear within certain thickness intervals.
Therefore, two different thicknesses of work function metal are deposited for NMOS and PMOS, respectively. To meet the threshold voltage requirements.
The process flow of a Replacement Metal Gate (RMG) gate portion of a MOSFET of the prior art is shown in fig. 1-6 and generally includes the following steps: sequentially forming a gate dielectric layer 20 'and a capping layer 30' on the substrate 10 ', as shown in FIG. 1, and then depositing an etch stop layer 40' (typically TaN) on the PMOS and NMOS gate regions, as shown in FIG. 2; then, depositing a P-type work function metal 50 ' (such as TiN) with the same thickness on the etching barrier layer 40 ', as shown in fig. 3, and removing the excess P-type work function metal 50 ' on the NMOS by etching, as shown in fig. 4; then depositing an N-type work function metal 60' (e.g., TiAl) of the same thickness, as shown in FIG. 5; finally, an adhesion layer 70 'and a tie layer 80' are deposited, as shown in FIG. 6. If more different threshold voltages are required in the design, the deposition process of the P-type work function metal may be repeated for a plurality of times. It is found that this approach deposits an excess N-type work function metal on the gate of the PMOS, increasing the thickness of the gate. If the removal is performed separately, a photolithography process is added, thereby increasing the cost virtually.
Disclosure of Invention
The invention mainly aims to provide a method for adjusting the work function of a metal gate and a method for preparing a metal-oxide-semiconductor field effect transistor (MOSFET), so as to solve the problem of the increase of the whole gate thickness caused by the adjustment of the work function of the metal gate in the prior art.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for adjusting a work function of a metal gate, comprising the steps of: s1, providing a substrate with a first gate dielectric layer and a second gate dielectric layer on the surface, wherein the first gate dielectric layer and the second gate dielectric layer are positioned on different areas of the substrate; s2, sequentially forming a TaN layer and a TiN layer on the first gate dielectric layer and the second gate dielectric layer along the direction far away from the substrate, and then removing the TiN layer on the first gate dielectric layer, wherein the TaN layer on the first gate dielectric layer has a first surface far away from the substrate, and the TiN layer on the second gate dielectric layer has a second surface far away from the substrate; and S3, respectively forming TiAl layers on the first surface and the second surface, and then removing the TiAl layers.
Further, between step S1 and step S2, the adjusting method further includes a step of forming cap layers on the first gate dielectric layer and the second gate dielectric layer, respectively.
Further, the material forming the cap layer is TiN.
Further, the thickness of the cap layer is less than or equal to 1.5 nm.
Further, the thickness of the TaN layer is 1-1.5 nm.
Further, the thickness of the TiN layer is less than 4 nm.
Further, in step S2, a TaN layer and a TiN layer are sequentially formed by an atomic layer deposition process, and the time interval between the step of forming the TaN layer and the step of forming the TiN layer is not less than 2 h.
Furthermore, the thickness of the TiAl layer is 4-5 nm.
Furthermore, both the first gate dielectric layer and the second gate dielectric layer are HfO2And (3) a layer.
According to another aspect of the present invention, there is provided a method for manufacturing a MOSFET, comprising the steps of: providing a substrate with a first source/drain region and a second source/drain region, forming a first gate dielectric layer on the surface of the substrate between the first source/drain regions, and forming a second gate dielectric layer on the surface of the substrate between the second source/drain regions; respectively forming metal work function layer stacks on a first gate dielectric layer and a second gate dielectric layer by adopting any one of the adjusting methods, wherein the metal work function layer stack on the first gate dielectric layer is provided with a first surface of the substrate far away from the first gate dielectric layer, and the metal work function layer stack on the second gate dielectric layer is provided with a second surface of the substrate far away from the second gate dielectric layer; and forming an adhesion layer and a connecting layer on the first surface and the second surface respectively in sequence along the direction far away from the substrate to form a first gate stack structure on the first gate dielectric layer and a second gate stack structure on the second gate dielectric layer, wherein the first source/drain region, the first gate dielectric layer and the first gate stack structure form an NMOS transistor, and the second source/drain region, the second gate dielectric layer and the second gate stack structure form a PMOS transistor.
By applying the technical scheme of the invention, as experiments show that TiAl is deposited on the TiN layer, the integral work function of the film can be reduced to about 4.2-4.3, and the integral work function of the film can be recovered to 4.7-4.8 after TiAl is removed; while the overall work function of the film is reduced to about 4.2-4.3 by depositing TiAl on the thin TaN (about 1nm), the overall work function of the film is still maintained in the interval and is not restored to the previous value after the TiAl is removed. Therefore, the invention provides a method for adjusting the work function of a metal gate, which utilizes the different properties of TiN and TaN to integrally remove the N-type work function metal TiAl in the NMOS and the PMOS, thereby keeping the work function of the NMOS unchanged after adjustment while removing the work function metal TiAl in the NMOS and obviously reducing the thickness of the gate. Meanwhile, the P-type work function metal TiN does not need to compensate the low work function of TiAl, so that the thickness of the PMOS gate can be further reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic perspective view of a base after a gate dielectric layer and a cap layer are sequentially formed on a substrate in a method for adjusting a work function of a metal gate provided in the prior art;
FIG. 2 is a schematic diagram showing the three-dimensional structure of the substrate after depositing an etch stop layer in the PMOS and NMOS gate regions shown in FIG. 1;
FIG. 3 is a schematic diagram showing the three-dimensional structure of the substrate after depositing a P-type work function metal with the same thickness on the etching barrier layer shown in FIG. 2;
FIG. 4 is a schematic diagram showing the three-dimensional structure of the substrate after removing the excess P-type work function metal from the NMOS shown in FIG. 3;
FIG. 5 is a schematic perspective view of the substrate shown in FIG. 4 after depositing an N-type work function metal with the same thickness thereon;
FIG. 6 is a schematic diagram showing the three-dimensional structure of the substrate after an adhesion layer and a connection layer are deposited on the N-type work function metal shown in FIG. 5;
fig. 7 is a schematic perspective view illustrating a substrate after cap layers are formed on the first gate dielectric layer and the second gate dielectric layer in the method for adjusting a work function of a metal gate provided in the embodiment of the present application;
FIG. 8 is a schematic perspective view showing the structure of the substrate after TaN layers are formed on the first gate dielectric layer and the second gate dielectric layer shown in FIG. 7;
FIG. 9 is a schematic diagram showing the three-dimensional structure of the substrate after TiN layers are respectively formed on the TaN layers shown in FIG. 8;
fig. 10 is a schematic diagram showing the three-dimensional structure of the substrate after removing the TiN layer on the first gate dielectric layer shown in fig. 9;
FIG. 11 is a schematic perspective view of the substrate after TiAl layers are formed on the first and second surfaces of FIG. 10;
FIG. 12 is a schematic perspective view of the substrate after the TiAl layers shown in FIG. 11 are removed;
fig. 13 is a schematic perspective view showing a three-dimensional structure of the base after an adhesion layer and a connection layer are formed on the first surface and the second surface of fig. 12, respectively.
Wherein the figures include the following reference numerals:
10', a substrate; 20', a gate dielectric layer; 30', a cap layer; 40', etching the barrier layer; 50', P-type work function metal; 60', an N-type work function metal; 70', an adhesive layer; 80', a connecting layer; 10. a substrate; 210. a first gate dielectric layer; 220. a second gate dielectric layer; 30. a cap layer; 40. a TaN layer; 50. a TiN layer; 60. a TiAl layer; 70. an adhesive layer; 80. and (7) connecting the layers.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background section, the prior art technique of adjusting the metal gate work function results in an increase in the overall gate thickness. The inventor of the present invention has studied the above problem and proposed a method for adjusting the work function of a metal gate, as shown in fig. 7 to 13, comprising the following steps: s1, providing a substrate 10 having a first gate dielectric layer 210 and a second gate dielectric layer 220 on the surface, wherein the first gate dielectric layer 210 and the second gate dielectric layer 220 are located on different regions of the substrate 10; s2, sequentially forming a TaN layer 40 and a TiN layer 50 on the first gate dielectric layer 210 and the second gate dielectric layer 220 along a direction away from the substrate 10, and then removing the TiN layer 50 on the first gate dielectric layer 210, wherein the TaN layer 40 on the first gate dielectric layer 210 has a first surface away from the substrate 10, and the TiN layer 50 on the second gate dielectric layer 220 has a second surface away from the substrate 10; s3, after the TiAl layers 60 are formed on the first surface and the second surface, respectively, the TiAl layers 60 are removed.
As the experiment reveals that TiAl is deposited on the TiN layer, the integral work function of the film can be reduced to about 4.2-4.3, and the integral work function of the film can be recovered to 4.7-4.8 after the TiAl is removed; while the overall work function of the film is reduced to about 4.2-4.3 by depositing TiAl on the thin TaN with the thickness of about 1nm, the overall work function of the film after removing the TiAl is still kept in the interval and cannot be restored to the previous value. Therefore, in the method for adjusting the work function of the metal gate, the N-type work function metal TiAl in the NMOS and the PMOS is removed integrally by using different properties of TiN and TaN, so that the work function metal TiAl in the NMOS can be removed while the work function of the NMOS is kept unchanged after adjustment, and the thickness of the gate is obviously reduced. Meanwhile, the P-type work function metal TiN does not need to compensate the low work function of TiAl, so that the thickness of the PMOS gate can be further reduced.
An exemplary embodiment of a method for adjusting a work function of a metal gate provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is executed: a substrate 10 having a first gate dielectric layer 210 and a second gate dielectric layer 220 on the surface thereof is provided, and the first gate dielectric layer 210 and the second gate dielectric layer 220 are located on different regions of the substrate 10, as shown in fig. 7.
In step S1, the first gate dielectric layer 210 and the second gate dielectric layer 220 formed on the surface of the substrate 10 are made of the same material or have the same thickness; preferably, the first gate dielectric layer 210 and the second gate dielectric layer 220 are both HfO2The layers are not limited to the above-mentioned kinds, and those skilled in the art can select the kinds of the first gate dielectric layer 210 and the second gate dielectric layer 220 appropriately according to the prior art.
Preferably, after the step S1, the adjusting method of the present invention may further include a step of forming a capping layer 30 on the first gate dielectric layer 210 and the second gate dielectric layer 220, respectively, as shown in fig. 7. The cap layer 30 may be selected by those skilled in the art according to the prior art, for example, the cap layer 30 may be TiN. In order to avoid the influence of too large thickness on the work function adjusting effect and too small thickness on the protection effect, the thickness of the capping layer 30 is preferably less than or equal to 1.5 nm.
After the step S1 is performed, a step S2 is performed: sequentially forming a TaN layer 40 and a TiN layer 50 on the first gate dielectric layer 210 and the second gate dielectric layer 220 in a direction away from the substrate 10, and then removing the TiN layer 50 on the first gate dielectric layer 210, wherein the TaN layer 40 on the first gate dielectric layer 210 has a first surface away from the substrate 10, and the TiN layer 50 on the second gate dielectric layer 220 has a second surface away from the substrate 10, as shown in fig. 8 to 10.
In the step S2, the TaN layer 40 serves as an etching barrier layer for preventing the over-etching of the subsequently formed layers from affecting the underlying first gate dielectric layer 210 and the underlying second gate dielectric layer 220. In order to effectively perform the etching barrier function, the thickness of the TaN layer 40 is preferably 1 to 1.5 nm.
In the step S2, the TiN layer 50 is a P-type work function metal for adjusting the work function of the gate electrode in the PMOS transistor, and since the TiN layer 50 is formed on the surface of the TaN layer 40 above the first gate dielectric layer 210 and the surface of the TaN layer 40 above the second gate dielectric layer 220 by one-step deposition, the thickness of the gate electrode in the NMOS transistor is reduced by removing the TiN layer 50 above the first gate dielectric layer 210. Also, in order to adjust the work function of the gate electrode in the PMOS transistor more effectively, the thickness of the TiN layer 50 is preferably less than 4 nm.
In the step S2, the TaN layer 40 and the TiN layer 50 may be sequentially formed by an atomic layer deposition process; in order to sufficiently fix the work function of the NMOS after TiAl is removed to about 4.2 to 4.3, the time interval between the step of forming the TaN layer 40 and the step of forming the TiN layer 50 is preferably not less than 2 h.
After the step S2 is performed, a step S3 is performed: after the TiAl layers 60 are formed on the first surface and the second surface, respectively, each TiAl layer 60 is removed, as shown in fig. 11 and 12.
As the experiment reveals that TiAl is deposited on the TiN layer, the integral work function of the film can be reduced to about 4.2-4.3, and the integral work function of the film can be recovered to 4.7-4.8 after the TiAl is removed; while the overall work function of the film is reduced to about 4.2-4.3 by depositing TiAl on the thin TaN with the thickness of about 1nm, the overall work function of the film after removing the TiAl is still kept in the interval and cannot be restored to the previous value. Therefore, in the step S3, the TiAl layer 60 is entirely removed after the formation of the TiAl layer by utilizing the different properties of TiN and TaN, so that the work function metal TiAl in the NMOS is removed while the work function of the NMOS remains unchanged after adjustment, thereby significantly reducing the gate thickness.
In step S3, in order to adjust the work function of the gate electrode of the NMOS transistor more effectively, the thickness of the TiAl layer 60 is preferably 4 to 5 nm.
According to another aspect of the present invention, there is also provided a method for manufacturing a MOSFET, including the steps of: providing a substrate 10 with a first source/drain region and a second source/drain region, forming a first gate dielectric layer 210 on the surface of the substrate 10 between the first source/drain regions, and forming a second gate dielectric layer 220 on the surface of the substrate 10 between the second source/drain regions; forming metal work function layer stacks on the first gate dielectric layer 210 and the second gate dielectric layer 220 by using the above adjusting method, where the metal work function layer stack on the first gate dielectric layer 210 has a first surface of the substrate 10 away from the first surface, and the metal work function layer stack on the second gate dielectric layer 220 has a second surface of the substrate 10 away from the second surface, as shown in fig. 7 to 12; an adhesion layer 70 and a connection layer 80 are sequentially formed on the first surface and the second surface in a direction away from the substrate 10 to form a first gate stack structure on the first gate dielectric layer 210 and a second gate stack structure on the second gate dielectric layer 220, wherein the first source/drain region, the first gate dielectric layer 210 and the first gate stack structure constitute an NMOS transistor, the second source/drain region, the second gate dielectric layer 220 and the second gate stack structure constitute a PMOS transistor, and the formed MOSFET is as shown in fig. 13.
The preparation method adopts the adjusting method to respectively form the metal work function layer stacks in the NMOS transistor and the PMOS transistor, so that the N-type work function metal TiAl in the NMOS and the PMOS is integrally removed by utilizing the different properties of TiN and TaN, the work function metal TiAl in the NMOS is removed, the work function of the NMOS can be kept unchanged after adjustment, and the thickness of a grid electrode is obviously reduced. Meanwhile, the P-type work function metal TiN does not need to compensate the low work function of TiAl, so that the thickness of the PMOS gate can be further reduced.
After the above-described step of forming the adhesive layers 70, a connection layer 80 is formed on each adhesive layer 70, as shown in fig. 13. The connection layer 80 serves as a lead for connection with a wiring layer and can protect the internal structure of the transistor and block strong destructive ions from the outside; the kind of the above-mentioned connection layer 80 can be reasonably selected by those skilled in the art according to the prior art, and the above-mentioned connection layer 80 can be a metal tungsten layer.
According to another aspect of the present invention, there is also provided a MOSFET, as shown in fig. 13, comprising a substrate 10 having first source/drain regions and second source/drain regions, a first gate dielectric layer 210 formed on a surface of the substrate 10 between the first source/drain regions, and a second gate dielectric layer 220 formed on a surface of the substrate 10 between the second source/drain regions, the MOSFET described above further comprises a metal work function layer stack, an adhesion layer 70 and a connection layer 80, the metal work function layer stack comprises a TaN layer 40 arranged on a first gate dielectric layer 210, and a TaN layer 40 and a TiN layer 50 arranged on a second gate dielectric layer 220, the metal work function layer stack on the first gate dielectric layer 210 has a first surface far away from the substrate 10, the metal work function layer stack on the second gate dielectric layer 220 has a second surface far away from the substrate 10, and the above-mentioned adhesive layer 70 and the connection layer 80 are sequentially disposed on the first surface and the second surface in a direction away from the substrate 10.
In the MOSFET of the present invention, the metal work function layer stack, the adhesion layer 70 and the connection layer 80 on the first gate dielectric layer 210 form a first gate stack structure, the metal work function layer stack, the adhesion layer 70 and the connection layer 80 on the second gate dielectric layer 220 form a second gate stack structure, the first source/drain region, the first gate dielectric layer 210 and the first gate stack structure form an NMOS transistor, and the second source/drain region, the second gate dielectric layer 220 and the second gate stack structure form a PMOS transistor.
The MOSFET of the invention adopts the method for adjusting the metal gate work function, and the method for adjusting the metal gate work function respectively forms the metal work function layer stacks in the NMOS transistor and the PMOS transistor, so that the N-type work function metal TiAl in the NMOS and the PMOS is integrally removed by utilizing the different properties of TiN and TaN, the work function metal TiAl in the NMOS can be removed, the work function of the NMOS can be kept unchanged after adjustment, and the thickness of a gate electrode is obviously reduced. Meanwhile, the P-type work function metal TiN does not need to compensate the low work function of TiAl, so that the thickness of the PMOS gate can be further reduced.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
according to the invention, the N-type work function metal TiAl in the NMOS and the PMOS is removed integrally by utilizing the different properties of TiN and TaN, so that the work function metal TiAl in the NMOS can be removed while the work function of the NMOS is kept unchanged after adjustment, and the thickness of a grid electrode is obviously reduced. Meanwhile, the P-type work function metal TiN does not need to compensate the low work function of TiAl, so that the thickness of the PMOS gate can be further reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for adjusting the work function of a metal gate is characterized by comprising the following steps:
s1, providing a substrate (10) with a first gate dielectric layer (210) and a second gate dielectric layer (220) on the surface, wherein the first gate dielectric layer (210) and the second gate dielectric layer (220) are located on different regions of the substrate (10);
s2, sequentially forming a TaN layer (40) and a TiN layer (50) on the first gate dielectric layer (210) and the second gate dielectric layer (220) respectively in a direction away from the substrate (10), and then removing the TiN layer (50) on the first gate dielectric layer (210), wherein the TaN layer (40) on the first gate dielectric layer (210) has a first surface away from the substrate (10), and the TiN layer (50) on the second gate dielectric layer (220) has a second surface away from the substrate (10);
s3, removing all TiAl layers (60) on the first surface and the second surface after forming the TiAl layers (60) on the first surface and the second surface respectively.
2. The conditioning method of claim 1, wherein between the step S1 and the step S2, the conditioning method further comprises a step of forming a cap layer (30) on the first gate dielectric layer (210) and the second gate dielectric layer (220), respectively.
3. Conditioning method according to claim 2, characterized in that the material forming the cap layer (30) is TiN.
4. The conditioning method according to claim 2, characterized in that the thickness of the cap layer (30) is ≦ 1.5 nm.
5. The conditioning method according to claim 1, characterized in that the TaN layer (40) has a thickness of 1-1.5 nm.
6. The conditioning method according to claim 1, characterized in that the thickness of the TiN layer (50) is less than 4 nm.
7. The conditioning method according to any of claims 1 to 6, wherein in step S2, the TaN layer (40) and the TiN layer (50) are sequentially formed using an atomic layer deposition process, and a time interval between the step of forming the TaN layer (40) and the step of forming the TiN layer (50) is ≧ 2 h.
8. The conditioning method according to claim 1, characterized in that the thickness of the TiAl layer (60) is between 4 and 5 nm.
9. The conditioning method of claim 1, wherein the first gate dielectric layer (210) and the second gate dielectric layer (220) are both HfO2And (3) a layer.
10. A preparation method of a MOSFET is characterized by comprising the following steps:
providing a substrate (10) having first and second source/drain regions, forming a first gate dielectric layer (210) on a surface of the substrate (10) between the first source/drain regions, and forming a second gate dielectric layer (220) on a surface of the substrate (10) between the second source/drain regions;
forming a metal work function layer stack on the first gate dielectric layer (210) and the second gate dielectric layer (220) respectively by using the adjusting method of any one of claims 1 to 8, wherein the metal work function layer stack on the first gate dielectric layer (210) has a first surface far away from the substrate (10), and the metal work function layer stack on the second gate dielectric layer (220) has a second surface far away from the substrate (10);
sequentially forming an adhesion layer (70) and a connection layer (80) on the first surface and the second surface, respectively, in a direction away from the substrate (10) to form a first gate stack structure on the first gate dielectric layer (210) and a second gate stack structure on the second gate dielectric layer (220),
the first source/drain region, the first gate dielectric layer (210) and the first gate stack structure form an NMOS transistor, and the second source/drain region, the second gate dielectric layer (220) and the second gate stack structure form a PMOS transistor.
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