CN109903799B - Three-dimensional flash memory array unit operation method capable of changing programming progression - Google Patents
Three-dimensional flash memory array unit operation method capable of changing programming progression Download PDFInfo
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Abstract
The invention discloses a three-dimensional flash memory array unit operation method with variable programming grades, which comprises the following steps: s1, receiving an erasing operation instruction and address information; s2, erasing the selected block structure; s3, receiving a multi-level programming instruction and address information; s4, judging whether the address overflows or not, if so, entering S5, otherwise, receiving programming level information of the target unit, and entering S6; s5, finishing the programming operation of the selected block structure; s6, performing multi-level programming operation on the current flash memory unit according to the multi-level programming instruction, the address information and the programming level information of the target unit; s7, judging whether the difference of the threshold voltages is not less than the preset minimum interval voltage, if so, changing the address information, and entering S3 to perform the programming operation of the next flash memory unit; otherwise, the current flash memory cell is subjected to the multilevel programming operation again for no more than a predetermined number of times. The invention programs the flash memory unit in a target level number to ensure that the threshold voltage of the flash memory unit is accurate to a preset value, thereby accurately controlling the data state of the flash memory unit.
Description
Technical Field
The invention belongs to the technical field of semiconductor storage, and particularly relates to a three-dimensional flash memory array unit operation method with variable programming grades.
Background
Flash memory (Flash), which is a type of nonvolatile memory, can be classified into NAND Flash memory and NOR Flash memory. Each memory cell of the NOR flash memory is independently connected with a bit line and a word line, thus exhibiting good random access characteristics, and a plurality of memory cells of the NAND flash memory are connected in series, thus exhibiting good integration characteristics, which is commonly used for the implementation of a high density flash memory array. With the reduction of feature size, flash memory arrays with planar structures will face the problems of increased adjacent cell crosstalk, too few floating gate stored electrons, etc. In order to continue to increase the storage density, flash memory arrays have been developed that have a three-dimensional vertical stack structure.
Three-dimensional vertical NAND memory strings were first disclosed in 2001, however, such NAND memory strings can only store one bit of data per cell. Multi-value storage is one of effective ways to achieve capacity expansion of a memory. When a plurality of states exist in a memory cell, how to accurately regulate the programming level of each cell in an array has important significance.
Patent CN104269407A discloses a nonvolatile high-density three-dimensional semiconductor memory device and a method for manufacturing the same, which changes the symmetric structure of the conventional flash memory string, achieves the effect of blocking the dielectric layer with different thicknesses in various directions through an asymmetric form, realizes the increase of the charge storage amount of the charge storage layer along with the increase of the write voltage, and enables one memory cell to store at least two bits of data. However, this patent does not describe a method of implementing multi-valued storage.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to solve the technical problem that the prior art does not relate to a multi-value storage implementation mode.
In order to achieve the above object, in a first aspect, an embodiment of the present invention provides a method for operating a three-dimensional flash memory array unit with variable programming levels, the method is based on a quadrilateral memory cell structure with different dielectric layer thicknesses, and the method includes the following steps:
s1, receiving an erasing operation instruction and address information;
s2, performing erasing operation with a verification function on the selected block structure according to the erasing instruction and the address information;
s3, receiving a multi-level programming instruction and address information;
s4, judging whether the address overflows or not, if so, entering a step S5, otherwise, receiving programming level information of the target unit, and entering a step S6;
s5, finishing the programming operation of the selected block structure and finishing the operation;
s6, performing multi-level programming operation on the current flash memory unit according to the multi-level programming instruction, the address information and the programming level information of the target unit;
s7, judging whether the difference between the current stage threshold voltage and the threshold voltage after the previous stage operation is not less than the preset minimum interval voltage, if so, changing address information, and entering the step S3 to perform the programming operation of the next flash memory unit; otherwise, the current flash memory cell is subjected to the multilevel programming operation again for no more than a predetermined number of times.
Specifically, the electron storage jumps as the programming voltage increases, producing 4 different high threshold voltage regions, corresponding to 4 data states.
Specifically, a combination of the erased state and any 3 data states is selected, or the data states of the 4 high threshold regions are used directly, represented by programming levels of 2 bits, each corresponding to one data state.
Specifically, the programming level information includes an initial programming pulse voltage level and a programming pulse width.
Specifically, the programming operation for a single level of data storage employs a two-cycle approach of pulse amplitude increment and pulse width increment.
Specifically, the pulse amplitude increment specifically is: applying a pulse sequence with gradually increased amplitude to the unit, wherein the delta V is the amplitude increment and is determined by the preset maximum amplitude and the maximum cycle number; after each programming pulse, a verify voltage of appropriate magnitude is applied to determine the magnitude of the threshold voltage of the cell after the programming pulse has been applied.
Specifically, the pulse width increment is specifically: and applying a pulse sequence with gradually increased pulse width to the cell, wherein delta t is the pulse width increment and is determined by the preset maximum pulse width and the maximum cycle number, and applying a verification voltage with proper amplitude after each programming pulse to determine the threshold voltage of the cell after the programming pulse acts.
In a second aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for operating a three-dimensional flash memory array unit according to the first aspect is implemented.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
the invention firstly carries out the whole erasing operation of the block structure, and then carries out the pulse programming operation of the target level number on the single flash memory unit in sequence, each programming level number corresponds to a data state, multi-value storage is realized through multi-level programming, and all the units in the three-dimensional flash memory array are set to the required state. The method can accurately program the threshold voltage of the memory cell to a preset value, and the stored charges have narrow spatial distribution in the memory layer, so that the effect of accurately controlling the state of each flash memory cell in the array is finally achieved, and a certain interval is ensured among multi-value states.
Drawings
Fig. 1 is a schematic diagram of a peripheral circuit structure of a three-dimensional flash memory array according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for operating a three-dimensional flash memory array unit with variable programming levels according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of threshold voltage distributions of memory cells according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a programming operation with gradually increasing pulse amplitudes according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a programming operation process with gradually increasing pulse width according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, when performing an erase operation, the microprocessor controls the erase control unit to send an erase command, controls the address decoder to write address information, controls the driving voltage generator to generate a voltage driving signal (erase voltage), and finally performs an erase operation on the selected block structure through the read/write circuit. And after the erasing operation of the selected block structure is finished, the detection control unit and the counting control unit are sequentially gated and verify the states of different flash memory strings in the 3D storage array. If the state is qualified, the erasing is successful, if the state is unqualified, the erasing voltage is changed, the erasing operation of the block structure is carried out again, and then the verification is continued. After the verification is successful, a program operation is performed. The microprocessor controls the programming control unit to send a multi-level programming instruction, controls the address information to be written into the address decoder, controls the driving voltage generator to generate a voltage driving signal, and finally performs multi-level cyclic programming operation on the selected unit through the read-write circuit.
As shown in fig. 2, a method for operating a three-dimensional flash memory array unit with variable programming levels is based on a quadrilateral memory cell structure with different dielectric layer thicknesses, and comprises the following steps:
s1, receiving an erasing operation instruction and address information;
s2, performing erasing operation with a verification function on the selected block structure according to the erasing instruction and the address information;
s3, receiving a multi-level programming instruction and address information;
s4, judging whether the address overflows or not, if so, entering a step S5, otherwise, receiving programming level information of the target unit, and entering a step S6;
s5, finishing the programming operation of the selected block structure and finishing the operation;
s6, performing multi-level programming operation on the current flash memory unit according to the multi-level programming instruction, the address information and the programming level information of the target unit;
s7, judging whether the difference between the current stage threshold voltage and the threshold voltage after the previous stage operation is not less than the preset minimum interval voltage, if so, changing address information, and entering the step S3 to perform the programming operation of the next flash memory unit; otherwise, the current flash memory cell is subjected to the multilevel programming operation again for no more than a predetermined number of times.
S1, receiving an erasing operation instruction and address information.
The control unit receives an erase command and the address decoder receives address information.
And S2, carrying out erasing operation with a verification function on the selected block structure according to the erasing instruction and the address information.
The object of the erase operation is the selected block structure. The flash memory finishes the erasing operation to reach a uniform data state first, so that the data state of the flash memory can be accurately regulated and controlled by the multi-level programming operation.
And S3, receiving a multi-level programming instruction and address information.
After the verification is successful, the control unit receives the multi-level programming instruction, and the address decoder receives the address information. The multi-level programming instruction includes the state set by the target flash memory cell.
As shown in fig. 3, since the quadrilateral memory cell structure with different dielectric layer thicknesses is adopted, the electron storage amount jumps with the increase of the programming voltage, so that 4 high threshold voltage regions with narrow distribution can be generated, corresponding to 4 data states, which are respectively 101, 102, 103 and 104 in fig. 1, and the initial erasing state 100 of the cell is added, thereby totaling 5 data states. Only 4 states are needed for 2-bit data storage, and thus a combination of the erase state (E) and any 3 data states can be selected, or the data states of the 4 high threshold regions (P1, P2, P3, P4) are used directly, constituting 2-bit data. The embodiment of the invention sets different programming levels for each flash memory unit in the three-dimensional array, each programming level corresponds to one data state, multi-value storage is realized through multi-level programming, and finally the effect of accurately controlling the state of each flash memory unit in the array is achieved.
And S4, judging whether the address overflows or not, if so, entering the step S5, and otherwise, entering the step S6.
The programming operation is performed on flash memory units, the flash memory units are sequentially programmed in a multi-level mode, the address serial numbers are continuously increased, when the address serial numbers are increased to be not corresponding to actual units, the addresses overflow, and the fact that all the units in the block complete the programming operation is shown.
And S5, finishing the programming operation of the selected block structure and finishing.
And S6, performing multi-level programming operation on the current flash memory unit according to the multi-level programming instruction, the address information and the programming level information of the target unit.
The programming level information includes an initial programming pulse voltage level, a programming pulse width.
S7, judging whether the difference between the current stage threshold voltage and the threshold voltage after the previous stage operation is not less than the preset minimum interval voltage, if so, changing address information, and entering the step S3 to perform the programming operation of the next flash memory unit; otherwise, the current flash memory cell is subjected to the multilevel programming operation again for no more than a predetermined number of times.
Since the threshold voltage interval between each two stages may not be met, the complete multi-stage programming operation is repeated. To prevent the voltage interval due to cell failure from consistently failing to meet the program forming a dead loop, it is necessary to set the maximum number of times of the multilevel programming operation, i.e., not more than a predetermined number of times.
For example, if the programming level of the target flash memory cell is 4, the level 1 programming, the level 2 programming, the level 3 programming, and the level 4 programming are required in sequence. Finishing the level 1 programming, and comparing the difference value of the threshold voltage after the level 1 programming and the initial threshold voltage with a preset minimum interval voltage; to complete the level 2 programming, the difference between the threshold voltage after level 2 programming and the threshold voltage after level 1 programming needs to be compared with a preset minimum separation voltage, and so on. The predetermined minimum interval voltage is determined according to the characteristics of the flash memory device, and in the embodiment of the invention, the predetermined minimum interval voltage is Δ V in fig. 31、ΔV2、ΔV3And Δ V4To the minimum value in between.
Finally, all cells in the three-dimensional flash memory array are set to the desired state by the multi-level programming instructions.
The bulk erase operation of the block is performed first, and then the pulse program operation of the target number of stages is sequentially performed on the individual flash memory cells. The programming operation for single-level data storage employs a two-cycle approach of pulse amplitude increment and pulse width increment. This method enables the threshold voltage of the memory cell to be accurately programmed to a predetermined value and the stored charge to have a narrow spatial distribution in the storage layer.
As shown in FIG. 4, a pulse train of gradually increasing amplitude is applied to the cell, where Δ V is the increase in amplitude, from a preset maximum amplitude (P)MCorresponding voltage amplitude) and maximum cycleThe number of times (M) is determined together. After each programming pulse, a verify voltage of appropriate magnitude is applied to determine the magnitude of the threshold voltage of the cell after the programming pulse has been applied.
The verifying voltage is not changed in the first-level programming process, the programming level is changed, the verifying voltage amplitude is changed and is between the two-level programming voltage, and the pulse width is not changed in the whole process.
As shown in FIG. 5, a pulse sequence with gradually increasing pulse width is applied to the cell, where Δ t is the increase in pulse width from a preset maximum pulse width (P)NCorresponding pulse width) and the maximum number of cycles (N). After each programming pulse, a verify voltage of appropriate magnitude is applied to determine the magnitude of the threshold voltage of the cell after the programming pulse has been applied.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. A three-dimensional flash memory array unit operation method with variable programming progression is characterized in that the method is based on a quadrilateral memory unit structure with different dielectric layer thicknesses, and the method comprises the following steps:
s1, receiving an erasing operation instruction and block structure address information;
s2, performing integral erasing operation with a verification function on the selected block structure according to the erasing instruction and the block structure address information;
s3, receiving a multi-level programming instruction and address information of a target unit, wherein the target unit is a single flash memory unit;
s4, judging whether the target unit address overflows or not, if so, entering a step S5, otherwise, receiving programming level information of the target unit, and entering a step S6;
s5, finishing the programming operation of the selected block structure and finishing the operation;
s6, performing multi-level programming operation on the current flash memory unit according to the multi-level programming instruction, the target unit address information and the programming grade information of the target unit;
s7, judging whether the difference between the current stage threshold voltage and the threshold voltage after the previous stage operation is not less than the preset minimum interval voltage, if so, changing address information, and entering the step S3 to perform the programming operation of the next flash memory unit; otherwise, the current flash memory cell is subjected to the multilevel programming operation again for no more than a predetermined number of times.
2. The method of claim 1, wherein the amount of electron storage jumps as the programming voltage increases, resulting in 4 different high threshold voltage regions, corresponding to 4 data states.
3. The method of claim 2, wherein a combination of an erased state and any 3 data states is selected, or wherein data states of 4 high threshold regions are used directly, represented by programming levels of 2 bits, each corresponding to a data state.
4. The method of claim 1, wherein the programming level information comprises an initial programming pulse voltage level and a programming pulse width.
5. The method of claim 1, wherein the programming operation for single level data storage is performed in a dual cycle manner with pulse amplitude increment and pulse width increment.
6. The method of claim 5, wherein the pulse amplitude increments are specifically: applying a pulse sequence with gradually increased amplitude to the unit, wherein the delta V is the amplitude increment and is determined by the preset maximum amplitude and the maximum cycle number; after each programming pulse, a verify voltage of appropriate magnitude is applied to determine the magnitude of the threshold voltage of the cell after the programming pulse has been applied.
7. The method of claim 5, wherein the pulse width increments are specifically: and applying a pulse sequence with gradually increased pulse width to the cell, wherein delta t is the pulse width increment and is determined by the preset maximum pulse width and the maximum cycle number, and applying a verification voltage with proper amplitude after each programming pulse to determine the threshold voltage of the cell after the programming pulse acts.
8. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the method of operating a three-dimensional flash memory array cell of any of claims 1 to 7.
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