CN109903799A - A kind of three-dimensional flash memory array element operating method of variable program series - Google Patents
A kind of three-dimensional flash memory array element operating method of variable program series Download PDFInfo
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Abstract
The invention discloses a kind of three-dimensional flash memory array element operating methods of variable program series, comprising: S1. receives erasing operation instruction and address information；S2. erasing operation is carried out to selected block structure；S3. multiple level programming instruction and address information are received；S4. judge whether address overflows, if so, otherwise, the programming series information of object element is received, into S6 into S5；S5. the programming operation for selecting block structure is completed, and is terminated；S6. according to multiple level programming instruction, the programming series information of address information and object element, multiple level programming operation is carried out to current flash unit；S7. whether the difference of judgment threshold voltage is not less than preset minimum interval voltage, if so, change address information carries out the programming operation of next flash cell into S3；Otherwise, the multiple level programming for carrying out not more than pre-determined number to current flash unit again operates.The present invention carries out the programming of target series to flash cell, so that its threshold voltage is accurate to predetermined value, to accurately control its data mode.
Description
Technical field
The invention belongs to technical field of semiconductor memory, more particularly, to a kind of three-dimensional flash memory of variable program series
Array element operating method.
Background technique
Flash memory (Flash) can be divided into two class of nand flash memory and NOR flash memory as a kind of nonvolatile memory.NOR
Each storage unit of flash memory is independently connect with bit line and wordline, therefore shows good random storage characteristic, nand flash memory
Multiple storage units be cascaded progress, thus show good Integrated Trait, be usually used in the reality of high density flash memory array
It is existing.With the reduction of characteristic size, the flash array of planar structure will be in face of closing on unit crosstalk exacerbation, floating gate storage electronics
The problems such as number is very few.In order to continue to improve storage density, the flash array of three-dimensional perpendicular stacked structure is developed.
Three-dimensional perpendicular NAND storage string is first public in 2001, and still, this each unit of NAND storage string can only
Store a data.Multilevel storage is one of the effective means of capacity extensions for realizing memory.In storage unit, there are multiple
When state, how the programming series of each unit has great importance in accuracy controlling array.
Patent CN104269407A discloses a kind of non-volatile high density three dimensional semiconductor memory device and preparation method thereof,
It is modified the symmetrical structure of conventional flash memory string, has reached barrier dielectric layer in all directions by asymmetrical form
The different effect of thickness realizes charge storage layer amount of charge stored and increases, a storage unit with the increase of write-in voltage
Two bits can at least be deposited.However, the patent is not described the implementation method of multilevel storage.
Summary of the invention
In view of the drawbacks of the prior art, it is an object of the invention to solve the prior art to be not directed to multilevel storage implementation
The technical issues of.
To achieve the above object, in a first aspect, the embodiment of the invention provides a kind of three-dimensional flash memories of variable program series
Array element operating method, based on the different quadrangle memory cell structure of thickness of dielectric layers, this method includes this method
Following steps:
Step S1. receives erasing operation instruction and address information；
Step S2. carries out the erasing for having authentication function to selected block structure according to the erasing instruction and address information
Operation；
Step S3. receives multiple level programming instruction and address information；
Step S4. judges whether address overflows, if so, entering step S5, otherwise, receives the programming series letter of object element
Breath, enters step S6；
The programming operation that step S5. selectes block structure is completed, and is terminated；
Step S6. is according to multiple level programming instruction, the programming series information of address information and object element, to current flash list
Member carries out multiple level programming operation；
Whether step S7. judges the difference of the threshold voltage after current series threshold voltage and upper level operation not less than default
Minimum interval voltage, if so, change address information, enter step S3, carry out the programming operation of next flash cell；It is no
Then, the multiple level programming for carrying out not more than pre-determined number to current flash unit again operates.
Specifically, Electronic saving amount is jumped with the increase of program voltage, generates 4 different high threshold voltage areas
Domain, corresponding 4 data modes.
Specifically, the combination of selective erasing state and any 3 data modes, alternatively, directly using 4 high-threshold regions
Data mode, with 2bit programming series expressions, each programming series corresponds to a kind of data mode.
Specifically, programming series information includes initial program pulse voltage swing, programming pulse pulsewidth.
Specifically, the Two-way Cycle side that the programming operation of single level data storage is incremented by using pulse amplitude and pulse width is incremented by
Formula.
Specifically, the pulse amplitude is incremented by specifically: applies the increased pulse train of amplitude gradual change to unit, wherein
△ V is amplitude incrementss, is codetermined by default maximum amplitude and maximum cycle；After each programming pulse, apply
The verifying voltage of suitable amplitude determines the threshold voltage size of unit after programming pulse effect.
Specifically, the pulse width is incremented by specifically: applies the increased pulse train of pulsewidth gradual change to unit, wherein
△ t is pulsewidth incrementss, is codetermined by default maximum pulse width and maximum cycle, after each programming pulse, is applied
The verifying voltage of suitable amplitude determines the threshold voltage size of unit after programming pulse effect.
Second aspect, the embodiment of the invention provides a kind of computer readable storage medium, the computer-readable storage mediums
Computer program is stored in matter, which realizes three-dimensional flash memory described in above-mentioned first aspect when being executed by processor
Array element operating method.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, have below beneficial to effect
Fruit:
The whole erasing operation of the advanced row block structure of the present invention, then successively carries out target series to single flash cell
Pulse programming operation, each programming series correspond to a kind of data mode, realize multilevel storage, three-dimensional flash memory battle array by multiple level programming
All units in column are set to the state needed.This method enables the threshold voltage of storage unit accurately to program
To predetermined value, and make the charge of storage that there is relatively narrow spatial distribution in accumulation layer, is finally reached every in accurate control array
The effect of a flash cell state, and guarantee certain interval between multivalue state.
Detailed description of the invention
Fig. 1 is three-dimensional flash memory array periphery electrical block diagram provided in an embodiment of the present invention；
Fig. 2 is a kind of three-dimensional flash memory array element operating method process of variable program series provided in an embodiment of the present invention
Figure；
Fig. 3 is the threshold voltage distribution schematic diagram of storage unit provided in an embodiment of the present invention；
Fig. 4 is the increased programming operation process schematic of pulse amplitude gradual change provided in an embodiment of the present invention；
Fig. 5 is the increased programming operation process schematic of pulsewidth gradual change provided in an embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
As shown in Figure 1, microprocessor control erasing control unit sends erasing instruction, and controls when carrying out erasing operation
Address information writing address decoder, control driving voltage generator generate voltage drive signals (erasing voltage), finally by
Read/write circuit carries out erasing operation to selected block structure.After the completion of selected block structure erasing operation, detection control unit
The state of different flash memory strings in 3D storage array is successively gated and verified with counting control unit.If state is qualified, it is erased into
Function changes erasing voltage if state is unqualified, carries out the erasing operation of block structure again, continues to verify later.It is proved to be successful
Later, it is programmed operation.Microprocessor controls programming Control unit and sends multiple level programming instruction, and controls address information write-in
Address decoder, control driving voltage generator generate voltage drive signals, carry out finally by read/write circuit to selected unit
Multiple stage circulation programming operation.
As shown in Fig. 2, a kind of three-dimensional flash memory array element operating method of variable program series, this method is with medium thickness
It spends based on different quadrangle memory cell structures, method includes the following steps:
Step S1. receives erasing operation instruction and address information；
Step S2. carries out the erasing for having authentication function to selected block structure according to the erasing instruction and address information
Operation；
Step S3. receives multiple level programming instruction and address information；
Step S4. judges whether address overflows, if so, entering step S5, otherwise, receives the programming series letter of object element
Breath, enters step S6；
The programming operation that step S5. selectes block structure is completed, and is terminated；
Step S6. is according to multiple level programming instruction, the programming series information of address information and object element, to current flash list
Member carries out multiple level programming operation；
Whether step S7. judges the difference of the threshold voltage after current series threshold voltage and upper level operation not less than default
Minimum interval voltage, if so, change address information, enter step S3, carry out the programming operation of next flash cell；It is no
Then, the multiple level programming for carrying out not more than pre-determined number to current flash unit again operates.
Step S1. receives erasing operation instruction and address information.
Control unit receives erasing instruction, and address decoder receives address information.
Step S2. carries out the erasing for having authentication function to selected block structure according to the erasing instruction and address information
Operation.
The object of erasing operation is selected block structure.Flash memory first completes the data mode that erasing operation reaches unified, is convenient for
Multiple level programming operates the accuracy controlling to flash data state.
Step S3. receives multiple level programming instruction and address information.
After being proved to be successful, control unit receives multiple level programming instruction, and address decoder receives address information.Multiple level programming
State comprising the setting of target flash unit in instruction.
As shown in figure 3, Electronic saving amount is with programming due to the quadrangle memory cell structure different using thickness of dielectric layers
The increase of voltage jumps, thus can produce the high threshold region of 4 narrow distributions, corresponding 4 data modes, respectively
For 101,102,103,104 in Fig. 1, in addition the initial erase status 100 of unit, totally 5 data modes.Carry out 2 bits
Data storage only needs 4 states, thus the combination of erasing state (E) and any 3 data modes may be selected, alternatively, directly using 4
The data mode (P1, P2, P3, P4) of a high-threshold region, the data of composition 2bit.Embodiment of the present invention is to cubical array
In each flash cell different programming series is set, each programming series corresponds to a kind of data mode, passes through multiple level programming
It realizes multilevel storage, is finally reached the effect of each flash cell state in accurate control array.
Step S4. judges whether address overflows, if so, entering step S5, otherwise, enters step S6.
The object of programming operation is flash cell, successively carries out multiple level programming to flash cell, and address serial number constantly becomes larger,
When address, serial number increases to no actual cell and overflows to address when corresponding to, and illustrates that unit all in block at this time is completed
Programming operation.
The programming operation that step S5. selectes block structure is completed, and is terminated.
Step S6. is according to multiple level programming instruction, the programming series information of address information and object element, to current flash list
Member carries out multiple level programming operation.
Programming series information includes initial program pulse voltage swing, programming pulse pulsewidth.
Whether step S7. judges the difference of the threshold voltage after current series threshold voltage and upper level operation not less than default
Minimum interval voltage, if so, change address information, enter step S3, carry out the programming operation of next flash cell；It is no
Then, the multiple level programming for carrying out not more than pre-determined number to current flash unit again operates.
Due to the threshold voltage interval between every two-stage be likely to it is not up to standard, so to re-start complete multiple level programming
Operation.In order to prevent because voltage spaces caused by cell failure are not up to standard always, program forms endless loop, needs to set weight multistage
The maximum times of programming operation require to be not more than pre-determined number.
For example, the programming series of target flash unit is 4, then needing successively to carry out 1 grade of programming, 2 grades of programmings, 3 grades of volumes
Journey, 4 grades of programmings.Complete 1 grade programming, need to compare 1 grade programming after the difference of threshold voltage and initial threshold voltage with it is preset
Minimum interval voltage；Complete 2 grades programming, need to compare 2 grades programming after threshold voltage and 1 grade programming after threshold voltage difference with
Default minimum interval voltage, and so on.Preset minimum interval voltage is determined according to the characteristic of flush memory device, the present invention
Preset minimum interval voltage takes Δ V in Fig. 3 in embodiment1、ΔV2、ΔV3With Δ V4Between minimum value.
Finally, it is instructed by multiple level programming, all units in three-dimensional flash memory array are set to the state needed.
The whole erasing operation of advanced row block, the pulse program for then successively carrying out target series to single flash cell are grasped
Make.The Two-way Cycle mode that the programming operation of single level data storage is incremented by using pulse amplitude and pulse width is incremented by.This method
The threshold voltage of storage unit is set accurately to be programmed into predetermined value, and it is relatively narrow to have the charge of storage in accumulation layer
Spatial distribution.
As shown in figure 4, applying the increased pulse train of amplitude gradual change to unit, wherein △ V is amplitude incrementss, by pre-
If maximum amplitude (PMCorresponding voltage magnitude) and maximum cycle (M) co-determination.After each programming pulse, apply
The verifying voltage of suitable amplitude determines the threshold voltage size of unit after programming pulse effect.
Verifying voltage is constant, change programming series, verifying voltage amplitude change, in two in level-one programming process
Between grade program voltage, pulsewidth is constant in the whole process.
As shown in figure 5, applying the increased pulse train of pulsewidth gradual change to unit, wherein △ t is pulsewidth incrementss, by pre-
If maximum pulse width (PNCorresponding pulse width) and maximum cycle (N) co-determination.After each programming pulse, apply
The verifying voltage of suitable amplitude determines the threshold voltage size of unit after programming pulse effect.
More than, the only preferable specific embodiment of the application, but the protection scope of the application is not limited thereto, and it is any
Within the technical scope of the present application, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
Cover within the scope of protection of this application.Therefore, the protection scope of the application should be subject to the protection scope in claims.
Claims (8)
1. a kind of three-dimensional flash memory array element operating method of variable program series, which is characterized in that this method is with medium thickness
It spends based on different quadrangle memory cell structures, method includes the following steps:
Step S1. receives erasing operation instruction and address information；
Step S2. carries out the erasing operation for having authentication function to selected block structure according to the erasing instruction and address information；
Step S3. receives multiple level programming instruction and address information；
Step S4. judges whether address overflows, if so, entering step S5, otherwise, receives the programming series information of object element,
Enter step S6；
The programming operation that step S5. selectes block structure is completed, and is terminated；
Step S6. instructs according to multiple level programming, the programming series information of address information and object element, to current flash unit into
The operation of row multiple level programming；
Step S7. judge current series threshold voltage and upper level operation after threshold voltage difference whether not less than it is preset most
Closely-spaced voltage, if so, change address information, enters step S3, carry out the programming operation of next flash cell；Otherwise, weight
The multiple level programming for newly carrying out not more than pre-determined number to current flash unit operates.
2. three-dimensional flash memory array element operating method as described in claim 1, which is characterized in that Electronic saving amount is with programming electricity
The increase of pressure jumps, and generates 4 different high threshold regions, corresponding 4 data modes.
3. three-dimensional flash memory array element operating method as claimed in claim 2, which is characterized in that selective erasing state and any 3
The combination of a data mode, alternatively, the data mode of 4 high-threshold regions is directly used, with 2bit programming series expressions,
Each programming series corresponds to a kind of data mode.
4. three-dimensional flash memory array element operating method as described in claim 1, which is characterized in that programming series information includes just
Beginning programming pulse voltage swing, programming pulse pulsewidth.
5. three-dimensional flash memory array element operating method as described in claim 1, which is characterized in that the programming of single level data storage
The Two-way Cycle mode that operation is incremented by using pulse amplitude and pulse width is incremented by.
6. three-dimensional flash memory array element operating method as claimed in claim 5, which is characterized in that the pulse amplitude is incremented by tool
Body are as follows: the increased pulse train of amplitude gradual change is applied to unit, wherein △ V is amplitude incrementss, by default maximum amplitude and most
Systemic circulation number codetermines；After each programming pulse, apply the verifying voltage of suitable amplitude, determines that programming pulse acts on
The threshold voltage size of unit afterwards.
7. three-dimensional flash memory array element operating method as claimed in claim 5, which is characterized in that the pulse width is incremented by tool
Body are as follows: the increased pulse train of pulsewidth gradual change is applied to unit, wherein △ t is pulsewidth incrementss, by default maximum pulse width and most
Systemic circulation number codetermines, and after each programming pulse, applies the verifying voltage of suitable amplitude, determines that programming pulse acts on
The threshold voltage size of unit afterwards.
8. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program, the computer program realize three-dimensional flash memory array list as described in any one of claim 1 to 7 when being executed by processor
Atom operation method.
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| US11250910B2 (en) | 2020-05-06 | 2022-02-15 | Yangtze Memory Technologies Co., Ltd. | Control method and controller of a programming process for 3D NAND flash |
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