CN109889045B

CN109889045B - Method for restraining current overshoot of DC/DC converter with valley current control during light load

Info

Publication number: CN109889045B
Application number: CN201910300959.XA
Authority: CN
Inventors: 李征
Original assignee: Nanjing Rongxin Microelectronic Co ltd
Current assignee: NANJING RONGXIN MICROELECTRONIC Co.,Ltd.
Priority date: 2019-04-15
Filing date: 2019-04-15
Publication date: 2021-06-29
Anticipated expiration: 2039-04-15
Also published as: CN109889045A

Abstract

The invention provides a method for restraining current overshoot of a DC/DC converter with valley current control under light load, which needs an Oscillator (Oscillator) with a period which can not be constant, the period of the Oscillator is not constant under the condition that the light load needs a skip period, in a period in which a PWM signal is generated, a period of an Oscillator (Oscillator) is varied according to a temporal variation in the generation of the PWM signal, the number of hop periods in light load is not necessarily an integer multiple of the period in freewheel mode, and may be any value, compared with the working mode of the traditional step-down DC/DC converter controlled by valley bottom current, the invention not only can ensure the device performance under light load, but also can improve the dynamic corresponding speed, inhibit the overshoot of inductive current, greatly reduce the corresponding ripple of output Voltage (VOUT), and simultaneously protect the input low voltage protection of a downstream chip to keep stable.

Description

Method for restraining current overshoot of DC/DC converter with valley current control during light load

Technical Field

The present invention relates to electronic components, semiconductors, and integrated circuits, and more particularly, to a method for suppressing current overshoot in a valley-bottom current controlled DC/DC converter during light load.

Background

The operation principle of the step-down DC/DC converter in the valley current mode is similar to that in the peak current mode. The difference is that the lower tube is turned off by a clock CLK signal in a peak current mode, the upper tube is turned on, the current of the upper tube is sampled and compared with the output COMP of the transconductance amplifier, and after the PWM signal is triggered, the upper tube is turned off and the lower tube is turned on. And in the valley current mode, the upper tube is turned off by a clock CLK signal, the lower tube is opened, the current of the lower tube is sampled and compared with the output COMP of the transconductance amplifier, and after a PWM signal is triggered, the lower tube is turned off and the upper tube is turned on. The same point is that the current RAMP used to trigger the PWM signal is the sampled current plus slope compensation. Fig. 1 is a schematic diagram of a conventional buck DC/DC converter, and fig. 2 is a waveform diagram of a valley current mode and a peak current mode of the conventional buck DC/DC converter.

In either mode, negative currents are generally avoided to improve conversion efficiency in the case of very light loads. The current zero point detection of the lower tube can turn off the lower tube when the current is reduced to be close to 0A, so that the current stops at 0A and cannot become negative. Thus, the cutoff mode is entered. Because the valley bottom current mode is the current of sampling lower tube, after the disconnection, the sampling current is not changed any more, and the sampling value when the disconnection is kept until the next triggering. At the same time, slope compensation is also stopped and the compensation value at turn-off is maintained. Since neither of these two components of the current is changing. Therefore, the entire current ramp remains constant. Triggering the next PWM signal can only slowly reduce the output Voltage (VOUT) through the load until the feedback voltage is lower than the reference voltage, thereby causing the output of the transconductance amplifier to change, forming a ramp wave with a small slope, and intersecting with a current ramp wave which is kept unchanged. The PWM interval is longer and longer as the load is reduced, which means that the DC/DC interval is separated by many clock cycles before the tube is switched on and off once. This results in a skip cycle mode of operation in valley bottom current mode under light load.

At present, the contradiction that the dynamic response of the DC/DC converter and the inductor current overshoot cannot be compatible exists in the operation mode, as shown in fig. 3, the output of the transconductance amplifier with slow change and the constant current ramp wave may meet at any time point, because the lighter the load is, the longer the time for stopping the switch is, the more the cycle for jumping is, and because the load is continuously changed, the time for stopping the switch is also continuously increased, the cycle for jumping is not necessarily an integer, and may jump 4.5 cycles. Fig. 4 is a flowchart of the operation of this case. The working steps of this case are described below:

step 1: the lower tube (LSON = 1) is in the on state, while the upper tube (HSON = 0) is in the off state;

step 2: until the inductor current is negative (LS 0x = 1), executing step 3, otherwise executing step 1;

and 3, step 3: turn off the down tube (LSON = 0);

and 4, step 4: until the inductor current stops changing;

and 5, step 5: the current RAMP (RAMP) stops falling and keeps the current value, meanwhile, the output Voltage (VOUT) slowly falls, and the output (COMP) of the transconductance amplifier slowly rises;

and 6, step 6: when the output of the transconductance amplifier is larger than the current ramp wave, executing the step 7, and stopping executing the step 3;

and 7, step 7: generating a PWM signal (PWM = 1);

and 8, step 8: opening the upper tube (HSON = 1);

step 9: if a clock rising edge occurs (CLK = 1), step 1 is executed, whereas step 8 is executed, and remains on until the next cycle of the CLK signal.

As shown in fig. 3, the long time the upper tube is open (which theoretically could be 99% open cycle) can cause an overshoot of the inductor current, and the ripple of the output Voltage (VOUT) response can be large, thereby affecting the performance of the downstream circuit.

The solution is to allow the upper tube to open for a fixed time only in case of a skip cycle, and the fixed open time needs to be relatively short no matter when the PWM signal is triggered, which does not cause current overshoot, and the ripple of the output voltage is within the allowable range. The realized method, as shown in fig. 5, generally delays to approach the next CLK clock signal, then opens for a relatively short time, and then the CLK signal turns off the CLK clock signal, and opens the down tube, and the delay ensures that the skipped period is an integral multiple of the original period, and generally does not cause a significant increase in ripple, because a light load does not have a great influence on the output voltage in a short time, although the design ensures the performance under a light load, the worst is that the dynamic response speed is slowed down.

The working steps of this case, as shown in fig. 6, are described as follows:

and 3, step 3: turn off the down tube (LSON = 0);

and 4, step 4: until the inductor current stops changing;

and 7, step 7: generating a PWM signal (PWM = 1);

and 8, step 8: if the rising edge of the CLK approaches, executing the step 9, otherwise, continuing to wait;

step 9: opening the upper tube (HSON = 1);

step 10: if a clock rising edge occurs (CLK = 1), step 1 is executed, whereas step 9 is executed.

As shown in fig. 5, in the case of a skip cycle, sudden loading occurs, the output voltage decreases, the output of the transconductance amplifier no longer changes slowly, when the output changes rapidly and meets a current ramp, a PWM signal is generated, an upper tube needs to be opened immediately, and no delay occurs, otherwise the output voltage is pulled lower by a heavy load, and we intentionally increase the delay for light load performance, which causes the output voltage to be pulled lower more, which not only harms dynamic response, but also may trigger the input low voltage protection of a downstream chip to cause shutdown in an extreme case.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: for the valley bottom current mode, a method is designed which can take into account both the skip cycle without current overshoot and the dynamic response without delay in the light load mode, and this can be achieved by dynamically adjusting the CLK cycle.

A method for suppressing current overshoot during light load of a DC/DC converter with valley current control comprises an oscillator with a non-constant period, wherein the period of the oscillator is not constant under the condition that a light load needs a skip period, and the period of the oscillator is changed according to the time change generated by a PWM signal in the period for generating the PWM signal, so that the skip period number during light load is not necessarily integral multiple of the period during free-wheeling mode and can be any value.

Further, the DC/DC converter includes at least one semiconductor device with a top-tube, HSON being a waveform signal of the top-tube, and in a steady state of a light load, when the PWM signal is generated, the HSON signal goes high immediately and turns on the top-tube for a fixed time, which is usually short, so as not to cause an over-charging of the inductor current or an excessive ripple of the output Voltage (VOUT).

Further, the DC/DC converter includes at least one semiconductor device down tube, the oscillator generates a clock signal immediately after the PWM signal turns on the up tube for a fixed short time, the down tube is turned on, and a time point of generating the clock signal is determined by a time point of the PWM signal.

Further, when the load suddenly gets heavier, the PWM signal is generated, the HSON signal immediately goes high, and the top tube is turned on, at which time the dynamic response reflecting speed of the valley current controlled DC/DC converter is not damaged, and there is no case that the output Voltage (VOUT) continues to be pulled low by the load due to response delay, since the top tube is only conducted for a short time, the output Voltage (VOUT) cannot be immediately pulled back, then the bottom tube is conducted for a minimum time T2, then the top tube is turned on again, and can be turned on for almost the entire period, thereby starting to recover the output Voltage (VOUT).

Further, the working steps are described as follows:

and 3, step 3: turn off the down tube (LSON = 0);

and 4, step 4: until the inductor current stops changing;

and 6, step 6: when the output of the transconductance amplifier is larger than the current ramp wave, executing the step 7, otherwise, executing the step 3;

and 7, step 7: generating a PWM signal (PWM = 1);

and 8, step 8: upper tube was opened immediately (HSON = 1);

step 9: executing the step 10 when the shortest starting time of the upper tube is over, or executing the step 8;

step 10: a clock rising edge (CLK = 1) is forced and step 1 is executed back.

Compared with the working mode of the traditional step-down DC/DC converter in the valley current mode, the invention not only can ensure the device performance under light load, but also can improve the dynamic response speed, inhibit the overshoot of the inductive current, greatly reduce the ripple wave of the output Voltage (VOUT) of the response, and simultaneously protect the input low voltage protection of the downstream chip to keep stable.

Drawings

The foregoing and other objects, features and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout.

Fig. 1 is a schematic diagram of a step-down DC/DC converter.

Fig. 2 is a waveform diagram of a step-down DC/DC converter with valley current control and peak current control in freewheel mode.

Fig. 3 is a waveform diagram illustrating the operation of a conventional valley-bottom current controlled buck DC/DC converter during a light-load skip cycle.

Fig. 4 is a flow chart of the operation of a conventional valley-bottom current controlled buck DC/DC converter during light load skip cycles.

Fig. 5 is a waveform diagram of the operation of a valley current controlled buck DC/DC converter with delayed top tube on time during light load skip cycles.

Fig. 6 is a flow chart of the operation of a valley current controlled buck DC/DC converter with delayed top tube on time in light load skip cycle conditions.

Fig. 7 is a schematic diagram of an oscillator according to the present invention in which the period may not be constant.

Fig. 8 is a waveform diagram illustrating the operation of the valley bottom current controlled buck DC/DC converter of the present invention during a light-load skip cycle.

Fig. 9 is a flow chart of the operation of the inventive valley bottom current controlled buck DC/DC converter during light load skip cycles.

In FIGS. 1-9, LSON is a lower tube waveform signal; HSON is an upper tube waveform signal; LS0x is an inductor current waveform signal; VOUT Ripple is output voltage Ripple; inductor Current is the Inductor Current.

Detailed Description

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "upper tube", "lower tube", etc. indicate orientations or positional relationships based on those shown in the drawings only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referenced devices must have a particular orientation, be constructed in a particular orientation, and be operated, and thus are not to be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "first", "second", and the like are to be broadly construed, and for example, may be third, fourth, or fifth; the term may be the sixth, seventh, etc., and those skilled in the art can understand the specific meaning of the above terms in the present invention in specific situations.

In the skip cycle mode, after PWM is generated, the upper tube needs to be turned on immediately, and cannot wait for the next CLK signal, but the upper tube is turned on only for a short fixed time to prevent current overshoot, and after the short on time is finished, the lower tube needs to be turned on immediately, but the CLK signal does not yet arrive, and the lower tube cannot be turned on, so that an oscillator capable of dynamically adjusting the cycle is needed, and a waveform diagram of the CLK signal is generated forcibly, as shown in fig. 8.

The period of the oscillator is not constant in the case of a skip period, the period of the oscillator will vary according to the time variation of the PWM signal generation in the period of the PWM signal generation, and the number of skip periods may be any value, not necessarily an integer multiple of the period in the freewheel mode.

When the load suddenly increases to generate a PWM signal, the HSON signal immediately becomes high, and the upper tube in the figure 1 is immediately started, so that the dynamic response reflecting speed of the DC/DC converter controlled by the valley bottom current cannot be damaged, and the condition that the output Voltage (VOUT) is continuously pulled down by the load due to response delay cannot occur; since the upper tube is only conducting for a short time, it cannot pull the output Voltage (VOUT) back right away, then the lower tube conducts for a minimum time T2, then the upper tube turns on again and can be turned on for almost the entire cycle to begin restoring the output Voltage (VOUT).

Further, as shown in fig. 7, the oscillator, which may not be constant, includes: the device comprises an upper tube, a lower tube, a D trigger, a non-gate tube, an AND gate tube, a comparator, a constant current source, a reference voltage source and a capacitor C.

The upper tube can be a PMOS structure, and the lower tube can be an NMOS structure; the oscillator is divided into two working modes, namely a constant period mode in a free-wheeling mode and a variable period mode in a cutoff mode;

in a freewheeling mode, the and gate signal SkipMode = 0, the output of the and gate is 0, and the D flip-flop is forced to be in a reset state, the inverted output QZ of the D flip-flop = 1, the upper tube is turned off, in this case, the oscillator always charges the capacitor C through the constant current source, when the voltage of the capacitor C reaches a reference voltage Vref set by the reference voltage source, the comparator generates the first CLK clock signal (CLK = 1), then the lower tube is turned on, and the electric quantity of the capacitor C is discharged; when the voltage of the capacitor C is lower than the reference voltage Vref, CLK of the comparator is reset (CLK = 0), the lower tube is turned off, the capacitor C restarts to charge next time, and the process of charging and discharging each time is repeated to form a period of the oscillator.

In the off mode, the and gate signal SkipMode = 1, between each clock cycle, the comparator generates CLK = 0, so the output of the and gate is 1, the D flip-flop is in the triggered state, when the PWM signal (PWM = 1) is generated, the D flip-flop reversely outputs QZ = 0, the upper tube is turned on, which is equivalent to adding a huge current to charge the capacitor C, so that the capacitor voltage can be pulled up instantaneously, the comparator generates a CLK clock signal (CLK = 1), that is, the CLK clock signal is generated immediately after the PWM signal, which is earlier than the normal time point, and the lower tube is opened under the action of CLK.

Although CLK is generated immediately following the PWM signal, there is a delay T1 between them, which is mainly due to the upper tube charging the capacitor C and the delay of the comparator state flipping, which is usually short in T1 and can be directly used to define the on-time of the upper tube.

The working steps of the invention, as shown in fig. 9, are described as follows:

and 3, step 3: turn off the down tube (LSON = 0);

and 4, step 4: until the inductor current stops changing;

and 7, step 7: generating a PWM signal (PWM = 1);

and 8, step 8: upper tube was opened immediately (HSON = 1);

step 10: a clock rising edge (CLK = 1) is forced and step 1 is executed back.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic representation of terms does not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the above description has been described with NMOS and PMOS transistors, the present invention is also applicable to other types of power mosfet devices, where only P is changed to N and N is changed to P. Furthermore, the invention is equally applicable to trench power metal oxide semiconductor field effect transistor devices or IGBTs (insulated gate bipolar transistors). The present invention is not limited to the above description but may be subject to various modifications and variations, wherein different manufacturing methods and ion implantation techniques result in the same method as the device structure of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims

1. A method for suppressing current overshoot during light load of a DC/DC converter with valley current control is characterized in that the DC/DC converter comprises an oscillator with a non-constant period, the period of the oscillator is not constant under the condition that a skip period is needed during light load, the period of the oscillator is changed according to the time change generated by the PWM signal during the period for generating the PWM signal, when the PWM signal is changed from high level to low level, the clock signal output by the oscillator is forced to be changed from low level to high level, therefore, the skip period number during light load is N times of the period of the oscillator during free-wheeling mode, wherein N is an arbitrary value.

2. The method for suppressing current overshoot during light load of a valley current controlled DC/DC converter as claimed in claim 1, wherein the DC/DC converter comprises at least one semiconductor device upper tube, the HSON signal is a waveform signal of the upper tube, and in the steady state of light load, when the PWM signal is generated, the HSON signal goes high immediately, and the upper tube is turned on for a fixed time immediately, so as not to cause the inductor current to be overcharged or the output Voltage (VOUT) has an excessive ripple.

3. The method of claim 2, wherein the DC/DC converter comprises at least one semiconductor device down tube, the LSON signal is a waveform signal of the down tube, the oscillator generates a clock signal immediately after the PWM signal turns on the up tube for a fixed short time, the down tube is turned on, and a time point of generating the clock signal is determined by a time point of the PWM signal.

4. A method of suppressing current overshoot at light load in a valley current controlled DC/DC converter as claimed in claim 3, when the load suddenly gets heavier, the PWM signal is generated, the HSON signal goes high immediately and turns on the top tube, the top tube is only conducting for a short time, then the bottom tube is conducting for a minimum time T2, then the top tube is turned on again and can be turned on for almost the entire period to start recovering the output Voltage (VOUT).

5. The method for suppressing the current overshoot of the valley bottom current controlled DC/DC converter according to claim 4, wherein the operation steps are described as follows:

step 1: the lower tube is in an on state, LSON = 1, and the upper tube is in an off state, HSON = 0;

step 2: until the inductor current is negative, LS0x = 1, executing the step 3, otherwise executing the step 1;

and 3, step 3: turn off down tube, LSON = 0;

and 4, step 4: until the inductor current stops changing;

generating a PWM signal, PWM = 1;

and 7, step 7: immediately starting an upper pipe, and HSON = 1;

and 8, step 8: executing the step 10 when the shortest starting time of the upper tube is over, or executing the step 8;

step 9: forcibly generating a clock rising edge, wherein CLK = 1, and returning to execute the step 1;

the HSON signal is a waveform signal of the upper tube;

the LSON signal is a waveform signal of the lower tube;

the LS0x signal is an inductor current signal.