CN109884493B

CN109884493B - Tunneling double-gate field effect transistor (T-FinFET) characteristic drain voltage extraction method

Info

Publication number: CN109884493B
Application number: CN201910259948.1A
Authority: CN
Inventors: 何进; 任源; 李春来; 胡国庆; 刘京京; 潘俊; 王小萌; 何箫梦; 于胜
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2019-04-02
Filing date: 2019-04-02
Publication date: 2021-07-09
Anticipated expiration: 2039-04-02
Also published as: CN109884493A

Abstract

The invention relates to a method for extracting a characteristic drain voltage of a T-FinFET (field effect transistor) suitable for a tunneling double-gate field effect transistor, which comprises the following steps of: three points of different drain-source voltages Vds are selected, the gate-source voltage Vgs is scanned from +0.5V to +2.0V, a transfer current characteristic curve Ids-Vgs of the field effect transistor is tested, and the normal work of the device is determined; three points of different Vgs are selected, Vds is scanned from 0V to +2.0V, and an output current characteristic curve Ids-Vds of the field effect transistor is tested; selecting two points in the linear region to connect as a straight line, obtaining the intercept of the corresponding straight line on a drain voltage axis, thus obtaining the cross turning point voltage of the linear region and the exponential region of the T-FinFET under different gate voltages, obtaining an output conductance characteristic curve Gout-Vds, then selecting two points in the linear region to connect as a straight line, thus extracting the cross turning point voltage of the linear region and the saturation region of the T-FinFET under different gate voltages. The method is simple to realize, is insensitive to the structure and the process of the device under low Vgs and Vds, and can inhibit the short channel effect and the ultrathin body effect caused by a small-size device.

Description

Tunneling double-gate field effect transistor (T-FinFET) characteristic drain voltage extraction method

The technical field is as follows:

the invention belongs to the technical field of integrated circuits, relates to a method for extracting a characteristic drain voltage of a field effect transistor, and particularly relates to a method for extracting a characteristic drain voltage of a nano tunneling double-gate field effect transistor (T-FinFET).

Background art:

as integrated circuit technology rapidly advances to the deep nanometer era, FinFET field effect transistors have been applied in large scale on 14-7 nanometer generation chip products with their good short channel effects and powerful gating capabilities. However, as the integration density of integrated circuits is higher and smaller, the short channel effect and power consumption become serious challenges to limit the further development of the nano chip. From the technical limit: the degradation of switching characteristics with increasing subthreshold slope and the increase of power tunneling are bottlenecks that limit 7-3 nm integrated circuits, and the traditional FinFET process and circuit design face serious challenges. With the development of chip technology towards 5nm generation and below, the FinFET structure with new working mechanism is the key to solve the contradiction between high speed and power consumption.

The nano tunneling FinFET (T-FinFET) is compatible with Moore's law, has the advantages of breaking through the CMOS subthreshold limit, enhancing the short channel effect and the like, and is the most possible next CMOS generation choice for solving the ultra-low power consumption and high speed restriction of an integrated circuit below 7 nanometers. The T-FinET adopts a new tunneling mechanism to realize the device conduction, breaks through the limit of 60mV/dec of the conventional and non-conventional CMOS sub-threshold slope at normal temperature, reduces the leakage current, can obtain higher conduction current and switch current ratio under the condition of extremely low power supply voltage, has better application prospect in the low power consumption application field in the future, and also obtains preliminary experimental verification and theoretical analysis on the aspects of process, integrated circuit application and the like. It appears that using well-established generic FinFET geometries on silicon nano-CMOS platforms, with new process technologies developed, the replacement of CMOS or CMOS integrated HYBRID CMOS in part is a viable approach for T-finfets into mainstream integrated circuits.

From the aspects of circuit principle and geometry, the working mechanism of the T-FinFET is the series connection of a tunneling P-N junction and the FinFET, and the tunneling P-N junction and the FinFET dominate different Ids-Vds regions under different bias voltages, so that the output curve of the T-FinFET is different from the characteristics of the traditional FinFET: as the drain voltage Vds increases from zero, an exponential region that tunnels the P-N junction dominates the current first appears, then the linear region and the final saturation region of the FinFET appear in sequence, as shown in fig. 3 for the regions and their turning points. On the output curve of the T-FinFET, the turning intersection point between the exponential region and the linear region is generally called bias drain voltage Vdoffset, which is the difference of the T-FinFET from the traditional FinFET and adds a characteristic bias drain voltage; the turning intersection between the linear and saturation regions of a T-FinFET is commonly referred to as the saturation drain voltage, Vdsat, which is where the T-FinFET shares a common saturation drain voltage with a conventional FinFET.

If the T-FinFET circuit is required to have high design precision, short period, low cost and few design errors, the characteristic drain voltage is used as a key parameter for representing the output characteristic of the T-FinFET, and accurate extraction and accurate representation have decisive significance for ensuring the successful design of the circuit function. There are many well-defined and extracted methods for the characteristic drain voltage of a general double-gate field effect transistor (FinET), but due to the special physical mechanism of the T-FinFET, the proposed method research and practice for the characteristic drain voltage of the T-FinFET is lacked at present. Meanwhile, due to the extremely thin body region and the extremely short channel length of the T-FinFET, the characteristic drain voltage is easily influenced by a short channel effect and an ultrathin body, so that the extraction result is very sensitive to the bias voltage and the process fluctuation, and the accuracy of the extraction result is influenced. Therefore, the invention provides a method for extracting the characteristic drain voltage of the nano T-FinFET, which has application significance to circuit design and device characteristic characterization based on the T-FinFET.

The invention content is as follows:

the technical problem to be solved by the invention is how to provide a method for extracting the characteristic drain voltage of a tunneling double-gate field effect transistor (T-FinFET), which can greatly reduce or eliminate the influence of a bias condition and a small-size effect.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a method for extracting the characteristic drain voltage of a tunneling field effect transistor (T-FET), in particular the tunneling field effect transistor (T-FinFET), is constructed, and comprises the following steps:

1) three points of different drain-source voltages Vds are selected, the gate-source voltage Vgs is scanned from +0.5 volt to +2.0 volt, a transfer current characteristic curve Ids-Vgs of the T-FinFET is tested, and the normal work of the device is determined.

2) Three points of different gate-source voltages Vgs are selected, Vds is scanned from 0 volt to +2.0 volts, and an output current characteristic curve Ids-Vds of the T-FinFET is tested; two optional points in the linear region are connected into a straight line, and the intercept of the corresponding straight line on a drain voltage axis is obtained, so that the cross turning point voltage of the linear region and the exponential region of the T-FinFET under different gate voltages, namely the offset drain voltage VdOffset, is obtained.

3) The drain-source output current Ids is differentiated with Vds to obtain an output conductance characteristic curve Gout-Vds; and then connecting two optional points in the linear region of the conductance characteristic curve into a straight line, and acquiring the intercept of the corresponding straight line on a drain voltage axis, thereby extracting the voltage of the cross turning point of the linear region and the saturation region of the T-FinFET under different gate voltages, namely the saturation drain voltage Vdsat.

Preferably, according to the extraction method provided by the invention, the three different drain-source voltages Vds are 0.1V, 0.5V and 1.0V, respectively.

Preferably, according to the extraction method provided by the invention, the three different gate-source voltages Vgs are 1.0V, 1.3V and 1.5V, respectively.

Preferably, according to the extraction method provided by the present invention, the tunneling field effect transistor includes, but is not limited to, a nano T-FinFET field effect transistor.

The method for extracting the characteristic drain voltage of the tunneling field effect transistor (T-FinFET) is improved on the basis of the output current characteristic of the FinFET, and the characteristic drain voltage of the nano T-FinFET is accurately extracted by extrapolation of the output characteristic. The method has the advantages of high accuracy, simplicity in operation, small influence by doping and small-size effects, and suitability for extracting small-size devices, especially characteristic drain voltage of T-FinFET.

Drawings

The invention is further described in detail below with reference to the following figures and specific examples:

FIG. 1 is a schematic diagram of a nano T-FinFET field effect transistor structure and test;

FIG. 2 is a T-FinFET transfer current characteristic Ids-Vgs curve for different gate-drain voltages Vds;

FIG. 3 is a T-FinFET output current characteristic Ids-Vds for different gate-source voltages Vgs;

FIG. 4 is a T-FinFET output conductance profile Gout-Vds for different gate-source voltages Vgs;

in the figure: the grid electrode 1, the source electrode 2, the drain electrode 3, the substrate 4 and the grid oxide layer 5;

Detailed Description

The invention will now be further illustrated by reference to the following specific examples, but the invention includes, but is not limited to, the following examples:

the specific embodiment uses an output current and conductance extrapolation method to extract the characteristic drain voltage of the nano T-FinFET field effect transistor, and the specific process comprises the following steps:

1) preparing a nano T-FinFET to be tested, wherein the specific test structure of the nano T-FinFET is shown in figure 1, a grid electrode 1, a source electrode 2, a drain electrode 3, a substrate 4 and a gate oxide layer 5 are arranged, the grid electrode 1 is provided with grid electrode potential, the drain electrode 3 is provided with drain electrode potential, the source electrode 2 is provided with source electrode potential, two grid electrode potential differences on a grid electrode potential shaft form grid electrode voltage, two source electrode potential differences on a source electrode potential shaft form source electrode voltage, and two drain electrode potential differences on a drain electrode potential shaft form drain electrode voltage; the potential difference between the gate potential and the source potential forms a gate-source voltage, and the potential difference between the drain potential and the source potential forms a drain-source voltage.

2) As shown in fig. 2, the gate-source voltage Vgs is swept from +0.5V to +2.0V, and the drain-source voltage Vds is 0.1V, 0.5V, and 1.0V, respectively. And testing a transfer current characteristic curve Ids-Vgs of the T-FinFET field effect transistor, and determining that the device works normally.

3) As shown in fig. 3, the drain-source voltage Vds is swept from 0V to +2.0V, and the gate-source voltage Vgs is 1.0V, 1.3V, 1.5V, respectively. And testing an output current characteristic curve Ids-Vds of the T-FinFET field effect transistor.

Two optional points in the linear region are connected into a straight line, and the intercept of the corresponding straight line on a leakage potential axis is obtained, so that the cross turning point voltage of the linear region and the exponential region of the T-FinFET under different gate voltages, namely the offset leakage voltage VdOffset, is obtained.

4) The output current (Ids) is differentiated from the drain voltage (Vds) to obtain a relationship curve between the output conductance Gout and the drain-source voltage Vds, as shown in fig. 4. When Vds is small, Gout is in a linear relation with Vds.

Two optional points in the linear region of the conductance characteristic curve are connected into a straight line, and the intercept of the corresponding straight line on a drain voltage axis is obtained, so that the cross turning point voltage of the linear region and the protection region of the T-FinFET under different gate voltages, namely the saturation drain voltage Vdsat, is extracted.

What has been described above are merely some embodiments of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the inventive concept thereof, and these changes and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A tunneling double-gate field effect transistor T-FinFET characteristic drain voltage extraction method is characterized by comprising the following steps:

(1) selecting three different drain-source voltages Vds, scanning a gate-source voltage Vgs from +0.5V to +2.0V, testing a transfer current characteristic curve Ids-Vgs of the T-FinFET, and determining that the device works normally;

(2) three points of different gate-source voltages Vgs are selected, Vds is scanned from 0 volt to +2.0 volts, and an output current characteristic curve Ids-Vds of the T-FinFET is tested; selecting two points in a linear region to be connected into a straight line, and acquiring the intercept of the corresponding straight line on a drain voltage axis to obtain the cross turning point voltage of the linear region and the exponential region of the T-FinFET under different gate voltages, namely the offset drain voltage VdOffset;

(3) the drain-source output current Ids is differentiated with Vds to obtain an output conductance characteristic curve Gout-Vds; and then connecting two optional points in the linear region into a straight line, acquiring the intercept of the corresponding straight line on a drain voltage axis, and extracting the voltage of the cross turning point of the linear region and the saturation region of the T-FinFET under different gate voltages, namely the saturation drain voltage Vdsat.

2. The tunneling double-gate field effect transistor (T-FinFET) characteristic drain voltage extraction method of claim 1, wherein the three different drain-source voltages Vds are 0.1V, 0.5V and 1.0V, respectively.

3. The method of claim 1, wherein the three different gate-source voltages Vgs are 1.0V, 1.3V and 1.5V, respectively.

4. The tunneling double-gate FET T-FinFET characteristic drain voltage extraction method of any of claims 1-3, wherein the FET is a nano T-FinFET FET.