CN109873639A

CN109873639A - A Phase-Locked Loop Method Based on First-Order Filter with Zeros

Info

Publication number: CN109873639A
Application number: CN201711260198.7A
Authority: CN
Inventors: 袁静泊; 包广清
Original assignee: Lanzhou University of Technology
Current assignee: Lanzhou University of Technology
Priority date: 2017-12-04
Filing date: 2017-12-04
Publication date: 2019-06-11

Abstract

The invention discloses a kind of phase-locked loop methods based on the firstorder filter containing zero point, it constructs filtering channel and orthogonal signal generator in phase demodulation link, input voltage is changed to 90 ° of phase phase difference of two sinusoidal signals by orthogonal signal generator, by introducing control amplified signal K to low-pass filter_n, so that adjusting the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state.The present invention can reduce the phase locking unit response time, improve the reliability of system, reduce interference, enhance locking phase precision.

Description

A kind of phase-locked loop method based on the firstorder filter containing zero point

Technical field

The present invention relates to digital filtering technique field, in particular to a kind of phaselocked loops based on the firstorder filter containing zero point Method.

Background technique

Phaselocked loop is one of the important link in grid-connected inverter system, and performance superiority and inferiority directly affects the control of grid-connected current Effect processed.SRF-PLL based on single synchronous coordinate system is the linear closed-loop PLL being widely used at present.In network voltage ideal shape Under state, SRF-PLL has good dynamic property and stable state accuracy.But network voltage is often nonideal, there are frequencies The power quality problems such as fluctuation, asymmetrical three-phase and voltage distortion.Fundamental wave negative sequence and harmonic signal are in synchronous reference coordinate following table Now it is low-frequency ac signal, makes phase-lock-ring output frequency that oscillatory regime be presented, influence locking phase output performance, in some instances it may even be possible to cause Phaselocked loop can not work normally.

Traditional SRF-PLL carries out locking phase for fundamental positive sequence.Coordinate transform is equivalent to phase discriminator (Phase Detector, PD), loop filter (Loop Filter, LF) generally uses PI controller, and integral element is equivalent to voltage-controlled vibration Swing device (Voltage Controlled Oscillator, VCO).

When network voltage is in nonideality, traditional SRF-PLL output 2 harmonics will occur and high order is humorous Wave, severe jamming locking phase precision are unfavorable for the operation of subsequent control system.

Summary of the invention

The purpose of the present invention is to solve the above-mentioned problems, provides a kind of locking phase based on the firstorder filter containing zero point The features such as ring method has and increases locking phase precision, raising steady-state performance, high reliability.

The present invention is in order to achieve the above object, using following scheme:

A kind of phase-locked loop method based on the firstorder filter containing zero point constructs filtering channel and orthogonal letter in phase demodulation link Number generator, detailed process is as follows for the method:

Step 1: network voltage V is input to orthogonal signal generator, and orthogonal signal generator output phase differs 90 ° Two sinusoidal signal V_α(s) and V_β(s), the sinusoidal signal V_α(s) and V_β(s) it is executed according to following transfer function:

V_α(s)=V (s) (1)

Then step 2 and step 3 are performed simultaneously；

Step 2: in input terminal input signal V (t)=sin (ω t+ φ) of phaselocked loop, the base of the input signal V (t) Frequency ω and phaselocked loop estimate frequencyIt matches, at this time signal V_β(s) following steady-state equation is executed:

Step 3: the sinusoidal signal V_α(s) and V_β(s) there are identical amplitude and frequency, the sinusoidal signal V_β(s) Phase falls behind sinusoidal signal V_α(s) phase, phase difference are pi/2, pass through control amplified signal K at this time_nValue, by amplified signal K_n Low-pass filter is inputted, adjusts the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state.

Preferably, the control amplified signal K_nWhen value is 0.5, response time t_sFor 20ms.

Preferably, the control amplified signal K_nWhen value is 1, response time t_sFor 10ms.

Preferably, the control amplified signal K_nWhen value is 2, response time t_sFor 5ms.

The beneficial effects of the present invention are:

1, the dynamic property of adjustable phase detectors.

2, the operation stability of network system is improved.

3, interference is reduced, locking phase precision is improved

Detailed description of the invention

Fig. 1 and Fig. 3 is time domain stable state block diagram of the present invention；

Fig. 2 is performance analysis plot figure of the present invention

Specific embodiment

With reference to the attached drawing in the embodiment of the present invention, to further illustrate the technical scheme of the present invention.

V_α(s)=V (s) (1)

Then step 2 and step 3 are performed simultaneously；

Embodiment:

When the present invention is applied in network system, filtering channel and orthogonal signal generator, this hair are constructed in phase demodulation link Detailed process is as follows for bright work:

V_α(s)=V (s) (1)

Then step 2 and step 3 are performed simultaneously；

Step 3: the sinusoidal signal V_α(s) and V_β(s) there are identical amplitude and frequency, the sinusoidal signal V_β(s) Phase falls behind sinusoidal signal V_α(s) phase, phase difference are pi/2, pass through control amplified signal K at this time_nValue, by amplified signal K_n Low-pass filter is inputted, adjusts the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state, such as Fig. 1 institute Show.

Work as K_nWhen=0.5, ω_ff=2 π 50rad/s, can obtain response time t_s=20ms, phase discriminator timeconstantτ ρ ≈ 6.7ms；Work as K_nWhen=1, ω_ff=2 π 50rad/s, can obtain response time t_s=10ms；Work as K_nWhen=2, ω_ff=2 π 50rad/s can obtain response time t_s=5ms, phase discriminator timeconstantτ ρ ≈ 1.7ms；It follows that the phase discriminator time is normal Number is approximately τ ρ==1/ (K_nω_ff), phaselocked loop dynamic analysis are as shown in Figure 2.

The phase demodulation link of phaselocked loop is finally constituted, as shown in figure 3, four signals of output are respectively the orthogonal letter of fundamental positive sequence Number and fundamental wave negative sequence orthogonal signalling, that is, the separate harmonious wave for realizing positive-negative sequence filters out.

It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with Understand on the basis of not departing from the principle and spirit of the invention, a variety of to the progress of these embodiments can change, modify, replace It changes and modification is limited without departure from protection scope of the present invention by the claim and its equivalent.

Claims

1. a phase-locked loop method based on the first-order filter containing zero, builds filter channel and quadrature signal generator in phase detection link, it is characterized in that, the concrete process of described method is as follows:

Step 1: The grid voltage V is input to the quadrature signal generator, and the quadrature signal generator outputs two sinusoidal signals V _α (s) and V _β (s) with a phase difference of 90°. The sinusoidal signals V _α (s) and V _β (s) according to the following transfer function:

V _α (s)=V(s) (1)

Then perform step 2 and step 3 at the same time;

Step 2: Input the signal V(t)=sin(ωt+φ) at the input end of the phase-locked loop, and the fundamental frequency ω of the input signal V(t) is the same as

Estimated frequency of phase locked loop match, at which time the signal V _β (s) performs the following steady-state equation:

Step 3: The sinusoidal signal V _α (s) and V _β (s) have the same amplitude and frequency, the phase of the sinusoidal signal V _β (s) lags behind the phase of the sinusoidal signal V _α (s), and the phase difference is π/2, at this time, by controlling the value of the amplified signal K _n , the amplified signal K _{n is} input to the low-pass filter to adjust the dynamic performance of the phase detector, and the phase-locked loop and the phase detector achieve a time-domain steady state.

2 . The phase-locked loop method based on a first-order filter with zeros according to claim 1 , wherein when the control amplification signal K _n is 0.5, the response time t _s is 20 ms. 3 .

3 . The phase-locked loop method based on a first-order filter with zeros according to claim 1 , wherein when the control amplification signal K _n is 1, the response time t _s is 10 ms. 4 .

4 . The phase-locked loop method based on a first-order filter with zeros according to claim 1 , wherein when the control amplification signal K _n is 2, the response time t _s is 5 ms. 5 .