CN109873639A - A kind of phase-locked loop method based on the firstorder filter containing zero point - Google Patents
A kind of phase-locked loop method based on the firstorder filter containing zero point Download PDFInfo
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- CN109873639A CN109873639A CN201711260198.7A CN201711260198A CN109873639A CN 109873639 A CN109873639 A CN 109873639A CN 201711260198 A CN201711260198 A CN 201711260198A CN 109873639 A CN109873639 A CN 109873639A
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Abstract
The invention discloses a kind of phase-locked loop methods based on the firstorder filter containing zero point, it constructs filtering channel and orthogonal signal generator in phase demodulation link, input voltage is changed to 90 ° of phase phase difference of two sinusoidal signals by orthogonal signal generator, by introducing control amplified signal K to low-pass filtern, so that adjusting the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state.The present invention can reduce the phase locking unit response time, improve the reliability of system, reduce interference, enhance locking phase precision.
Description
Technical field
The present invention relates to digital filtering technique field, in particular to a kind of phaselocked loops based on the firstorder filter containing zero point
Method.
Background technique
Phaselocked loop is one of the important link in grid-connected inverter system, and performance superiority and inferiority directly affects the control of grid-connected current
Effect processed.SRF-PLL based on single synchronous coordinate system is the linear closed-loop PLL being widely used at present.In network voltage ideal shape
Under state, SRF-PLL has good dynamic property and stable state accuracy.But network voltage is often nonideal, there are frequencies
The power quality problems such as fluctuation, asymmetrical three-phase and voltage distortion.Fundamental wave negative sequence and harmonic signal are in synchronous reference coordinate following table
Now it is low-frequency ac signal, makes phase-lock-ring output frequency that oscillatory regime be presented, influence locking phase output performance, in some instances it may even be possible to cause
Phaselocked loop can not work normally.
Traditional SRF-PLL carries out locking phase for fundamental positive sequence.Coordinate transform is equivalent to phase discriminator (Phase
Detector, PD), loop filter (Loop Filter, LF) generally uses PI controller, and integral element is equivalent to voltage-controlled vibration
Swing device (Voltage Controlled Oscillator, VCO).
When network voltage is in nonideality, traditional SRF-PLL output 2 harmonics will occur and high order is humorous
Wave, severe jamming locking phase precision are unfavorable for the operation of subsequent control system.
Summary of the invention
The purpose of the present invention is to solve the above-mentioned problems, provides a kind of locking phase based on the firstorder filter containing zero point
The features such as ring method has and increases locking phase precision, raising steady-state performance, high reliability.
The present invention is in order to achieve the above object, using following scheme:
A kind of phase-locked loop method based on the firstorder filter containing zero point constructs filtering channel and orthogonal letter in phase demodulation link
Number generator, detailed process is as follows for the method:
Step 1: network voltage V is input to orthogonal signal generator, and orthogonal signal generator output phase differs 90 °
Two sinusoidal signal Vα(s) and Vβ(s), the sinusoidal signal Vα(s) and Vβ(s) it is executed according to following transfer function:
Vα(s)=V (s) (1)
Then step 2 and step 3 are performed simultaneously；
Step 2: in input terminal input signal V (t)=sin (ω t+ φ) of phaselocked loop, the base of the input signal V (t)
Frequency ω and phaselocked loop estimate frequencyIt matches, at this time signal Vβ(s) following steady-state equation is executed:
Step 3: the sinusoidal signal Vα(s) and Vβ(s) there are identical amplitude and frequency, the sinusoidal signal Vβ(s)
Phase falls behind sinusoidal signal Vα(s) phase, phase difference are pi/2, pass through control amplified signal K at this timenValue, by amplified signal Kn
Low-pass filter is inputted, adjusts the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state.
Preferably, the control amplified signal KnWhen value is 0.5, response time tsFor 20ms.
Preferably, the control amplified signal KnWhen value is 1, response time tsFor 10ms.
Preferably, the control amplified signal KnWhen value is 2, response time tsFor 5ms.
The beneficial effects of the present invention are:
1, the dynamic property of adjustable phase detectors.
2, the operation stability of network system is improved.
3, interference is reduced, locking phase precision is improved
Detailed description of the invention
Fig. 1 and Fig. 3 is time domain stable state block diagram of the present invention；
Fig. 2 is performance analysis plot figure of the present invention
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, to further illustrate the technical scheme of the present invention.
A kind of phase-locked loop method based on the firstorder filter containing zero point constructs filtering channel and orthogonal letter in phase demodulation link
Number generator, detailed process is as follows for the method:
Step 1: network voltage V is input to orthogonal signal generator, and orthogonal signal generator output phase differs 90 °
Two sinusoidal signal Vα(s) and Vβ(s), the sinusoidal signal Vα(s) and Vβ(s) it is executed according to following transfer function:
Vα(s)=V (s) (1)
Then step 2 and step 3 are performed simultaneously；
Step 2: in input terminal input signal V (t)=sin (ω t+ φ) of phaselocked loop, the base of the input signal V (t)
Frequency ω and phaselocked loop estimate frequencyIt matches, at this time signal Vβ(s) following steady-state equation is executed:
Step 3: the sinusoidal signal Vα(s) and Vβ(s) there are identical amplitude and frequency, the sinusoidal signal Vβ(s)
Phase falls behind sinusoidal signal Vα(s) phase, phase difference are pi/2, pass through control amplified signal K at this timenValue, by amplified signal Kn
Low-pass filter is inputted, adjusts the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state.
Embodiment:
When the present invention is applied in network system, filtering channel and orthogonal signal generator, this hair are constructed in phase demodulation link
Detailed process is as follows for bright work:
Step 1: network voltage V is input to orthogonal signal generator, and orthogonal signal generator output phase differs 90 °
Two sinusoidal signal Vα(s) and Vβ(s), the sinusoidal signal Vα(s) and Vβ(s) it is executed according to following transfer function:
Vα(s)=V (s) (1)
Then step 2 and step 3 are performed simultaneously；
Step 2: in input terminal input signal V (t)=sin (ω t+ φ) of phaselocked loop, the base of the input signal V (t)
Frequency ω and phaselocked loop estimate frequencyIt matches, at this time signal Vβ(s) following steady-state equation is executed:
Step 3: the sinusoidal signal Vα(s) and Vβ(s) there are identical amplitude and frequency, the sinusoidal signal Vβ(s)
Phase falls behind sinusoidal signal Vα(s) phase, phase difference are pi/2, pass through control amplified signal K at this timenValue, by amplified signal Kn
Low-pass filter is inputted, adjusts the dynamic property of phase detectors, phaselocked loop and phase discriminator reach time domain stable state, such as Fig. 1 institute
Show.
Work as KnWhen=0.5, ωff=2 π 50rad/s, can obtain response time ts=20ms, phase discriminator timeconstantτ ρ ≈
6.7ms；Work as KnWhen=1, ωff=2 π 50rad/s, can obtain response time ts=10ms；Work as KnWhen=2, ωff=2 π
50rad/s can obtain response time ts=5ms, phase discriminator timeconstantτ ρ ≈ 1.7ms；It follows that the phase discriminator time is normal
Number is approximately τ ρ==1/ (Knωff), phaselocked loop dynamic analysis are as shown in Figure 2.
The phase demodulation link of phaselocked loop is finally constituted, as shown in figure 3, four signals of output are respectively the orthogonal letter of fundamental positive sequence
Number and fundamental wave negative sequence orthogonal signalling, that is, the separate harmonious wave for realizing positive-negative sequence filters out.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
Understand on the basis of not departing from the principle and spirit of the invention, a variety of to the progress of these embodiments can change, modify, replace
It changes and modification is limited without departure from protection scope of the present invention by the claim and its equivalent.
Claims (4)
1. a kind of phase-locked loop method based on the firstorder filter containing zero point constructs filtering channel and orthogonal signalling in phase demodulation link
Generator, which is characterized in that detailed process is as follows for the method:
Step 1: network voltage V is input to orthogonal signal generator, and orthogonal signal generator output phase differs two of 90 °
Sinusoidal signal Vα(s) and Vβ(s), the sinusoidal signal Vα(s) and Vβ(s) it is executed according to following transfer function:
Vα(s)=V (s) (1)
Then step 2 and step 3 are performed simultaneously；
Step 2: in input terminal input signal V (t)=sin (ω t+ φ) of phaselocked loop, the fundamental frequency omega of the input signal V (t)
With
Phaselocked loop estimates frequencyIt matches, at this time signal Vβ(s) following steady-state equation is executed:
Step 3: the sinusoidal signal Vα(s) and Vβ(s) there are identical amplitude and frequency, the sinusoidal signal Vβ(s) phase
Fall behind sinusoidal signal Vα(s) phase, phase difference are pi/2, pass through control amplified signal K at this timenValue, by amplified signal KnInput
Low-pass filter, adjusts the dynamic property of phase detectors, and phaselocked loop and phase discriminator reach time domain stable state.
2. a kind of phase-locked loop method based on the firstorder filter containing zero point according to claim 1, which is characterized in that institute
State control amplified signal KnWhen value is 0.5, response time tsFor 20ms.
3. a kind of phase-locked loop method based on the firstorder filter containing zero point according to claim 1, which is characterized in that institute
State control amplified signal KnWhen value is 1, response time tsFor 10ms.
4. a kind of phase-locked loop method based on the firstorder filter containing zero point according to claim 1, which is characterized in that institute
State control amplified signal KnWhen value is 2, response time tsFor 5ms.
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Citations (3)
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|---|---|---|---|---|
| CN101617234A (en) * | 2006-11-06 | 2009-12-30 | 歌美飒创新技术公司 | Advanced real-time grid monitoring system |
| CN104104113A (en) * | 2014-08-11 | 2014-10-15 | 哈尔滨同为电气股份有限公司 | Method for grid-connected control of LCI driving high-voltage synchronous motor |
| CN105785788A (en) * | 2015-11-26 | 2016-07-20 | 华中科技大学 | Rapid three-phase voltage phase-locked loop method and dynamic response performance analyzing method thereof |
-
2017
- 2017-12-04 CN CN201711260198.7A patent/CN109873639A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101617234A (en) * | 2006-11-06 | 2009-12-30 | 歌美飒创新技术公司 | Advanced real-time grid monitoring system |
| CN104104113A (en) * | 2014-08-11 | 2014-10-15 | 哈尔滨同为电气股份有限公司 | Method for grid-connected control of LCI driving high-voltage synchronous motor |
| CN105785788A (en) * | 2015-11-26 | 2016-07-20 | 华中科技大学 | Rapid three-phase voltage phase-locked loop method and dynamic response performance analyzing method thereof |
Non-Patent Citations (2)
| Title |
|---|
| DJORDJE STOJIĆ等: ""Novel orthogonal signal generator for single phase PLL applications"", 《IET POWER ELECTRONICS》 * |
| LONG-YUE YANG等: ""A Novel Phase Locked Loop for Grid-Connected Converters under Non-Ideal Grid Conditions"", 《JOURNAL OF POWER ELECTRONICS》 * |
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