CN109872636B - Display panel and display device - Google Patents
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- CN109872636B CN109872636B CN201910253048.6A CN201910253048A CN109872636B CN 109872636 B CN109872636 B CN 109872636B CN 201910253048 A CN201910253048 A CN 201910253048A CN 109872636 B CN109872636 B CN 109872636B
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Abstract
The invention discloses a display panel and a display device, which relate to the technical field of display and comprise: the display device comprises a display area and a non-display area, wherein the non-display area comprises a plurality of shift register groups, and each shift register group comprises a first shift register group positioned in a first non-display area and a cascade shift register group positioned in a first non-display area; the first shift register group comprises a plurality of cascaded first shift registers, and the cascaded shift register group comprises a plurality of cascaded shift registers; the driving signal output end of the first shift register is electrically connected with the first pixel unit row and transmits a driving signal to the first pixel unit row; the first shift register group is cascaded with the cascaded shift register group; the width of the cascaded shift registers is smaller than the width of the first shift register along the second direction. In such a way, the width of the first non-display area along the second direction is favorably reduced, the narrow frame design of the display panel is realized, and the product screen occupation ratio is favorably improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the development of science and technology, the display device with the display panel has more and more extensive applications, so that the requirements of people on the display panel are more and more diversified, the requirements are not only met with the conventional performance indexes of the display panel, such as large size, high definition and the like, but also more diversified requirements are met on the appearance of the display panel, and the special-shaped display panel is formed.
The display panel breaks through the limitation of a single rectangular structure of the display panel, so that not only the display effect is more diversified, but also the application way of the display panel is more and more extensive, and the display panel is successfully applied to wearable electronic designs such as watches, glasses or intelligent bracelets. Compared with a conventional display screen, the special-shaped display screen is mainly different in that the display area of the special-shaped display screen is in a non-rectangular special shape.
When the display area is in a non-rectangular special shape, how to design a narrow frame of the non-display area becomes one of the current technical problems to be solved urgently.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device, wherein along the second direction, the width of the cascade shift register is smaller than the width of the first shift register, so as to be beneficial to reducing the width of the first non-display area along the second direction, and to realize a narrow frame design of the display panel, thereby being beneficial to improving the screen occupation ratio of the product.
In a first aspect, the present application provides a display panel comprising:
a display area and a non-display area surrounding the display area; the display area comprises a first display area and a second display area, and the second display area is adjacent to the first display area along a first direction; the non-display area comprises a first non-display area and a second non-display area, the display area is positioned between the first non-display area and the second non-display area along a second direction, and the first direction and the second direction are intersected;
the first non-display area comprises a first non-display area which is formed by sinking towards the display area along the second direction, and the second non-display area comprises a second non-display area which is arranged opposite to the first non-display area; the first non-display area further comprises a first non-display area, and the first non-display area is adjacent to the first display area along the second direction;
a plurality of pixel unit rows arranged along the first direction and extending along the second direction, the pixel unit rows including a first pixel unit row located in the first display region and a second pixel unit row located in the second display region;
the non-display area comprises a plurality of shift register groups, and the shift register groups comprise a first shift register group positioned in the first non-display area and a cascade shift register group positioned in the first non-display area; the first shift register group comprises a plurality of cascaded first shift registers, and the cascaded shift register group comprises a plurality of cascaded shift registers; a driving signal output end of the first shift register is electrically connected with the first pixel unit row and transmits a driving signal to the first pixel unit row; the first shift register group is cascaded with the cascaded shift register group;
the width of the cascaded shift register is smaller than the width of the first shift register along the second direction.
In a second aspect, based on the same inventive concept, the present application further provides a display device, including a display panel, where the display panel is the display panel provided in the present application.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
in the display panel and the display device provided by the application, the first non-display area comprises a first non-display area formed by sinking towards the display area and a first non-display area adjacent to the first non-display area along a first direction, the first shift register group is located in the first non-display area, the cascade shift register group is located in the first non-display area, particularly, along a second direction, the width of the cascade shift register in the cascade shift register group is smaller than that of the first shift register in the first shift register group, and by adopting the design, the space occupied by the cascade shift register in the first non-display area is reduced, so that the frame width of the first non-display area along the second direction is favorably realized, and the screen occupation ratio of the display panel and the display device is favorably improved.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a top view of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a diagram showing a relative position relationship of a part of the shift register set in the first non-display area;
fig. 3 is a top view of another display panel provided in the embodiment of the present application;
fig. 4 is a top view of another display panel provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of a shift register in a display panel according to an embodiment of the present disclosure;
FIG. 6 is an AA' cross-sectional view of the display panel provided in the embodiment of FIG. 1;
fig. 7 is a schematic structural diagram illustrating an orthographic projection of an output transistor on a substrate in a display panel according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of fig. 7 illustrating an orthographic projection of a cascaded transistor on a substrate in a display panel according to an embodiment of the present application;
fig. 9 is a top view of a first metal layer and a capacitor metal layer in a first shift register of a display panel according to an embodiment of the present disclosure;
fig. 10 is a top view of a first metal layer and a capacitor metal layer in a cascaded shift register in a display panel according to an embodiment of the present disclosure;
fig. 11 is a top view of another display panel provided in an embodiment of the present application;
fig. 12 is a structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the prior art, the display panel breaks through the limitation of a single rectangular structure of the display panel, so that not only the display effect is more diversified, but also the application way of the display panel is more and more extensive, and the display panel is successfully applied to wearable electronic designs such as watches, glasses or smart bracelets. Compared with a conventional display screen, the special-shaped display screen is mainly different in that the display area of the special-shaped display screen is in a non-rectangular special shape. When the display area is in a non-rectangular special shape, how to design a narrow frame of the non-display area becomes one of the current technical problems to be solved urgently.
In view of this, the present invention provides a display panel and a display device, wherein along the second direction, the width of the cascade shift register is smaller than the width of the first shift register, so as to be beneficial to reducing the width of the first non-display area along the second direction, and to realize a narrow frame design of the display panel, thereby being beneficial to improving the screen occupation ratio of the product.
The following detailed description is to be read in connection with the drawings and the detailed description.
Fig. 1 is a top view of a display panel according to an embodiment of the present disclosure, fig. 2 is a relative position diagram of a partial shift register set in a first non-display area, and referring to fig. 1 and fig. 2, a display panel 100 according to an embodiment of the present disclosure includes:
a display area 102 and a non-display area 103 surrounding the display area 102; the display area 102 includes a first display area 11 and a second display area 12, and the second display area 12 is adjacent to the first display area 11 along the first direction; the non-display area 103 includes a first non-display area 31 and a second non-display area 32, the display area being located between the first non-display area 31 and the second non-display area 32 in a second direction, the first direction and the second direction intersecting;
the first non-display region 31 includes a first non-display region 311 concavely formed toward the display region along the second direction, and the second non-display region 32 includes a second non-display region 321 disposed opposite to the first non-display region 311; the first non-display area 31 further includes a first second non-display area 312, and the first second non-display area 312 is adjacent to the first display area 11 along the second direction;
a plurality of pixel unit rows arranged in a first direction and extending in a second direction, the pixel unit rows including a first pixel unit row 21 located in the first display region 11 and a second pixel unit row 22 located in the second display region 12;
the non-display area includes a plurality of shift register groups including a first shift register group 61 located in the first non-display area 312 and a cascade shift register group 50 located in the first non-display area 311; the first shift register group 61 includes a plurality of cascaded first shift registers 41, and the cascaded shift register group 50 includes a plurality of cascaded shift registers 51; a driving signal output terminal of the first shift register 41 is electrically connected to the first pixel cell row 21, and transmits a driving signal to the first pixel cell row 21; the first shift register group 61 is cascaded with the cascaded shift register group 50;
in the second direction, the width W11 of the cascade shift register 51 is smaller than the width W22 of the first shift register 41.
Specifically, with continuing reference to fig. 1 and fig. 2, in the display panel 100 provided in the embodiment of the present application, the first non-display area 31 includes a first non-display area 311 formed by being recessed toward the display area along the first direction and a first second non-display area 312 adjacent to the first display area 11 along the second direction, wherein a cascaded shift register set 50 is disposed in the first non-display area 311, a first shift register set 61 is disposed in the first second non-display area 312, and a driving signal output end of the first shift register set 61 is electrically connected to the first pixel unit row 21 in the first display area 11 to transmit a driving signal to the first pixel unit row 21; the first shift register group 61 is cascaded with the cascaded shift register group 50, and the cascaded shift register 51 plays a role of transmitting a shift signal, for example, IN the first shift register group 61 located at the upper side of the cascaded shift register group 50 along the first direction IN the view shown IN fig. 2, the shift signal output end OUT1 thereof is connected with the shift signal input end IN of the cascaded shift register group 51, and outputs the shift signal to the cascaded shift register group 50; the shift signal output terminal OUT2 of the cascade shift register group 50 is electrically connected to the first shift register group 61 located on the lower side in the first direction, and outputs a shift signal to the first shift register group 61. Particularly, along the second direction, the width W11 of the cascaded shift register 51 is smaller than the width W22 of the first shift register 41, which is beneficial to saving the space occupied by the cascaded shift register 51 in the first non-display area 311, so as to be beneficial to reducing the width of the first non-display area 311 along the second direction, and beneficial to realizing the narrow frame design of the corresponding position of the first non-display area 311, and further beneficial to improving the screen occupation ratio of the display panel 100. In addition, when the cascade shift register 51 is not disposed in the first non-display area 311, the first shift register groups 50 located at the upper and lower sides of the second display area 12 are electrically connected directly through shift signal lines under the viewing angle shown in fig. 1, and when the first pixel unit row 21 in the first display area 11 adopts bilateral driving and the shift register located at the right side of the second pixel unit row 22 drives the second pixel unit row 22, the shift signals at the two sides of the second pixel unit row 22 are not synchronized, which causes that the two received drive signals of the first pixel unit row 21 located below the second display area 12 are not synchronized, thereby making it difficult to normally drive the first pixel unit row 21; in the present application, after the cascade shift register 51 is disposed in the first non-display area 311, the function of transmitting the shift signal can be normally performed, and the shift signals of the shift registers on both sides of the second pixel unit row 22 can be kept synchronous, so that the two received driving signals of the first pixel unit row 21 located below the second display area 12 can be synchronous, which is beneficial to improving the reliable and synchronous driving of each first pixel unit row in the display panel.
It should be noted that, the embodiment shown in fig. 1 only shows that the display panel 100 includes one first non-display area 311, and besides this, in some other embodiments provided in the present application, the display panel 100 may further include two or more first non-display areas 311, and the shape and size of the first non-display area 311 may also be flexibly set according to the actual situation, which is not specifically limited in the present application. In addition, fig. 1 also shows only one relative positional relationship between the pixel unit row and the gate driving unit, and does not represent an actual number and size, and the sub-pixels included in the pixel unit row are also schematically illustrated and do not represent an actual number and size.
Alternatively, in the viewing angle shown in fig. 1, the embodiment only shows a situation where the first non-display area 311 is located in the middle area of the left edge of the display panel 100, that is, the display panel 100 includes one second display area 12 and two first display areas 11 located at two sides of the second display area 12 along the first direction, in some other embodiments of the present application, the first non-display area 311 may also be located at a corner position of the display panel 100, for example, please refer to fig. 3, fig. 3 shows another top view of the display panel 100 provided in the embodiment of the present application, and in the viewing angle shown in fig. 3, the first non-display area 311 is located at an upper left corner position of the display panel 100, and the display panel 100 includes only one first display area 11 and one second display area 12 adjacent to the first display area 11 along the first direction. Of course, under the viewing angles shown in fig. 1 and fig. 3, the first non-display region 311 is located at the right edge of the display panel 100, in some other embodiments of the present application, the first non-display region 311 may also be located at the right edge of the display panel 100, for example, please refer to fig. 4, which is not particularly limited in this application, wherein fig. 4 is another top view of the display panel 100 provided in the embodiment of the present application.
Optionally, the display panel 100 provided in the embodiment of the present application includes a gate driving circuit located in the non-display area, and the shift register in the shift register group is a minimum repeating unit in the gate driving circuit;
fig. 5 is a schematic structural diagram of a shift register IN the display panel 100 according to an embodiment of the present disclosure, please refer to fig. 5, IN which the shift register includes a control unit 60, an output transistor 40, a shift signal input terminal IN1, a driving signal output terminal OUT0, and a shift signal output terminal OUT 3;
a first input terminal of the control unit 60 serves as a shift signal input terminal IN1, a first output terminal of the control unit 60 serves as a shift signal output terminal OUT3, a second output terminal of the control unit 60 is electrically connected to the output transistor, and an output terminal of the output transistor 40 serves as a driving signal output terminal OUT 0.
It should be noted that fig. 5 only shows the case of one input terminal (i.e., the shift signal input terminal IN1) of the shift register, and IN fact, each shift register includes a plurality of input terminals, such as a clock signal input terminal, etc., and fig. 5 only illustrates the input terminals that may be involved IN the present application and does not represent the number of actual signal terminals of the shift register. The shift register receives a shift signal through a shift signal input terminal IN1, causing the corresponding output transistor to output a drive signal to the connected row of pixel cells. It should be noted that fig. 5 only shows one structure of the shift register, and the shift register includes two output transistors 40, in some embodiments, the two output transistors 40 may transmit the driving signal to the row of pixel units in common, and of course, in some other embodiments of the present application, the shift register may also include one output transistor or three or more output transistors, which is not limited in this application. It should be noted that the first shift register and the cascade shift register both have the structure of the shift register; the first shift register and the cascade shift register are different in that: the first shift register has the same structure and function as those of the shift register in the prior art, that is, the first shift register not only can normally drive pixels to emit light, but also can transmit cascade signals to realize the cascade function of the shift register; the reduction of the width of the cascaded shift register in the structural dimension leads to the reduction of the function, compared with the first shift register, the cascaded shift register can functionally realize the function, but the luminous capability for driving the pixel is reduced, and even the pixel cannot be driven.
Optionally, referring to fig. 5, in the embodiment shown in fig. 2, the first shift register 41 includes a first output transistor, the cascade shift register 51 includes a cascade output transistor, and a width of the cascade output transistor is smaller than a width of the first output transistor along the second direction.
Specifically, when the width of the cascade output transistor along the second direction is designed to be smaller than the width of the first output transistor, the width of the cascade shift register 51 along the second direction can be reduced, so that the arrangement inside the cascade shift register 51 is more compact along the second direction, and the width of the cascade shift register 51 is smaller than the width of the first shift register 41, thereby being beneficial to saving the space of the first non-display area 311 where the cascade shift register 51 is located along the second direction, being beneficial to realizing the narrow-frame design of the first non-display, and further being beneficial to improving the screen occupation ratio of the display panel 100.
Alternatively, fig. 6 is an AA' cross-sectional view of the display panel 100 provided in the embodiment of fig. 1, fig. 7 is a schematic structural view of an orthographic projection of the output transistor 411 on the substrate 101 in the display panel 100 provided in the embodiment of the present application, fig. 8 is a schematic structural view of an orthographic projection of the cascode transistor 412 on the substrate in the display panel provided in the embodiment of the present application, please refer to fig. 6-8, the display panel 100 includes the substrate 101 and the polysilicon layer 90, the first metal layer 91 and the second metal layer 92 disposed on the substrate 101, the output transistor 40 in fig. 5 includes the gate 94 located on the first metal layer 91 and the source 95 and the drain 96 located on the second metal layer 92, and the gate 94 and the polysilicon layer 90 form an overlapping region in the orthographic projection of the substrate 101;
along the second direction, the width of the overlapping region 81 of the first output transistor 411 is W1, and the width of the overlapping region 83 of the cascode output transistor 412 is W2, where W2 < W1.
Specifically, with reference to fig. 6 to 8, in the display panel 100 provided in the embodiment of the present application, an overlapping region is formed by orthographic projections of the gates of the first output transistor 411 and the cascade output transistor 412 and the polysilicon layer 90 on the plane of the substrate 101, and along the second direction, when the width W1 of the overlapping region 81 of the first output transistor 411 is smaller than the width W2 of the overlapping region 83 of the cascade output transistor 412, the width of the cascade output transistor 412 along the second direction can be smaller than the width of the first output transistor 411 along the second direction, which is also beneficial to saving the space of the first non-display region 311 where the cascade shift register 51 is located along the second direction, and is beneficial to realizing a narrow bezel design of the first non-display, thereby being beneficial to improving the screen ratio of the display panel 100. It should be noted that the overlap region refers to a region corresponding to a conventional channel width-to-length ratio in a transistor.
Optionally, the width-to-length ratio of the first output transistor is a1, and the width-to-length ratio of the cascade output transistor is a2, a2 < a 1.
Specifically, the width-to-length ratio of the output transistor is proportional to the driving capability of the output transistor to the row of pixel cells connected thereto, and the larger the width-to-length ratio, the larger the driving capability of the output transistor. Considering that the first non-display region 311 is formed recessed toward the inside of the display region along the first direction, the number of sub-pixels included in the second pixel cell row 22 is smaller than the number of sub-pixels included in the first pixel cell row 21, and therefore, the driving capability required for the second pixel cell row 22 correspondingly will be smaller than that required for the first pixel cell row 21, and therefore, even when the width-to-length ratio a2 of the cascade output transistors is smaller than the width-to-length ratio a1 of the first output transistors, the influence on the driving capability of the second pixel cell row 22 is small. In addition, when a2 is smaller than a1, the overall size of the cascade output transistor is smaller than that of the first output transistor, and the width of the cascade output transistor is smaller than that of the first output transistor along the second direction, so that the space of the first non-display region 311 where the cascade shift register 51 is located along the second direction is saved, the narrow frame design of the first non-display region is facilitated on the premise that the driving capability of the corresponding driven pixel row is not affected, and the screen occupation ratio of the display panel 100 is further facilitated to be improved. It should be noted that, when the width-to-length ratio of the cascade output transistor is smaller than a2 to a certain extent, the driving capability thereof is greatly weakened, and it may not be possible to output the driving signal to the corresponding pixel unit row, but the cascade function of the cascade output transistor is not affected, and the shift signal can still be normally transmitted.
Alternatively, referring to fig. 7 and 8, along the first direction, the length of the overlapping region 81 of the first output transistor is L1, the length of the overlapping region 81 of the cascode output transistor is L2,
A1-W1/L1, A2-W2/L2, wherein W1 is not less than 100 mu m and not more than 200 mu m, and L1 is not less than 3 mu m and not more than 4 mu m; w2 is more than or equal to 6 microns and less than or equal to 15 microns, and L2 is more than or equal to 3 microns and less than or equal to 4 microns.
As such, in the first direction, the length L2 corresponding to the overlap region 81 of the cascaded shift register 51 is similar to the length L1 corresponding to the overlap region 81 of the first shift register 41; however, in the second direction, the width of the overlapping region 81 corresponding to the cascade shift register 51 is reduced to a width of 6 μm to 15 μm, which is equivalent to that of the first shift register 41, by a width of 100 μm to 200 μm, and the reduced width is larger, so that the space occupied by the cascade shift register 51 in the first non-display region 311 in the second direction is reduced to a great extent, which is more beneficial to reducing the frame width of the first non-display region 311 in the second direction, and is more beneficial to realizing the narrow frame design of the first non-display region 311. In addition, the cascade output transistors in the cascade shift register 51 are retained in the present application, and the shift function of the cascade transistors is not affected.
Optionally, referring to fig. 6, fig. 9 and fig. 10, fig. 9 is a top view of the first metal layer 91 and the capacitor metal layer 93 in the first shift register 41 in the display panel 100 provided by the embodiment of the present application, and fig. 10 is a top view of the first metal layer 91 and the capacitor metal layer 93 in the cascaded shift register 51 in the display panel provided by the embodiment of the present application, where the shift register includes a storage capacitor C, the storage capacitor C includes two oppositely disposed plates, and an orthogonal projection of the two plates on a plane where the substrate 101 is located forms an overlapping region; the storage capacitors comprise a first storage capacitor C1 located in the first shift register 41 and a second storage capacitor C2 located in the cascade shift register 51;
along the second direction, the width of the overlapping region 82 of the first storage capacitor C1 is M1, and the width of the overlapping region 84 of the second storage capacitor C2 is M2, wherein M2 < M1.
Specifically, with continuing reference to fig. 6, 9, and 10, the display panel 100 provided in the embodiment of the present application further includes a capacitor metal layer 93 located between the first metal layer 91 and the second metal layer 92, the capacitor metal layer 93 and the first metal layer 91 overlap in a front projection of the plane where the substrate 101 is located, so as to form a storage capacitor, and two plates forming the storage capacitor are located in the first metal layer 91 and the capacitor metal layer 93, respectively. When M2 < M1, it is beneficial to reduce the width of the second storage capacitor C2 along the second direction, that is, it is beneficial to reduce the space occupied by the second storage capacitor C2 in the first non-display region 311, and it is also beneficial to reduce the space occupied by the cascaded shift register 51 in the first non-display region 311 along the second direction, so it is also beneficial to implement the narrow frame design of the first non-display region 311, and improve the screen occupation ratio of the display panel 100.
It should be noted that, in some embodiments of the present application, while the width of the cascade output transistor along the second direction is reduced, the space occupied by the second storage capacitor in the cascade transistor in the first non-display region 311 may also be reduced, so as to be beneficial to reducing the frame width of the first non-display region 311 to a great extent, and to be more beneficial to improving the screen occupation ratio of the display panel 100.
Optionally, please continue to refer to fig. 11, fig. 11 is another top view of the display panel 100 provided in the embodiment of the present application, referring to fig. 11, in the display panel 100 provided in the embodiment of the present application, the second non-display area 32 further includes a second non-display area 322, and in the second direction, the second non-display area 322 is adjacent to the first display area 11; the shift register group further includes a second shift register group located in the second Dinop display area 321 and a third shift register group located in the second Dinop display area 322, the second shift register group including a plurality of cascaded second shift registers 42, the third shift register group including a plurality of cascaded third shift registers 43;
the driving signal output terminal of the second shift register 42 is electrically connected to the second pixel cell row 22, and transmits a driving signal to the second pixel cell row 22; the drive signal output terminal of the third shift register 43 is electrically connected to the first pixel cell row 21, and outputs a drive signal to the first pixel cell row 21.
Specifically, referring to fig. 11, the first pixel unit row 21 in the first display area 11 is electrically connected to the first shift register 41 and the third shift register 43, respectively, and the first shift register 41 and the third shift register 43 transmit the driving signal to the first pixel unit row 21, that is, the first pixel unit row 21 is driven by adopting a bilateral driving method, which is favorable for enhancing the driving capability of the first pixel unit row 21. Meanwhile, the second shift register 42 is electrically connected to the second pixel cell row 22, and transmits a driving signal to the second pixel cell row 22, thereby implementing driving of the second pixel cell row 22.
Optionally, with continued reference to fig. 11, in the display panel 100 provided in the embodiment of the present application, the cascade shift register 51 includes cascade output transistors, and the second shift register 42 includes second output transistors, and along the second direction, the width of the cascade output transistors is smaller than the width of the second output transistors.
Specifically, when the width of the cascade output transistor is designed to be smaller than the width of the second output transistor, the space occupied by the cascade output transistor in the first non-display region 311 is saved, and the width of the first non-display region 311 in the second direction can be smaller than the width of the second non-display region 321, so that the narrow frame design of the first non-display region 311 is facilitated.
Alternatively, in the embodiment shown in fig. 11, the width-to-length ratio of the cascade output transistor is a2, the width-to-length ratio of the second output transistor is A3, a2 < A3.
As mentioned above, the aspect ratio of the output transistors is proportional to the driving capability thereof, and when a2 < A3, the space occupied by the cascade output transistors in the first non-display region 311 is reduced, and the output capability of the cascade output transistors is also reduced. However, since the output capability of the second output transistor is greater than that of the cascade output transistor, and the number of sub-pixels included in the second pixel cell row 22 is reduced, the second output transistor with strong driving capability can be used to normally drive the second pixel cell row 22, and thus the normal display function of the second display region 12 is not affected.
Optionally, with reference to fig. 11, in the display panel 100 provided in the embodiment of the present application, the second shift registers 42 are electrically connected to the second pixel unit rows 22 in a one-to-one correspondence manner, and the number of the cascaded shift registers 51 is the same as the number of the second shift registers 42.
Specifically, in the display panel 100 provided in the embodiment of the present application, the first non-display region 311 and the second non-display region 321 are respectively disposed on both sides of the second display region 12 along the second direction, the cascade shift registers 51 are disposed in the first non-display region 311, the second shift registers 42 are disposed in the second non-display region 321, the second shift registers 42 are electrically connected to the second pixel unit rows 22 in a one-to-one correspondence manner, when the number of the cascade shift registers 51 is the same as the number of the second shift registers 42, the shift signals in the first non-display region 31 and the second non-display region 32 can be synchronized, that is, the second shift register 42 at the last stage sends the shift signal to the first shift register 41 connected thereto, and the second shift register 42 at the last stage also sends the shift signal to the third shift register 43 connected thereto, so that the first and third shift registers 41 and 43 located at both sides of the first display region 11 in the second direction simultaneously drive the same first pixel cell row 21.
Optionally, in the display panel 100 provided in the embodiment of the present application, the driving signal output terminal of the cascaded shift register 51 does not send a driving signal to the second pixel unit row 22.
Specifically, in the present application, when the span of the cascaded shift register 51 along the second direction is designed to be smaller, the driving capability of the cascaded shift register is weakened, so that the second pixel unit row 22 in the second display area 12 can be driven in a single-side driving manner, that is, only the second shift register is used to drive the second pixel unit row 22, and the driving function can also be realized, so that the second display area 12 can normally display.
Optionally, in the display panel 100 provided in the embodiment of the present application, the shift register includes a plurality of transistors, the number of the transistors included in the first shift register 41 is N1, and the number of the transistors included in the cascade shift register 51 is N2, where N2 < N1.
Specifically, usually, the shift register includes a plurality of transistors, on the premise that the cascade shift register 51 can normally transmit the shift signal, the number of transistors included in the cascade shift register 51 can be reduced, when the number of transistors in the cascade shift register 51 is reduced, the size of the cascade shift register 51 can be reduced to a certain extent, and the space occupied by the cascade shift register 51 in the first non-display area 311 along the second direction is saved, thereby being also beneficial to realizing the narrow-frame design of the first non-display area 311.
Based on the same inventive concept, the present application further provides a display device, please refer to fig. 12, fig. 12 is a structural diagram of the display device according to the embodiment of the present application, the display device 200 includes a display panel 100, and the display panel is the display panel 100 according to any of the embodiments of the present application. It should be noted that, for the embodiments of the display device 200 provided in the embodiments of the present application, reference may be made to the embodiments of the display panel described above, and repeated descriptions are omitted. The display device provided by the application can be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
Optionally, referring to fig. 12, the display device 200 provided in the embodiment of the present application further includes a camera 401 and/or an optical sensor 402; the optical sensor 402 may sense light and convert the light signal into an electrical signal, which may be, for example, a fingerprint recognition sensor.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following advantages:
in the display panel and the display device provided by the application, the first non-display area comprises a first non-display area formed by sinking towards the display area and a first non-display area adjacent to the first non-display area along a first direction, the first shift register group is located in the first non-display area, the cascade shift register group is located in the first non-display area, particularly, along a second direction, the width of the cascade shift register in the cascade shift register group is smaller than that of the first shift register in the first shift register group, and by adopting the design, the space occupied by the cascade shift register in the first non-display area is reduced, so that the frame width of the first non-display area along the second direction is favorably realized, and the screen occupation ratio of the display panel and the display device is favorably improved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (12)
1. A display panel, comprising:
a display area and a non-display area surrounding the display area; the display area comprises a first display area and a second display area, and the second display area is adjacent to the first display area along a first direction; the non-display area comprises a first non-display area and a second non-display area, the display area is positioned between the first non-display area and the second non-display area along a second direction, and the first direction and the second direction are intersected;
the first non-display area comprises a first non-display area formed by being sunken towards the display area along the second direction, and the second non-display area comprises a second non-display area arranged opposite to the first non-display area; the first non-display area further comprises a first non-display area, and the first non-display area is adjacent to the first display area along the second direction;
a plurality of pixel unit rows arranged along the first direction and extending along the second direction, the pixel unit rows including a first pixel unit row located in the first display region and a second pixel unit row located in the second display region;
the non-display area comprises a plurality of shift register groups, each shift register group comprises a shift register, and each shift register comprises an output transistor; the shift register group comprises a first shift register group positioned in the first non-display area and a cascade shift register group positioned in the first non-display area; the first shift register group comprises a plurality of cascaded first shift registers, and the cascaded shift register group comprises a plurality of cascaded shift registers; a driving signal output end of the first shift register is electrically connected with the first pixel unit row and transmits a driving signal to the first pixel unit row; the first shift register group is cascaded with the cascaded shift register group;
the width of the cascade shift register is smaller than that of the first shift register along the second direction; the driving signal output end of the cascade shift register does not send a driving signal to the second pixel unit row;
the display panel comprises a substrate base plate, a polycrystalline silicon layer, a first metal layer and a second metal layer, wherein the polycrystalline silicon layer, the first metal layer and the second metal layer are arranged on the substrate base plate; the first shift register comprises a first output transistor, the cascade shift register comprises cascade output transistors, the width of the overlapping region of the first output transistor along the second direction is W1, the width of the overlapping region of the cascade output transistors is W2, wherein 100 [ mu ] m & lt/EN ] W1 & lt/EN & gt 200 [ mu ] m, 6 [ mu ] m & lt/EN ] W2 & lt/EN & gt 15 [ mu ] m.
2. The display panel according to claim 1, wherein the display panel comprises a gate driving circuit located in the non-display region, and the shift register in the shift register group is a minimum repeating unit in the gate driving circuit;
the shift register also comprises a control unit, a shift signal input end, a driving signal output end and a shift signal output end;
the first input end of the control unit is used as the shift signal input end, the first output end of the control unit is used as the shift signal output end, the second output end of the control unit is electrically connected with the output transistor, and the output end of the output transistor is used as the driving signal output end.
3. The display panel according to claim 2, wherein a width of the cascode output transistor is smaller than a width of the first output transistor along the second direction.
4. The display panel of claim 1, the first output transistor having a width to length ratio of a1, the cascode output transistor having a width to length ratio of a2, a2 < a 1.
5. The display panel according to claim 1,
along the first direction, the overlap region of the first output transistor has a length of L1, the overlap region of the cascode output transistor has a length of L2,
a1= W1/L1, A2= W2/L2, wherein L1 is less than or equal to 3 μm and less than or equal to 4 μm, and L2 is less than or equal to 3 μm and less than or equal to 4 μm.
6. The display panel according to claim 2, wherein the shift register comprises a storage capacitor, the storage capacitor comprises two oppositely arranged plates, and the orthographic projection of the two plates on the plane of the substrate base plate forms an overlapping region; the storage capacitor comprises a first storage capacitor positioned in the first shift register and a second storage capacitor positioned in the cascade shift register;
along the second direction, the width of the overlapping region of the first storage capacitor is M1, and the width of the overlapping region of the second storage capacitor is M2, wherein M2 < M1.
7. The display panel according to claim 2, wherein the second non-display region further includes a second non-display region adjacent to the first display region in the second direction; the shift register group further comprises a second shift register group positioned in the second non-display area and a third shift register group positioned in the second non-display area, the second shift register group comprises a plurality of cascaded second shift registers, and the third shift register group comprises a plurality of cascaded third shift registers;
the driving signal output end of the second shift register is electrically connected with the second pixel unit row and transmits a driving signal to the second pixel unit row; and the driving signal output end of the third shift register is electrically connected with the first pixel unit row and outputs driving signals to the first pixel unit row.
8. The display panel of claim 7, wherein the cascade shift register comprises cascade output transistors, wherein the second shift register comprises second output transistors, and wherein the width of the cascade output transistors is smaller than the width of the second output transistors along the second direction.
9. The display panel according to claim 8, wherein the width-to-length ratio of the cascode output transistor is a2, and the width-to-length ratio of the second output transistor is A3, a2 < A3.
10. The display panel according to claim 7, wherein the second shift registers are electrically connected to the second pixel unit rows in a one-to-one correspondence, and the number of the cascaded shift registers is the same as the number of the second shift registers.
11. The display panel according to claim 1, wherein the shift register comprises a plurality of transistors, the number of transistors included in the first shift register is N1, the number of transistors included in the cascade shift register is N2, where N2 < N1.
12. A display device comprising the display panel according to any one of claims 1 to 11.
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| CN110619835B (en) * | 2019-09-30 | 2022-07-22 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113838398B (en) * | 2020-06-24 | 2023-07-18 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN113011353B (en) * | 2021-03-25 | 2022-10-11 | 厦门天马微电子有限公司 | Display panel and display device |
| CN113380310A (en) * | 2021-06-04 | 2021-09-10 | 上海中航光电子有限公司 | Display panel and display device |
| WO2023023944A1 (en) * | 2021-08-24 | 2023-03-02 | 京东方科技集团股份有限公司 | Display substrate, and display device |
| WO2024000496A1 (en) * | 2022-06-30 | 2024-01-04 | 京东方科技集团股份有限公司 | Gate driving circuit and display panel |
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| CN109410761A (en) * | 2018-10-30 | 2019-03-01 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109459898A (en) * | 2018-12-21 | 2019-03-12 | 武汉天马微电子有限公司 | Display panel and display device |
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| KR102650352B1 (en) * | 2016-12-29 | 2024-03-21 | 엘지디스플레이 주식회사 | Shift register and display device comprising the same |
| CN107731151B (en) * | 2017-11-30 | 2020-12-22 | 信利（惠州）智能显示有限公司 | Array substrate and display device |
| CN108597438B (en) * | 2018-07-03 | 2020-12-15 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and driving method thereof and display device |
| CN109192121B (en) * | 2018-09-28 | 2021-09-28 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109272921B (en) * | 2018-11-23 | 2022-02-22 | 合肥京东方显示技术有限公司 | Grid driving circuit and driving method thereof, display panel and display device |
| CN109459901B (en) * | 2018-12-25 | 2021-07-23 | 武汉天马微电子有限公司 | Display panel and display device |
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| CN109459898A (en) * | 2018-12-21 | 2019-03-12 | 武汉天马微电子有限公司 | Display panel and display device |
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