CN109863581B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN109863581B
CN109863581B CN201780063822.6A CN201780063822A CN109863581B CN 109863581 B CN109863581 B CN 109863581B CN 201780063822 A CN201780063822 A CN 201780063822A CN 109863581 B CN109863581 B CN 109863581B
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diffusion region
semiconductor substrate
main surface
semiconductor device
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CN109863581A (en
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柳振一郎
野中裕介
野间诚二
樱井晋也
池浦奖悟
笠原淳志
泷泽伸
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Denso Corp
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Denso Corp
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Abstract

The semiconductor device includes: a semiconductor substrate (10) having a diode formation region (Di); upper diffusion regions (20, 50, 70) of a first conductivity type formed on a surface layer of a main surface (10a) of the semiconductor substrate in the diode formation region; and a second conductivity type lower diffusion region (30, 60, 80) formed at a position deeper than the upper diffusion region with respect to the main surface in the depth direction of the semiconductor substrate, and having an impurity concentration higher than that of the semiconductor substrate. The lower diffusion region forms a PN junction surface (S) that is joined to the upper diffusion region at a position deeper than the main surface, and the lower diffusion region in the diode-forming region has a local maximum point (P, P1, P2) that represents a local maximum in concentration in the impurity concentration characteristics of the lower diffusion region.

Description

Semiconductor device and method for manufacturing the same
Cross reference to related applications
The present application is based on Japanese patent application No. 2016-.
Technical Field
The present disclosure relates to a semiconductor device including a zener diode and a method of manufacturing the same.
Background
A constant voltage power supply using a zener diode is known. Although a constant voltage power supply is used also in a monitoring IC or the like of a battery mounted on a vehicle, high-precision voltage control is required for power supply to the IC or the like.
Conventionally, in a PN junction between an N-type epitaxial layer and a P-type diffusion layer, a zener voltage is uniquely determined depending on the concentrations of the two. In contrast, in the semiconductor device disclosed in patent document 1, the first diffusion region and the second diffusion region are provided in the semiconductor substrate, and the impurity concentrations of the two diffusion regions of the PN junction can be arbitrarily controlled. Then, desired zener characteristics are obtained by controlling the impurity concentration of the diffusion region.
Documents of the prior art
Patent document
Patent document 1: japanese patent application laid-open No. 2010-239015
Disclosure of Invention
However, it is known that there is a variation in zener voltage with time caused by breakdown (japanese: droop). It is presumed that the characteristic variation is caused by the trapping of hot carriers generated by the breakdown phenomenon by surface defects of the semiconductor substrate.
In the semiconductor device described in patent document 1, in a junction portion formed by overlapping the first diffusion region and the second diffusion region, a breakdown voltage due to the overlap is reduced. Then, breakdown occurs at a portion corresponding to the overlap. In this configuration, the portion corresponding to the overlap is a three-dimensional region, and the breakdown phenomenon occurs somewhere in the three-dimensional region, but the position is not determined. I.e. the exact location where the breakdown occurs cannot be controlled.
Since the state of generation of hot carriers and trapping of the hot carriers into surface defects differs depending on the position where breakdown occurs, the position where breakdown occurs is uncertain and becomes a cause of increasing the temporal variation amount of the zener voltage. Further, a temporal variation in the zener voltage may hinder highly accurate voltage control.
Accordingly, an object of the present disclosure is to provide a semiconductor device capable of suppressing a variation in zener voltage, and to provide a method for manufacturing the semiconductor device.
A semiconductor device according to a first aspect of the present disclosure includes: a semiconductor substrate having a diode forming region; an upper diffusion region of the first conductivity type formed in a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a second conductivity type lower diffusion region formed deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region forming a PN junction surface joined to the upper diffusion region at a position deeper than the main surface, and having a maximum point indicating a maximum value of concentration in an impurity concentration characteristic (profile) of the lower diffusion region in the diode forming region.
This can increase the electric field at the maximum point of the impurity concentration in the lower diffusion region, and thus can easily cause the breakdown phenomenon at the maximum point. The designer can arbitrarily determine the impurity concentration and the peak position thereof in the lower diffusion region, and can control the position where the breakdown phenomenon occurs. That is, the variation factor of the zener voltage can be suppressed to the minimum.
Further, since the PN junction surface between the upper diffusion region and the lower diffusion region is formed deeper than the main surface of the semiconductor substrate, the probability of trapping by surface defects existing on the main surface when hot carriers are generated can be reduced. That is, the amount of zener voltage variation can be reduced.
Thus, according to the semiconductor device, the variation factor of the zener voltage is minimized, and the characteristic variation amount at the time of breakdown can be suppressed.
A method for manufacturing a semiconductor device according to a second aspect of the present disclosure includes: preparing a semiconductor substrate; implanting an impurity into a surface layer of a main surface of a semiconductor substrate to form a lower implanted region of a second conductivity type so as to have a rotationally symmetric shape when the main surface is viewed from the front; after forming the lower implant region, diffusing the lower implant region by annealing; implanting an impurity into a surface layer of the main surface of the semiconductor substrate after diffusion by annealing of the lower implanted region, and forming an upper implanted region of the first conductivity type in a position shallower than the lower implanted region with respect to the main surface so as to be in a rotationally symmetric shape concentric with the lower implanted region; and after forming the upper implantation region, forming a lower diffusion region by diffusing the lower implantation region by annealing, and forming an upper diffusion region by diffusing the upper implantation region.
This makes it possible to form a local maximum point at which the impurity concentration has a local maximum value on the axis of rotational symmetry of the lower implanted region, thereby minimizing the variation factor of the zener voltage.
In addition, a semiconductor device according to a third aspect of the present disclosure includes: a semiconductor substrate of a second conductivity type having a diode formation region; an upper diffusion region of the first conductivity type formed in a surface layer of a main surface of the semiconductor substrate in the diode formation region; a lower diffusion region of the second conductivity type formed deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, and having an impurity concentration higher than that of the semiconductor substrate; and a second-conductivity-type counter electrode region formed on a surface layer of the main surface of the diode formation region and having an impurity concentration higher than that of the semiconductor substrate, wherein an inter-electrode region of the second conductivity type having an impurity concentration higher than that of the semiconductor substrate is formed on the surface layer of the main surface and in a region between the upper diffusion region and the counter electrode region.
Thus, when a breakdown (break down) occurs, the penetration of the depletion layer extending to the surface layer of the main surface between the upper diffusion region and the counter electrode region can be suppressed, and the increase in resistance in the current path can be suppressed. This can suppress the variation in zener voltage.
A method for manufacturing a semiconductor device according to a fourth aspect of the present disclosure includes the steps of: preparing a semiconductor substrate of a second conductivity type; implanting an impurity into a surface layer of a main surface of a semiconductor substrate to form a lower implanted region of a second conductivity type having an impurity concentration higher than that of the semiconductor substrate; after forming the lower implant region, diffusing the lower implant region by annealing; implanting impurities into a surface layer of the diffused lower implanted region after diffusion by annealing of the lower implanted region, thereby forming an upper implanted region of the first conductivity type at a position shallower than the lower implanted region with respect to the main surface; after forming the upper implantation region, forming a lower diffusion region by diffusing the lower implantation region by annealing, and forming an upper diffusion region by diffusing the upper implantation region; in addition, an impurity is implanted into the surface layer of the semiconductor substrate at a position separated from the lower implantation region to form a second conductivity type counter electrode implantation region; and forming an inter-electrode region having an impurity concentration higher than that of the semiconductor substrate in a region on the surface layer of the semiconductor substrate and between the counter electrode implantation region and the lower implantation region.
Thus, when the breakdown occurs, the penetration of the depletion layer spreading to the surface layer of the main surface between the upper diffusion region and the counter electrode region can be suppressed, and the increase in the resistance in the current path can be suppressed. This can suppress the variation in zener voltage.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent with reference to the attached drawings and the following detailed description. In the drawings, there is shown in the drawings,
FIG. 1 is a cross-sectional view and a top surface of a semiconductor device according to a first embodiment,
FIG. 2 is a sectional view showing a step of preparing a semiconductor substrate,
FIG. 3 is a sectional view showing a step of forming a lower implantation region,
FIG. 4 is a sectional view showing a first annealing step,
FIG. 5 is a sectional view showing a step of forming an upper implantation region,
FIG. 6 is a sectional view showing a second annealing step,
FIG. 7 is a graph showing three-dimensional characteristics of impurity concentrations,
FIG. 8 is a graph showing a change with time of the amount of fluctuation of the Zener voltage,
FIG. 9 is a sectional view of a semiconductor device in a second embodiment,
FIG. 10 is a sectional view showing a step of forming a lower implantation region,
FIG. 11 is a sectional view showing a first annealing step,
FIG. 12 is a sectional view showing a step of forming an upper implanted region,
FIG. 13 is a sectional view of a semiconductor device in a third embodiment,
FIG. 14 is a sectional view showing a step of forming a lower implantation region and an electrode implantation region,
FIG. 15 is a sectional view showing a first annealing step,
FIG. 16 is a sectional view showing a step of forming an upper implantation region and an inter-electrode implantation region,
fig. 17 is a sectional view of a semiconductor device according to a fourth embodiment.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or equivalent portions are denoted by the same reference numerals.
(first embodiment)
First, a schematic configuration of the semiconductor device of the present embodiment will be described with reference to fig. 1.
The semiconductor device includes a zener diode as an element, and is introduced into a power supply circuit to function as a constant voltage power supply, for example.
As shown in fig. 1, the semiconductor device 100 includes a semiconductor substrate 10, an upper diffusion region 20, a lower diffusion region 30, and a silicide block layer 40.
The semiconductor substrate 10 is a part of a semiconductor wafer of N conductivity type, and particularly, a part of the main surface 10a side is illustrated in fig. 1. The semiconductor substrate 10 has a diode formation region Di. In diode forming region Di, upper diffusion region 20 and lower diffusion region 30, which will be described later, are formed to form a PN junction diode as an element. The P-conductive type upper diffusion region 20 functions as an anode, and the N-conductive type semiconductor substrate 10 functions as a cathode. In this embodiment, the N conductivity type corresponds to the second conductivity type, and the P conductivity type corresponds to the first conductivity type.
The upper diffusion region 20 is a P-conductivity-type semiconductor region. The upper diffusion region 20 is formed in the surface layer of the semiconductor substrate 10 on the main surface 10a side so as to be exposed to the main surface 10a of the semiconductor substrate 10. As shown in fig. 1, the upper diffusion region 20 is formed so as to be rotationally symmetric with respect to an axis a orthogonal to the main surface 10 a. In particular, the upper diffusion region 20 in the present embodiment is formed in a substantially perfect circle shape centered on a point passing through the axis a when the main surface 10a is viewed from the front. As shown in fig. 1, the cross-sectional shape of the upper diffusion region 20 passing through the axis a has a structure in which the vicinity of the axis a is recessed. Namely, it is formed in a disk shape with a central depression. The axis a in the present embodiment coincides with the axis of symmetry, which will be described later. The upper diffusion region 20 in the present embodiment has a substantially perfect circle when the main surface 10a is viewed from the front and has a shape of a so-called rotor, but is not necessarily required to have a rotor shape. For example, when the main surface 10a is viewed from the front, it may have an n-fold symmetrical shape. Specifically, an ellipse, a capsule shape (double symmetry), a regular triangle (triple symmetry), a square (quadruple symmetry), or the like may be used.
The lower diffusion region 30 is an N-conductivity type semiconductor region. The lower diffusion region 30 is formed to cover the upper diffusion region 20. The lower diffusion region 30 is also formed rotationally symmetrical with respect to the axis a, as in the upper diffusion region 20, and particularly, the lower diffusion region 30 in the present embodiment is formed in a substantially perfect circle shape centered on a point passing through the axis a when the main surface 10a is viewed from the front. The shape of the lower diffusion region 30 when the main surface 10a is viewed from the front is not limited to a perfect circle, and may be formed so as to be n-fold symmetric.
Since the lower diffusion region 30 is formed adjacent to the upper diffusion region 20, a PN junction surface S is formed between the N-conductive lower diffusion region 30 and the P-conductive upper diffusion region. As described above, since the upper diffusion region 20 is recessed on the opposite surface not exposed on the main surface 10a, the PN junction surface S is also formed in the same shape. That is, the PN junction surface S is formed in a concave shape mainly in the upper diffusion region 20.
In the present embodiment, the lower diffusion region 30 completely covers the upper diffusion region 20, and a part thereof is exposed on the main surface 10 a. That is, when the main surface 10a is viewed from the front, the lower diffusion region 30 is exposed to the main surface 10a with respect to a region having a center of formation other than the outer edge of the upper diffusion region 20. In other words, when the main surface 10a is viewed from the front, the upper diffusion region 20, the lower diffusion region 30, and the N-type semiconductor region of the semiconductor substrate 10 are formed to extend concentrically around the point where the axis a intersects the main surface 10 a.
As described above, in the semiconductor device 100, the P-type semiconductor region of the upper diffusion region 20, the lower diffusion region 30, and the N-type semiconductor region of the semiconductor substrate 10 form a PN junction to form a diode. The P-conductive upper diffusion region 20 functions as an anode, and the N-conductive semiconductor substrate 10 functions as a cathode.
The silicide block layer 40 is an insulating film, and in the present embodiment, is made of, for example, SiO2And (4) forming. The silicide block layer 40 is formed in an annular shape around a point where the axis a intersects the main surface 10 a. In the semiconductor device 100 of the present embodiment, the upper diffusion region 20 and the lower diffusion region 30 are exposed on the main surface 10a, and the semiconductor region of the semiconductor substrate 10 is exposed outside thereof. The silicide block layer 40 is formed to cover the semiconductor substrate 1 from the outer edge of the upper diffusion region 20 through the lower diffusion region 300, face of the semiconductor region. That is, a PN junction line L1 extending between P-type upper diffusion region 20 and N-type semiconductor region exposed on main surface 10a and a boundary line L2 extending between lower diffusion region 30 and semiconductor substrate 10 are formed.
In addition, the silicide block layer 40 is formed for the following purpose: when a silicide electrode, for example, including cobalt, which functions as an electrode for the anode and the cathode, is laminated and formed on the main surface 10a, electrical insulation between the P-conductive upper diffusion region 20 and the N-conductive lower diffusion region 30 or the semiconductor substrate 10 is maintained.
Next, a method for manufacturing the semiconductor device 100 will be described with reference to fig. 2 to 6 and fig. 1.
First, as shown in fig. 2, a semiconductor substrate 10 formed to have N conductivity type is prepared.
Then, a photoresist (not shown) having a circular shape with a diameter R is laminated on the main surface 10a, and phosphorus or arsenic is ion-implanted. The ion implantation is performed at the same energy on one surface 10a, and the implantation depth is made substantially constant. Thereby, as shown in fig. 3, N-conductivity type lower implanted region 31 having a diameter R is formed. That is, a disk-shaped N-type conductive region having the axis a as a rotational symmetry axis is formed. The lower implanted region 31 is a region before diffusion by annealing, and becomes the lower diffusion region 30 after two annealing steps described later.
After the lower implantation region 31 is formed, the photoresist, not shown, is removed, and a first annealing step is performed. Through the annealing step, the impurity forming the lower implanted region 31 as shown in fig. 4 diffuses into the semiconductor substrate 10. In the first annealing step, impurity region 32 formed by thermally diffusing lower implant region 31 does not diffuse to the extent of lower diffusion region 30 shown in fig. 1.
After the first annealing step, a photoresist (not shown) hollowed into a perfect circle having the same center as that of the lower implantation region 31 and a diameter smaller than that of the impurity region 32 shown in fig. 4 is laminated on the main surface 10a, and boron is ion-implanted. The ion implantation is performed at the same energy on one surface 10a, and the implantation depth is made substantially constant. Thereby, as shown in fig. 5, P-conductive upper implant region 21 surrounded by impurity region 32 is formed. That is, a disk-shaped P-type conductive region having the axis a as a rotational symmetry axis is formed. The upper implantation region 21 is a region before diffusion by annealing, and becomes the upper diffusion region 20 after a second annealing step described later.
After the upper implantation region 21 is formed, the photoresist, not shown, is removed, and a second annealing step is performed. As shown in fig. 6, the upper implantation region 21 is thermally diffused and the impurity region 32 in which the lower implantation region 31 is diffused to some extent is further thermally diffused by the second annealing step. The upper implantation region 21 after the second annealing step is diffused into a region corresponding to the upper diffusion region 20, and the lower implantation region 31 is diffused into a region corresponding to the lower diffusion region 30.
The depth of formation of the thermally diffused lower diffusion region 30 is preferably designed to be substantially the same as the diameter R of the ion implantation in the lower implantation region 31. The annealing temperature, the ion implantation energy, and the impurity concentration may be determined by sharing the parameters with other elements formed on the semiconductor substrate 10, and the values may be difficult to change. Therefore, designing the formation depth of the lower diffusion region 30 to be substantially the same as the diameter R of the ion implantation of the lower implantation region 31 means that the formation radius of the lower implantation region 31 is matched to the assumed formation depth of the lower diffusion region 30.
However, before the second annealing step, a peak is present at a position deeper than the upper implantation region 21 on the axis a due to the impurity concentration of the impurity region 32 of the lower implantation region 31. Therefore, when the upper implantation region 21 is thermally diffused through the second annealing step, the conductivity type near the center of the disk-shaped upper implantation region 21 is not easily inverted. Thus, after the second annealing step is performed, as shown in fig. 6, the cross-sectional shape of the upper diffusion region 20 passing through the axis a has a structure in which the vicinity of the axis a is recessed as shown in fig. 1. That is, the upper diffusion region 20 is formed in a disc shape with a central depression. That is, the PN junction surface S between the upper diffusion region 20 and the lower diffusion region 30 is formed in a concave shape mainly in the upper diffusion region 20.
In fig. 6, the contour lines shown in the lower diffusion region 30 indicate contour lines of impurity concentration, showing that the peak of impurity concentration in the lower diffusion region 30 is located below the recess in the upper diffusion region 20.
After the second annealing step, as shown in fig. 1, the silicide block layer 40 is formed so as to extend across the PN junction line L1 between the P-type upper diffusion region 20 and the N-type semiconductor region exposed on the main surface 10a and the boundary L2 between the lower diffusion region 30 and the semiconductor substrate 10.
The semiconductor device 100 can be manufactured by a manufacturing method including the above steps.
Next, the operation and effects of the semiconductor device 100 and the method for manufacturing the same in this embodiment will be described.
Since the semiconductor device 100 shown in fig. 1 and 6 is formed such that the upper diffusion region 20 and the lower diffusion region 30 are substantially rotationally symmetric with respect to the axis a, the impurity characteristics of each are also substantially rotationally symmetric with respect to the axis a. The inventors have simulated specific impurity characteristics using a computer. The results of the simulation are shown in fig. 7.
As shown in fig. 7, lower diffusion region 30 formed in diode forming region Di has local maximum point P where the impurity concentration is local maximum. In the present embodiment, particularly, only one local maximum point P is provided in the lower diffusion region 30. The maximum point P in the present embodiment is located on the axis a and below the PN junction surface S.
In general, in a PN junction zener diode, when a reverse bias is applied, an electric field increases between portions of the N-conductive type region and the P-conductive type region where the impurity concentration is high, and a breakdown phenomenon is likely to occur. In the case of the semiconductor device 100 of the present embodiment, the portion of the lower diffusion region 30 indicating N conductivity in which the impurity concentration is high is not three-dimensionally distributed as in the conventional case, but is defined as zero-dimensional (dot), and therefore, the portion in which the breakdown phenomenon occurs can be specified as a dot. That is, the occurrence position of the breakdown phenomenon in the semiconductor device 100 can be fixed to a substantially predetermined position (local maximum point P).
The reason why the amount of change with time of the zener voltage is increased is presumed to be: the generation sources of the breakdown phenomenon are three-dimensionally distributed, and the generation of the breakdown phenomenon is not determined, but the generation position of the breakdown phenomenon can be determined as a point in the semiconductor device 100 of the present embodiment. This makes it possible to limit the position of occurrence of the breakdown phenomenon compared to a conventional configuration in which the breakdown phenomenon occurs three-dimensionally, and suppress the temporal variation in the zener voltage compared to the conventional configuration, as shown in fig. 8. Further, for example, when a zener diode included in the semiconductor device 100 is used for a constant voltage power supply, the output voltage can be controlled with high accuracy regardless of the passage of time.
In addition, the semiconductor device 100 of the present embodiment has a concave structure in which the PN junction surface S is depressed when the upper diffusion region 20 is mainly used. In particular, in the present embodiment, the structure is recessed near the axis a. As a result, as shown in fig. 7, an impurity distribution having a peak at the lower part of the recessed portion of the upper diffusion region 20 in the lower diffusion region 30 can be easily formed. In other words, the maximum value of the impurity concentration can be easily formed in a dot shape.
In the semiconductor device 100 of the present embodiment, the upper diffusion region 20 and the lower diffusion region 30 have a rotationally symmetric shape, particularly a perfect circle shape, when the one surface 10a is viewed from the front. This makes it possible to make the maximum value of the impurity concentration in the lower diffusion region 30 on the axis of rotational symmetry (axis a in the present embodiment) and to easily form the maximum value of the impurity concentration in a dot shape.
In the manufacturing process of the semiconductor device 100 according to the present embodiment, the formation diameter R of the lower implantation region 31, which is a precursor region of the lower diffusion region 30, is set to be substantially the same as the assumed formation depth of the lower diffusion region 30. This makes it possible to easily form the local maximum of the impurity concentration in the lower diffusion region 30 in a dot shape. For example, if the formation diameter R of the lower implantation region 31 is larger than the assumed formation depth of the lower diffusion region 30, the maximum portion of the impurity concentration is likely to be distributed in one or two dimensions extending in the direction along the main surface 10 a. Alternatively, if the formation diameter R of the lower implantation region 31 is smaller than the assumed formation depth of the lower diffusion region 30, the maximum portion of the impurity concentration is likely to be distributed in one or two dimensions extending in the depth direction of the semiconductor substrate 10. In contrast, if the formation diameter R of the lower implantation region 31 is made substantially equal to the assumed formation depth of the lower diffusion region 30, the maximum impurity concentration in the lower diffusion region 30 can be easily made to be a point.
In addition, in the manufacturing process of the semiconductor device 100 of the present embodiment, particularly in the formation of the upper implantation region 21, impurities are ion-implanted at a uniform depth. Thus, in the second annealing step, the conductivity type is easily inverted in the portion of the lower diffusion region 30 where the impurity concentration is small in the impurity region 32 which is the precursor region, and the concave structure of the PN junction surface S can be easily formed. That is, as described above, the maximum impurity concentration of the lower diffusion region 30 can be easily made to be a point.
The semiconductor device 100 of the present embodiment is formed such that the lower diffusion region 30 covers the upper diffusion region 20, and is exposed on the main surface 10 a. Thus, in comparison with the configuration in which the lower diffusion region 30 is not exposed to the main surface, the extension of the depletion layer formed between the P-conductive type upper diffusion region 20 and the N-conductive type region along the main surface 10a can be suppressed in the surface layer of the main surface 10 a. This can suppress trapping of hot carriers in the energy level due to the surface defects existing in the vicinity of the main surface 10a, and suppress the temporal variation of the zener voltage.
However, the semiconductor device 100 of the present embodiment includes the silicide block layer 40 on the main surface 10 a. This can prevent electrical conduction due to silicide from occurring between the P-conductive upper diffusion region 20 and the N-conductive lower diffusion region 30 or the semiconductor substrate 10 when the silicide electrode is laminated and formed on the main surface 10 a. For this purpose, when the lower diffusion region 30 is exposed to the main surface 10a, the silicide block layer 40 should be formed so as to extend across the PN junction line L1 between the upper diffusion region 20 and the lower diffusion region 30 and so as to extend across the boundary L2 between the lower diffusion region 30 and the semiconductor region in the semiconductor substrate 10. In the case where the lower diffusion region 30 is not exposed to the main surface 10a, it should be formed so as to extend across the boundary between the upper diffusion region 20 and the semiconductor region in the semiconductor substrate 10.
(second embodiment)
In the first embodiment, the PN junction surface S between the upper diffusion region 20 and the lower diffusion region 30 is a concave surface when the upper diffusion region 20 is mainly used, but may be a convex surface.
As shown in fig. 9, the semiconductor device 110 according to the present embodiment includes an upper diffusion region 50 and a lower diffusion region 60 having different shapes from those of the first embodiment. The semiconductor device 110 has a convex portion C having a convex surface in a cross section of the PN junction surface S. The upper diffusion region 50 and the lower diffusion region 60 of the semiconductor device 110 are also in the shape of a perfect circle when the main surface 10a is viewed from the front, and constitute a rotation body having an axis of symmetry B passing through the center of the perfect circle and orthogonal to the main surface 10 a. The concave portion C has a convex apex on the axis B.
In the present embodiment, the impurity concentration of the lower diffusion region 60 has a peak in the vicinity of the lower portion of the concave portion formed outside the convex portion C of the PN junction surface S. That is, in the cross section shown in fig. 9, there is a maximum point of the impurity concentration at the points shown by the points P1 and P2. Actually, since the upper diffusion region 50 and the lower diffusion region 60 are disk-shaped, the local maximum points P1 and P2 are also part of a circle having the axis B as a symmetry axis. That is, in the present embodiment, the plurality of local maximum points of the impurity concentration in the lower diffusion region 60 are one-dimensionally (specifically, circularly) distributed around the axis B.
By making the PN junction surface S convex in this way, the local maximum points of the impurity concentration in the lower diffusion region 60 can be distributed one-dimensionally. As in the first embodiment, the local maximum point of the impurity concentration is useful as a generation position of the breakdown phenomenon, and therefore, the generation position of the breakdown phenomenon can be determined as a line in the semiconductor device 110. Thus, compared to a conventional configuration in which the breakdown phenomenon occurs three-dimensionally, the position of occurrence of the breakdown phenomenon can be limited, and the temporal variation of the zener voltage can be suppressed. Further, for example, when a zener diode included in the semiconductor device 110 is used for a constant voltage power supply, the output voltage can be controlled with high accuracy regardless of the lapse of time.
Hereinafter, a method for manufacturing the semiconductor device 110 will be briefly described.
First, as in the first embodiment, the semiconductor substrate 10 is prepared as shown in fig. 2.
Next, as shown in fig. 10, phosphorus or arsenic is ion-implanted to form a lower implantation region 61. The lower injection region 61 is formed in a rotationally symmetrical shape with the axis B as a symmetry axis. In particular, in the present embodiment, the ring shape is formed. The lower injection region 31 in the first embodiment is a perfect circle when the main surface 10a is viewed from the front, but the lower injection region 61 in the present embodiment is an annular ring shape with a hollow portion in the vicinity of the center. Since fig. 10 is a cross-sectional view, two lower injection regions 61 are illustrated as being separated from each other, but are actually continuous in the front-rear direction of the paper. The lower implantation region 61 is a region that becomes the lower diffusion region 60 by two thermal diffusions in a subsequent process.
Next, a first annealing step is performed. Thereby, as shown in fig. 11, the lower implantation region 61 is thermally diffused to form an N-conductive impurity region 62. Since lower implant region 61 before the annealing step is annular, the concentration structure of the impurity in impurity region 62 after thermal diffusion has a substantially annular structure in which the higher concentration portion is distributed in a circular shape having axis B as a symmetry axis.
Next, as shown in fig. 12, boron is ion-implanted to form an upper implanted region 51. Upper implanted region 51 is formed to be covered with impurity region 62. Specifically, in impurity region 61 which is a precursor region of lower diffusion region 60, upper implant region 51 is formed above the portion where the concentration has a peak. That is, the upper injection region 51 is formed in a rotationally symmetric shape with the axis B as a symmetry axis. In particular, in the present embodiment, the upper injection region 51 is formed in an annular shape. The upper injection region 21 in the first embodiment is a perfect circle when the main surface 10a is viewed from the front, but the upper injection region 51 in the present embodiment is hollowed out in an annular shape near the center. Since fig. 12 is a cross-sectional view, the two upper injection regions 51 are illustrated as being separated from each other, but are actually continuous in the front-rear direction of the paper. The upper implantation region 51 is a region that becomes the upper diffusion region 50 by two thermal diffusions in a subsequent process.
Next, a second annealing step is performed. As a result, as shown in fig. 9, the upper implantation region 51 is thermally diffused, and the impurity region 62 in which the lower implantation region 61 is diffused to some extent is further thermally diffused. The upper implantation region 51 after the second annealing step is diffused into a region corresponding to the upper diffusion region 50, and the lower implantation region 61 is diffused into a region corresponding to the lower diffusion region 60.
At this time, the annular shape of the impurity concentration distribution of the impurity region 62 which is a precursor region of the lower diffusion region 60 is substantially maintained, and the maximum value of the impurity concentration of the lower diffusion region 60 is configured to be a circular shape as described above. The silicide block layer 40 is formed so as to straddle the PN junction line between the P-type upper diffusion region 50 and the N-type semiconductor region exposed on the main surface 10a and the boundary between the lower diffusion region 60 and the semiconductor substrate 10.
As described above, the semiconductor device 110 having the convex PN junction surface S can be manufactured.
(third embodiment)
In the configuration having the lower diffusion regions 30 and 60 as exemplified in the first and second embodiments, the depletion layer at the time of occurrence of breakdown may spread over a wide region outside the lower diffusion regions 30 and 60 in the surface layer of the semiconductor substrate 10. This is presumably due to surface traps in the surface layer of the semiconductor device 10, and an increase in resistance of the current path between the upper diffusion regions 20 and 50 as the anode and the cathode occurs. Further, this increase in resistance may become an important factor for the temporal variation in zener voltage.
Therefore, as shown in fig. 13, semiconductor device 120 according to the present embodiment includes, in addition to upper diffusion region 70 and lower diffusion region 80, a cathode region 90 having an impurity concentration higher than that of semiconductor substrate 10 in diode forming region Di, and an inter-electrode region 91 functioning as an anode and formed between upper diffusion region 70 and cathode region 90. The cathode region 90 corresponds to a counter electrode region.
The upper diffusion region 70 and the lower diffusion region 80 in the present embodiment are formed in the same manner as the upper diffusion region 20 and the lower diffusion region 30 in the first embodiment, respectively. That is, the upper diffusion region 70 is a P-conductivity-type semiconductor region formed so as to be exposed to the main surface 10a, and the lower diffusion region 80 is an N-conductivity-type semiconductor region formed so as to cover the upper diffusion region 70 in the semiconductor substrate 10. Although the detailed structure is not described in the first embodiment, the PN junction surface S between the upper diffusion region 70 and the lower diffusion region 80 is also structurally controlled so as to have a concave shape and the break point is formed substantially as a point (zero dimension).
The cathode region 90 as the counter electrode region is an N-conductivity type semiconductor region having a higher concentration than the semiconductor substrate 10, and is an annular region concentric with the upper diffusion region 70 when the main surface 10a is viewed from the front. The cathode region 90 is exposed on the main surface 10a, and a cathode electrode is ohmically bonded to the exposed surface. In the present embodiment, the cathode region 90 and the lower diffusion region 80 are formed in the same step, and the average impurity concentration is substantially the same.
The inter-electrode region 91 is an N-conductive semiconductor region formed between the upper diffusion region 70 and the cathode region 90. The impurity concentration of the inter-electrode region 91 is higher than the impurity concentration of the semiconductor substrate 10. The inter-electrode region 91 is formed so as to be exposed on the main surface 10a, and thus the region surrounded by the cathode region 90 does not expose the N-conductivity-type region constituting the semiconductor substrate 10 on the main surface 10 a. In other words, the distribution of the impurities in the movement radius direction on the main surface 10a as viewed from the center of the upper diffusion region 70 spreads concentrically in the order of the P conductivity type of the upper diffusion region 70, the N conductivity type of the lower diffusion region 80 exposed on the main surface 10a, the N conductivity type of the inter-electrode region 91, and the N conductivity type of the cathode region 90.
In the semiconductor device 120 of the present embodiment, the inter-electrode region 91 is formed as a step different from the step of forming the lower diffusion region 80 and the cathode region 90. Accordingly, the impurity concentration of the inter-electrode region 91 can be controlled independently of the lower diffusion region 80 and the cathode region 90, and can be determined according to the intention of the designer. The impurity concentration of the inter-electrode region 91 needs to be lower than the impurity concentration of the cathode region 90 to which the cathode electrode is connected, and is preferably higher than the concentration of the semiconductor substrate 10 and lower than the maximum value of the impurity concentration of the lower diffusion region 80. The position where the impurity concentration of the lower diffusion region 80 becomes maximum in the present embodiment is the maximum point of the impurity concentration, and is formed almost as a point (zero dimension) to become a breakpoint. The impurity concentration of the inter-electrode region 91 is set to a lower concentration than the impurity concentration at the break point. This prevents breakdown in the vicinity of the inter-electrode region 91. In other words, in the lower diffusion region 80, the breakdown is intentionally caused to occur.
Regarding the method for manufacturing the semiconductor device 120, the description about the method for manufacturing the semiconductor device 100 in the first embodiment is referred to and explained with reference to fig. 14 to 16.
First, the semiconductor substrate 10 formed of N conductivity type is prepared.
Thereafter, as shown in fig. 14, the lower implantation region 81 is formed by ion implantation as in the first embodiment. At this time, the counter electrode implantation region 92 is formed by the same or different process as the lower implantation region 81. The lower injection region 81 is formed on the surface layer of the main surface 10a together with the counter electrode injection region 92. These regions are regions that become the lower diffusion region 80 and the cathode region 90, respectively, by an annealing process described later.
Thereafter, an annealing process is performed to thermally diffuse the impurities. As shown in fig. 15, the impurities in the lower implantation region 81 and the counter electrode implantation region 92 are diffused in the semiconductor substrate 10 by the annealing step to form a semiconductor region having a higher concentration than the semiconductor substrate 10.
Thereafter, ion implantation is performed on the region in which the lower implanted region 81 has been thermally diffused through an annealing process, thereby forming a P-conductive upper implanted region 71. Further, ion implantation is performed on the surface layer of the main surface 10a surrounded by the lower implantation region 81 and the counter electrode implantation region 92, thereby forming an N-conductive type inter-electrode implantation region 93.
Thereafter, the annealing step is performed again to thermally diffuse the impurities in the semiconductor regions. Thereby, the distribution of the impurities becomes the distribution as shown in fig. 13. Thereafter, the silicide block layer 40 is formed into an annular shape, thereby manufacturing the semiconductor device 120. The inner edge of the annular ring of silicide-barrier layer 40 is brought to the upper diffusion region 70 and the outer edge of the annular ring is brought to the cathode region 90. That is, the exposed portion of the lower diffusion region 80 on the main surface 10a and the inter-electrode region 91 are completely shielded by the silicide block layer 40.
The operation and effect of the semiconductor device 120 according to this embodiment will be described.
As described above, the depletion layer at the time of occurrence of breakdown may spread over a wide region outside the lower diffusion regions 30 and 60 in the surface layer of the semiconductor substrate 10, and this is presumably caused by surface traps in the surface layer of the semiconductor device 10. The semiconductor device 120 includes a cathode region 90, and an inter-electrode region 91 having a higher concentration than the semiconductor substrate 10 is provided in the semiconductor substrate 10a so as not to expose the N-conductive-type impurity layer constituting the semiconductor substrate 10. This makes it possible to create a situation in which the depletion layer extending from the upper diffusion region 70 is less likely to enter the inter-electrode region 91. Therefore, an increase in electrical resistance between the upper diffusion region 70 and the cathode region 90 can be suppressed. Accordingly, the temporal variation of the zener voltage can be suppressed.
(fourth embodiment)
In the third embodiment, the example of forming the inter-electrode implantation region 93 has been described as a step different from the ion implantation step involving the formation of the lower diffusion region 80 and the cathode region 90 when forming the inter-electrode region 91, but the step of forming the inter-electrode implantation region 93 can be omitted by bringing the formation positions of the lower diffusion region 80 and the cathode region 90 close to each other.
As shown in fig. 17, the semiconductor device 130 according to the present embodiment is formed with the inter-electrode region 91 as a portion where the lower diffusion region 80 and the cathode region 90 as the counter electrode region overlap each other. The inter-electrode region 91 is of N conductivity type, and has a concentration higher than the impurity concentration constituting the semiconductor substrate 10, as in the third embodiment.
In order to realize this, for example, in the process of forming the lower implantation region 81 and the counter electrode implantation region 92 described with reference to fig. 14 in the third embodiment, the layout is performed by shortening the distance between them. Thus, the regions where the impurity thermally diffuses overlap each other in the annealing step after the ion implantation, and the inter-electrode region 91 is formed. With this method and method, the number of steps of ion implantation for forming the inter-electrode implantation region 93 can be reduced, and a situation in which the depletion layer extending from the upper diffusion region 70 is less likely to enter the inter-electrode region 91 can be generated.
(other embodiments)
The present disclosure has been described in terms of embodiments, but it is to be understood that the disclosure is not limited to the embodiments and constructions. The present disclosure also includes various modifications and equivalent variations. In addition, various combinations and modes are included, and other combinations and modes including only one element, more than one element, or less than one element are also within the scope and spirit of the present disclosure.
In the above-described embodiments, the upper diffusion regions 20, 50, and 70 and the upper implantation regions 21, 51, and 71 are formed in a perfect circle shape with the axis a or the axis B as a symmetry axis, but the shapes of the upper diffusion regions 20, 50, and 70 and the upper implantation regions 21, 51, and 71 when viewed from the front of the main surface 10a are not limited to a perfect circle, and may be any n-fold symmetrical shape. Specifically, an ellipse, a capsule shape (double symmetry), a regular triangle (triple symmetry), a square (quadruple symmetry), a regular pentagon (quintuple symmetry), a regular hexagon (sextuple symmetry), or the like may be used.
Similarly, the examples in which the lower diffusion regions 30, 60, and 80 and the lower injection regions 31, 61, and 81 are formed in a perfect circle shape with the axis a or the axis B as a symmetry axis have been described, but the shapes of the lower diffusion regions 30, 60, and 80 and the lower injection regions 31, 61, and 81 when viewed from the front of the main surface 10a are not limited to a perfect circle, and may be any n-fold symmetrical shape. In the two-fold symmetric shape, the maximum value of the impurity concentration is not a point but a line (one-dimensional) along the long side.
In addition, the lower diffusion regions 30, 60, and 80 corresponding to the upper diffusion regions 20, 50, and 70 preferably have similar shapes when viewed from the front of the main surface 10 a. Since the upper diffusion regions 20, 50, and 70 have symmetry with the corresponding lower diffusion regions 30, 60, and 80, the break points can be easily formed in the lower diffusion regions 30, 60, and 80 in one dimension or zero dimension lower than three dimensions.
In the above-described embodiments, the example in which the silicide block layer 40 is formed so as to be the same as the centers of the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 has been described, but the present invention is not limited thereto, and the centers of formation may be shifted. The silicide block layer 40 may not be necessary when the silicide-based electrode is not formed, and this is not an essential element.
In each of the above embodiments, the P conductivity type is used for the upper diffusion regions 20 and 50, and the N conductivity type is used for the lower diffusion regions 30 and 60. In addition, although an example in which an N-conductivity-type substrate is used as the semiconductor substrate has been described, any one of an N-conductivity type and a P-conductivity type may be used as the semiconductor substrate regardless of the conductivity types of the upper diffusion regions 20 and 50 and the lower diffusion regions 30 and 60. However, when the inter-electrode region 91 is provided, the counter electrode region corresponding to the cathode region 90 and the lower diffusion regions 30, 60, and 80 need to have the same conductivity type as the semiconductor substrate 10.
In the above embodiments, the lower diffusion regions 30, 60, and 80 are illustrated as being exposed to the main surface 10a while completely covering the corresponding upper diffusion regions 20, 50, and 70 in the semiconductor substrate 10, but the lower diffusion regions may be located only below the upper diffusion regions and not exposed to the main surface 10 a. In this case, by configuring the lower diffusion region to completely cover the upper diffusion region and expose it to the main surface 10a, the extension of the depletion layer formed between the P-conductive type upper diffusion regions 20, 50, 70 and the N-conductive type region along the main surface 10a can be suppressed in the surface layer of the main surface 10a, as compared with the configuration in which the lower diffusion regions 30, 60, 80 do not expose it to the main surface. This can suppress trapping of hot carriers in the energy level due to the surface defects existing in the vicinity of the main surface 10a, and suppress the temporal variation of the zener voltage. In this regard, it is more advantageous to provide the inter-electrode region 91.
In the above embodiments, the description has been focused on the formation of the diode forming region Di of the zener diode in the semiconductor substrate 10, but the formation of other elements in the region other than the diode forming region on the semiconductor substrate 10 is not prevented. For example, a MOSFET or an IGBT may be separately formed on the same semiconductor substrate 10.
In the third and fourth embodiments, the description has been given of the configuration in which the junction surfaces between the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 are formed in the concave shape, and the maximum points indicating the maximum values of the concentrations are formed in the impurity concentration characteristics of the lower diffusion regions 30, 60, 80, but the effect of suppressing the temporal variation of the zener voltage by forming the inter-electrode region 91 can be obtained compared to the conventional embodiment in which the junction surfaces between the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 are formed in the flat shape. That is, the effect of providing the inter-electrode region 91 can be achieved independently of the technical idea of forming the local maximum point indicating the local maximum in the impurity concentration characteristics of the lower diffusion regions 30, 60, and 80.

Claims (24)

1. A semiconductor device includes:
a semiconductor substrate (10) having a diode formation region (Di);
an upper diffusion region (20, 50, 70) of a first conductivity type formed in a surface layer of a main surface (10a) of the semiconductor substrate in the diode formation region; and
a lower diffusion region (30, 60, 80) of a second conductivity type formed at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate,
the lower diffusion region forms a PN junction surface (S) which is joined to the upper diffusion region at a position deeper than the main surface,
has a maximum point (P, P1, P2) indicating a maximum value of concentration in the impurity concentration characteristics of the lower diffusion region in the diode formation region,
the semiconductor substrate is of a second conductivity type,
the semiconductor device further comprises a second conductivity type counter electrode region (90) formed on the surface layer of the main surface of the diode formation region and having an impurity concentration higher than that of the semiconductor substrate,
forming a second-conductivity-type inter-electrode region (91) in a region on the surface layer of the main surface and between the upper diffusion region and the counter electrode region, the second-conductivity-type inter-electrode region (91) having an impurity concentration higher than that of the semiconductor substrate,
the inter-electrode region has an impurity concentration lower than the maximum point of the impurity concentration in the lower diffusion region.
2. The semiconductor device according to claim 1,
the upper diffusion region and the lower diffusion region are rotationally symmetrically distributed with an imaginary line passing through the maximum point and along the depth direction as an axis of symmetry (A, B), and the PN junction surface is a concave surface or a convex surface.
3. The semiconductor device according to claim 2,
the upper diffusion region and the lower diffusion region are shaped similar to each other when the main surface is viewed from the front.
4. The semiconductor device according to claim 2,
the upper diffusion region and the lower diffusion region are distributed in a right circular shape centered on the axis of symmetry when the principal surface is viewed from the front.
5. The semiconductor device according to claim 1,
the lower diffusion region is formed so as to cover the upper diffusion region, and a part of the lower diffusion region is exposed on the main surface.
6. The semiconductor device according to claim 1,
further comprises a silicide block layer (40) provided on the main surface,
the silicide block layer is formed so as to cross a PN junction line (L1, L2) between the upper diffusion region exposed on the main surface and the semiconductor region of the second conductivity type.
7. The semiconductor device according to claim 1,
the inter-electrode region is formed as an impurity region independent from the lower diffusion region and the counter electrode region.
8. The semiconductor device according to claim 1,
the inter-electrode region is formed by overlapping the lower diffusion region and the counter electrode region with an impurity of a second conductivity type.
9. A semiconductor device includes:
a semiconductor substrate (10) of a second conductivity type having a diode formation region (Di);
an upper diffusion region (20, 50, 70) of a first conductivity type formed in a surface layer of a main surface (10a) of the semiconductor substrate in the diode formation region;
a lower diffusion region (30, 60, 80) of a second conductivity type formed deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, and having an impurity concentration higher than that of the semiconductor substrate; and
a counter electrode region (90) of a second conductivity type formed on a surface layer of the main surface in the diode formation region and having an impurity concentration higher than that of the semiconductor substrate,
further, a second-conductivity-type inter-electrode region (91) is formed in a region on the surface layer of the main surface and between the upper diffusion region and the counter electrode region, the second-conductivity-type inter-electrode region (91) having an impurity concentration higher than that of the semiconductor substrate,
the impurity concentration of the inter-electrode region is set to a concentration lower than the maximum value of the impurity concentration in the lower diffusion region.
10. The semiconductor device according to claim 9,
the inter-electrode region is formed as an impurity region independent from the lower diffusion region and the counter electrode region.
11. The semiconductor device according to claim 9,
the inter-electrode region is formed by overlapping the lower diffusion region and the counter electrode region with an impurity of a second conductivity type.
12. A method for manufacturing a semiconductor device includes the steps of:
preparing a semiconductor substrate (10);
implanting an impurity into a surface layer of a main surface of the semiconductor substrate, and forming a second conductivity type lower implanted region (31, 61, 81) having an impurity concentration higher than that of the semiconductor substrate so as to have a rotationally symmetric shape when the main surface is viewed from the front;
after forming the lower implant region, diffusing the lower implant region by annealing;
implanting an impurity into a surface layer of a main surface of the semiconductor substrate after diffusion of the lower implanted region by annealing, and forming an upper implanted region (21, 51, 71) of a first conductivity type at a position shallower than the lower implanted region with respect to the main surface so as to have a rotationally symmetric shape concentric with the lower implanted region; and
forming a lower diffusion region (30, 60, 80) by diffusing the lower implant region by annealing after forming the upper implant region, and forming an upper diffusion region (20, 50, 70) by diffusing the upper implant region,
the semiconductor substrate is of a second conductivity type,
the method for manufacturing a semiconductor device further includes:
a counter electrode implantation region (92) formed by implanting an impurity into a surface layer of the semiconductor substrate at a position separated from the lower implantation region to form a second conductivity type; and
an inter-electrode region (91) having an impurity concentration higher than that of the semiconductor substrate is formed in a region on the surface layer of the semiconductor substrate and between the counter electrode implantation region and the lower implantation region.
13. The method for manufacturing a semiconductor device according to claim 12,
the lower implantation region and the upper implantation region are formed in similar shapes so that the upper diffusion region and the lower diffusion region have similar shapes when the main surface is viewed from the front.
14. The method for manufacturing a semiconductor device according to claim 12,
the upper injection region and the lower injection region are formed in a right circular shape having a center on a symmetry axis of rotational symmetry when the main surface is viewed from the front.
15. The method for manufacturing a semiconductor device according to claim 12,
in the process of forming the upper implantation region, impurities are implanted at a uniform depth.
16. The method for manufacturing a semiconductor device according to claim 12,
in the process of forming the lower implantation region, a diameter (R) when the main surface is viewed from the front surface is set to be the same as a formation depth of the lower diffusion region in a depth direction of the semiconductor substrate.
17. The method for manufacturing a semiconductor device according to claim 12, further comprising the step of:
a silicide block layer (40) is formed on the main surface so as to straddle the PN junction line between the upper diffusion region exposed on the main surface and the semiconductor region of the second conductivity type.
18. The method for manufacturing a semiconductor device according to claim 12,
the impurity concentration of the inter-electrode region is set to a concentration lower than the maximum value of the impurity concentration in the lower diffusion region.
19. The method for manufacturing a semiconductor device according to claim 12,
the inter-electrode region is formed by forming an inter-electrode implantation region (93) independent of the lower implantation region and the counter electrode implantation region, and by diffusion by annealing.
20. The method for manufacturing a semiconductor device according to claim 12,
the inter-electrode region is formed using the impurity diffused by the annealing of the lower implantation region and the impurity diffused by the annealing of the counter electrode implantation region.
21. A method for manufacturing a semiconductor device includes the steps of:
preparing a semiconductor substrate (10) of a second conductivity type;
implanting an impurity into a surface layer of the main surface of the semiconductor substrate to form a lower implanted region (31, 61, 81) of a second conductivity type having an impurity concentration higher than that of the semiconductor substrate;
after forming the lower implant region, diffusing the lower implant region by annealing;
implanting an impurity into a surface layer of the diffused lower implanted region after diffusion of the lower implanted region by annealing, thereby forming an upper implanted region (21, 51, 71) of a first conductivity type at a position shallower than the lower implanted region with respect to the main surface;
after forming the upper implant region, forming a lower diffusion region (30, 60, 80) by diffusing the lower implant region by annealing and forming an upper diffusion region (20, 50, 70) by diffusing the upper implant region;
in addition, an impurity is implanted into a surface layer of the semiconductor substrate at a position separated from the lower implantation region to form a second conductivity type counter electrode implantation region (92); and
an inter-electrode region (91) having an impurity concentration higher than that of the semiconductor substrate is formed in a region on the surface layer of the semiconductor substrate and between the counter electrode implantation region and the lower implantation region.
22. The method for manufacturing a semiconductor device according to claim 21, wherein,
the impurity concentration of the inter-electrode region is set to a concentration lower than the maximum value of the impurity concentration in the lower diffusion region.
23. The method for manufacturing a semiconductor device according to claim 21 or 22,
the inter-electrode region is formed by forming an inter-electrode implantation region (93) independent of the lower implantation region and the counter electrode implantation region, and by diffusion by annealing.
24. The method for manufacturing a semiconductor device according to claim 21 or 22,
the inter-electrode region is formed using the impurity diffused by the annealing of the lower implantation region and the impurity diffused by the annealing of the counter electrode implantation region.
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