CN109861788B - Method and device for realizing parallel CRC calculation - Google Patents
Method and device for realizing parallel CRC calculation Download PDFInfo
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Abstract
The invention discloses a method and a device for realizing parallel CRC calculation, which are characterized in that high n bits of a CRC initial value C are intercepted, XOR operation is carried out on the high n bits of the CRC initial value C and input parallel data D to generate a first intermediate result X, feedback XOR operation is carried out by utilizing the first intermediate result X to generate a second intermediate result Y, XOR operation is carried out between bits in the second intermediate result Y, and XOR operation is carried out between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z. The invention improves the universality of the CRC calculation implementation method, avoids matrix high power solving in the traditional parallel CRC calculation method, is easy to realize hardware and reduces the difficulty of parallel CRC calculation hardware design.
Description
Technical Field
The invention belongs to the technical field of parallel CRC (cyclic redundancy check) calculation, and particularly relates to a method and a device for realizing parallel CRC calculation.
Background
Errors are inevitable during the transmission of information, which may result in one or more frames transmitted over the link being corrupted and thus erroneous data being received by the receiving party. In order to improve the accuracy of receiving data by the receiver as much as possible, the receiver needs to perform error detection on the data when receiving the data, and the receiver can really receive the data only when the detection result is correct. Cyclic Redundancy Check (CRC) is one such error checking method, and is widely used in communication fields such as information transmission and data compression.
The CRC method is that at the transmitting end, the binary sequence to be transmitted is calculated by a certain rule, i.e. a generator polynomial, to generate a supervisory code, i.e. a CRC code, which is attached to the back of the original information, thereby forming a new binary sequence and then transmitting the new binary sequence. At the receiving end, a check is also made to determine whether the information has been corrupted during transmission, again based on such rules between the information code and the supervision code.
In principle, there are many kinds of CRC generator polynomials, commonly used are CRC-5, CRC-8, CRC-16, CRC-32, etc., and there are many kinds of generator polynomials for CRC of the same length, such as CRC16 and CRC-CCITT. CRC calculation is realized in serial and parallel modes, and the serial realization mode is simple and universal but low in efficiency; the parallel implementation mode is high in efficiency, the table lookup method or the matrix high power solution is usually adopted in the prior art, in the table lookup method, when the calculation data width or the generator polynomial is changed, a lookup table needs to be generated again, the universality is poor, the transportability is low, and the matrix high power solution is not easy to directly implement on hardware.
Disclosure of Invention
The invention aims to provide a method and a device for realizing parallel CRC calculation, which overcome the problems of poor universality and low portability in the prior art and are easy to realize on hardware.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for realizing parallel CRC calculation includes inputting parallel data D ═ D0D1…Dn-3Dn-2Dn-1]CRC initial value C ═ C0C1…Ck-3Ck-2Ck-1]And the input parallel data width n is not more than the CRC width k, and the implementation method of the parallel CRC calculation comprises the following steps:
step 1, obtaining the highest power k of a generator polynomial and the width n of input parallel data, and obtaining the arrangement e of all powers except 0 and k in the generator polynomial from small to large0<e1<e2<…<em-2<em-1And a number m;
step 2, intercepting high n bits of a CRC initial value C, and carrying out XOR operation with input parallel data D to generate a first intermediate result X;
step 3, utilizing the first intermediate result X to perform feedback XOR operation to generate a second intermediate result Y, Y [ i ]]＝X[i]⊕Y[i+k-e0]⊕Y[i+k-e1]⊕…⊕Y[i+k-em-1]，i＝{0,1,2,…,n-2,n-1}；
Step 4, carrying out XOR operation between the internal bits of the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{0,1,2,…,n-2,n-1}；
Step 5, carrying out XOR operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, Z [ i [ ] I [ ]]＝C[i-n]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{n,n+1,…,k-2,k-1}。
Further, the step 3 further comprises:
judging the expression i + k-e0，i+k-e1…i+k-em-1And whether the calculation result exceeds the range from 0 to n-1, and if so, the Y of the corresponding bit is assigned to be 0.
Further, after the step 4, the method further includes:
and judging whether n is equal to k, if so, skipping the step 5 and finishing the CRC calculation.
Further, the steps 4 and 5 further include:
judging the expression i-e0，i-e1…i-em-1And whether the calculation result exceeds the range from 0 to n-1, and if so, the Y of the corresponding bit is assigned to be 0.
The invention also provides a device for realizing parallel CRC calculation, and the input parallel data D ═ D0D1…Dn-3Dn- 2Dn-1]CRC initial value C ═ C0C1…Ck-3Ck-2Ck-1]And the input parallel data width n is not more than the CRC width k, and the device for realizing parallel CRC calculation comprises:
a configuration module for obtaining the highest power k of the generator polynomial and the input parallel data width n, and obtaining the permutation e of all powers except 0 and k in the generator polynomial from small to large0<e1<e2<…<em-2<em-1And a number m;
the first intermediate result generation module is used for intercepting the high n bits of the CRC initial value C and carrying out XOR operation with the input parallel data D to generate a first intermediate result X;
a second intermediate result generation module for performing a feedback XOR operation with the first intermediate result X to generate a second intermediate result Y, Y [ i [ ]]＝X[i]⊕Y[i+k-e0]⊕Y[i+k-e1]⊕…⊕Y[i+k-em-1]，i＝{0,1,2,…,n-2,n-1}；
A result output module for performing XOR operation between bits in the second intermediate result Y to obtain a final CRC calculation result Z, Z [ i [ ]]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]I ═ 0,1,2, …, n-2, n-1 }; performing XOR operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, Z [ i]＝C[i-n]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{n,n+1,…,k-2,k-1}。
Further, the second intermediate result generation module further performs the following operations:
judging the expression i + k-e0，i+k-e1…i+k-em-1And whether the calculation result exceeds the range from 0 to n-1, and if so, the Y of the corresponding bit is assigned to be 0.
Further, the result output module further performs the following operations:
judging whether n is equal to k, if yes, carrying out XOR operation between internal bits of the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i ]]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]And i is {0,1,2, …, n-2, n-1}, and the CRC calculation is finished.
Further, the result output module further performs the following operations:
judging the expression i-e0，i-e1…i-em-1And whether the calculation result exceeds the range from 0 to n-1, and if so, the Y of the corresponding bit is assigned to be 0.
The method and the device for realizing the parallel CRC calculation adopt a parameterization method, realize the change of the width of parallel input data and the generation of a polynomial according to needs, thereby improving the universality and the portability of the parallel CRC calculation method, and the parallel CRC calculation adopts the XOR operation, thereby avoiding the matrix high power solution in the traditional parallel CRC calculation method, being easy for hardware realization and reducing the difficulty of the hardware design of the parallel CRC calculation.
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FIG. 1 is a flow chart of a method for implementing parallel CRC calculation according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an apparatus for implementing parallel CRC calculation according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the drawings and examples, which should not be construed as limiting the present invention.
As shown in fig. 1, an implementation method of parallel CRC calculation includes:
s101, acquiring the highest power k of a generator polynomial and the width n of input parallel data, and acquiring the arrangement e of all powers except 0 and k in the generator polynomial from small to large0<e1<e2<…<em-2<em-1And a number m.
In this embodiment, the input parallel data D ═ D0D1…Dn-3Dn-2Dn-1]N is the input parallel data width, and the CRC initial value C ═ C0C1…Ck-3Ck-2Ck-1]K is the CRC width, i.e. the highest power k of the generator polynomial, and the input parallel data width n is not greater than the CRC width k.
S102, intercepting high n bits of a CRC initial value C, and carrying out XOR operation with input parallel data D to generate a first intermediate result X.
In this embodiment, an exclusive or operation is performed on the input parallel data D to generate a first intermediate result X, and a calculation formula is: x ═ D ≦ C.
Specifically, the method comprises the following steps:
X[n-1]＝D[n-1]⊕C[k-1]；
X[n-2]＝D[n-2]⊕C[k-2]；
…；
X[1]＝D[1]⊕C[k-n+1]；
X[0]＝D[0]⊕C[k-n]。
s103, performing feedback XOR operation by using the first intermediate result X to generate a second intermediate result Y, Y [ i [ I ] ]]＝X[i]⊕Y[i+k-e0]⊕Y[i+k-e1]⊕…⊕Y[i+k-em-1]，i＝{0,1,2,…,n-2,n-1}。
Specifically, the method comprises the following steps:
Y[n-1]＝X[n-1]⊕Y[n-1+k-e0]⊕Y[n-1+k-e1]⊕…⊕Y[n-1+k-em-1]if n-1+ k-e0，n-1+k-e1When the calculation result exceeds the range of 0 to n-1, Y [ n-1+ k-e ]0]，Y[n-1+k-e1]The value is equal to 0;
Y[n-2]＝X[n-2]⊕Y[n-2+k-e0]⊕Y[n-2+k-e1]⊕…⊕Y[n-2+k-em-1]if n-2+ k-e0，n-2+k-e1When the calculation result exceeds the range of 0 to n-1, Y [ n-2+ k-e ]0]，Y[n-2+k-e1]The value is equal to 0;
…；
Y[1]＝X[1]⊕Y[1+k-e0]⊕Y[1+k-e1]⊕…⊕Y[1+k-em-1]if 1+ k-e0，1+k-e1When the calculation result exceeds the range of 0 to n-1, Y [1+ k-e ]0]，Y[1+k-e1]The value is equal to 0;
Y[0]＝X[0]⊕Y[k-e0]⊕Y[k-e1]⊕…⊕Y[k-em-1]if k-e0，k-e1When the calculated result exceeds the range of 0 to n-1, Y [ k-e ] is determined0]，Y[k-e1]The value is equal to 0;
s104, carrying out XOR operation between the bits in the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i ]]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{0,1,2,…,n-2,n-1}。
Specifically, the method comprises the following steps:
Z[n-1]＝Y[n-1]⊕Y[n-1-e0]⊕Y[n-1-e1]⊕…⊕Y[n-1-em-1]if n-1-e0，n-1-e1When the calculation result exceeds the range of 0 to n-1, thenReacting Y [ n-1-e0]，Y[n-1-e1]The value is equal to 0;
Z[n-2]＝Y[n-2]⊕Y[n-2-e0]⊕Y[n-2-e1]⊕…⊕Y[n-2-em-1]if n-2-e0，n-2-e1When the calculated result exceeds the range of 0 to n-1, Y [ n-2-e ] is determined0]，Y[n-2-e1]The value is equal to 0;
…；
Z[1]＝Y[1]⊕Y[1-e0]⊕Y[1-e1]⊕…⊕Y[1-em-1]if 1-e0，1-e1When the calculated result exceeds the range of 0 to n-1, Y1-e is determined0]，Y[1-e1]The value is equal to 0;
Z[0]＝Y[0]⊕Y[-e0]⊕Y[-e1]⊕…⊕Y[-em-1]is prepared from Y [ -e [ ]0]，Y[-e1]The value is equal to 0;
s105, carrying out XOR operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, Z [ i [ ] I [ ]]＝C[i-n]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{n,n+1,…,k-2,k-1}。
Specifically, the method comprises the following steps:
Z[k-1]＝C[k-1-n]⊕Y[k-1-e0]⊕Y[k-1-e1]⊕…⊕Y[k-1-em-1]if k-1-e0，k-1-e1When the calculated result exceeds the range of 0 to n-1, Y [ k-1-e ] is determined0]，Y[k-1-e1]The value is equal to 0;
Z[k-2]＝C[k-2-n]⊕Y[k-2-e0]⊕Y[k-2-e1]⊕…⊕Y[k-2-em-1]if k-2-e0，k-2-e1When the calculated result exceeds the range of 0 to n-1, Y [ k-2-e ] is determined0]，Y[k-2-e1]The value is equal to 0;
…；
Z[n+1]＝C[1]⊕Y[n+1-e0]⊕Y[n+1-e1]⊕…⊕Y[n+1-em-1]if n +1-e0，n+1-e1When the calculation result exceeds the range of 0 to n-1, Y [ n +1-e ]0]，Y[n+1-e1]The value is equal to 0;
Z[n]＝C[0]⊕Y[n-e0]⊕Y[n-e1]⊕…⊕Y[n-em-1]if n-e0，n-e1When the calculated result exceeds the range of 0 to n-1, Y [ n-e ]0]，Y[n-e1]Etc. are assigned a value of 0.
In another embodiment of the present invention, the step S104 further includes:
and judging whether n is equal to k, if so, skipping the technology of the step S105, otherwise, executing the step S105.
I.e. in case n is equal to k, all CRC values have been calculated in step S104, without the need to continue the calculation in step S105.
It should be noted that the present invention also judges the expression i + k-e0，i+k-e1If the calculation result exceeds the range from 0 to n-1, assigning the Y of the corresponding bit as 0; and, judging the expression i-e0，i-e1And if the calculation result exceeds the range from 0 to n-1, assigning the Y of the corresponding bit as 0.
In addition to the above embodiments, the implementation method of the parallel CRC calculation is examined by taking, as an example, one parallel input data 110011 having a bit width of 6, and it is assumed that the corresponding generator polynomial is Poly ═ X8+X2+ X +1, CRC initial value 11000101.
First, the highest power k of the generator polynomial is 8, the width n of the parallel input data is 6, and the sequence e of all powers except 0 and 8 in the generator polynomial is obtained from the lowest power to the highest power0＝1<e12 and m 2;
cutting high-order 6 bits of a CRC initial value to be C ═ 000101, and carrying out exclusive-or operation on the C ═ 000101 and input parallel data D ═ 110011 to generate a first intermediate result X ═ D ═ C ═ 110011 ^ 000101 ═ 110110;
and performing a feedback exclusive-or operation using the first intermediate result X to generate a second intermediate result Y, where Y [ i ] ═ X [ i ], [ Y [ i +7], [ Y [ i +6], [ i ], [ 0,1,2,3,4,5 ].
Specifically, the method comprises the following steps:
Y[5]＝X[5]⊕Y[12]⊕Y[11]＝0⊕0⊕0＝0；
Y[4]＝X[4]⊕Y[11]⊕Y[10]＝1⊕0⊕0＝1；
Y[3]＝X[3]⊕Y[10]⊕Y[9]＝1⊕0⊕0＝1；
Y[2]＝X[2]⊕Y[9]⊕Y[8]＝0⊕0⊕0＝0；
Y[1]＝X[1]⊕Y[8]⊕Y[7]＝1⊕0⊕0＝1；
Y[0]＝X[0]⊕Y[7]⊕Y[6]＝1⊕0⊕0＝1；
performing exclusive-or operation between bits in the second intermediate result Y to obtain a CRC final calculation result Z, where Z [ i ] ═ Y [ i ], [ Y [ i-1], [ Y [ i-2], i ═ 0,1,2,3,4,5 };
specifically, the method comprises the following steps:
Z[5]＝Y[5]⊕Y[4]⊕Y[3]＝0⊕1⊕1＝0；
Z[4]＝Y[4]⊕Y[3]⊕Y[2]＝1⊕1⊕0＝0；
Z[3]＝Y[3]⊕Y[2]⊕Y[1]＝1⊕0⊕1＝0；
Z[2]＝Y[2]⊕Y[1]⊕Y[0]＝0⊕1⊕1＝0；
Z[1]＝Y[1]⊕Y[0]⊕Y[-1]＝1⊕1⊕0＝0；
Z[0]＝Y[0]⊕Y[-1]⊕Y[-2]＝1⊕0⊕0＝1；
and performing exclusive-or operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, where Z [ i ] ≦ C [ i-6] ≦ Y [ i-1] ≦ Y [ i-2], and i ≦ 6, 7.
Specifically, the method comprises the following steps:
Z[7]＝C[1]⊕Y[6]⊕Y[5]＝1⊕0⊕0＝1；
Z[6]＝C[0]⊕Y[5]⊕Y[4]＝1⊕0⊕1＝0；
the input data is 110011, the generator polynomial is X8+ X2+ X +1, the CRC initial value is 11000101, and the CRC parallel calculation result is 10000001.
Correspondingly, a device for realizing parallel CRC calculation is also provided, as shown in FIG. 2, the input parallel data D ═ D0D1…Dn-3Dn-2Dn-1]CRC initial value C ═ C0C1…Ck-3Ck-2Ck-1]And the input data width is not more than the CRC width, and the device for realizing parallel CRC calculation comprises:
a configuration module 100 for obtaining a generator polynomialThe highest power k and the parallel data width n of the polynomial are obtained, and the arrangement e of all powers except 0 and the k power from small to large in the generator polynomial is obtained0<e1<e2<…<em-2<em-1And a number m;
a first intermediate result generating module 200, configured to intercept the high n bits of the CRC initial value C, and perform an exclusive or operation with the input parallel data D to generate a first intermediate result X, where X is D ≦ C;
a second intermediate result generating module 300, configured to perform a feedback xor operation on the first intermediate result X to generate a second intermediate result Y, Y [ i [ ] i]＝X[i]⊕Y[i+k-e0]⊕Y[i+k-e1]⊕…⊕Y[i+k-em-1]，i＝{0,1,2,…,n-2,n-1}；
A result output module 400, configured to perform an exclusive-or operation between the bits in the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i [ ] i]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]I ═ 0,1,2, …, n-2, n-1 }; performing XOR operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, Z [ i]＝C[i-n]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{n,n+1,…,k-2,k-1}。
It should be noted that, in the second intermediate result generation module 300, if i + k-e0，i+k-e1When the value exceeds the range of 0 to n-1, Y [ i + k-e ] is added0]，Y[i+k-e1]Etc. are assigned a value of 0. In the result output module 400, if i-e0，i-e1When the value is out of the range of 0 to n-1, Y [ i-e ] is set0]，Y[i-e1]Etc. are assigned a value of 0.
The result output module of this embodiment further performs the following operations:
judging whether n is equal to k, if yes, carrying out XOR operation between internal bits of the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i ]]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]And i is {0,1,2, …, n-2, n-1}, and the CRC calculation is finished.
In conclusion, the method adopts a parameterization method, the width of parallel input data and a generating polynomial are changed according to needs, so that the universality and the portability of the parallel CRC calculation method are improved, the exclusive OR operation is adopted in the parallel CRC calculation, the matrix high power solving in the traditional parallel CRC calculation method is avoided, the hardware implementation is easy, and the difficulty of the hardware design of the parallel CRC calculation is reduced.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, but these corresponding changes and modifications should fall within the protection scope of the appended claims.
Claims (4)
1. A method for realizing parallel CRC calculation includes inputting parallel data D ═ D0 D1…Dn-3Dn-2 Dn-1]CRC initial value C ═ C0 C1…Ck-3 Ck-2 Ck-1]And the input parallel data width n is not more than the CRC width k, and the implementation method of the parallel CRC calculation comprises the following steps:
step 1, obtaining the highest power k of a generator polynomial and the width n of input parallel data, and obtaining the arrangement e of all powers except 0 and k in the generator polynomial from small to large0<e1<e2<…<em-2<em-1And a number m;
step 2, intercepting high n bits of a CRC initial value C, and carrying out XOR operation with input parallel data D to generate a first intermediate result X;
step 3, utilizing the first intermediate result X to perform feedback XOR operation to generate a second intermediate result Y, Y [ i ]]＝X[i]⊕Y[i+k-e0]⊕Y[i+k-e1]⊕…⊕Y[i+k-em-1]，i＝{0,1,2,…,n-2,n-1}；
Step 4, carrying out XOR operation between the internal bits of the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{0,1,2,…,n-2,n-1}；
Step 5, carrying out XOR operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, Z [ i [ ] I [ ]]＝C[i-n]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{n,n+1,…,k-2,k-1}；
Wherein, the step 3 further comprises:
judging the expression i + k-e0，i+k-e1…i+k-em-1Whether the calculation result exceeds the range from 0 to n-1 or not, and if so, assigning the Y of the corresponding bit as 0;
the steps 4 and 5 further comprise:
judging the expression i-e0，i-e1…i-em-1And whether the calculation result exceeds the range from 0 to n-1, and if so, the Y of the corresponding bit is assigned to be 0.
2. The method of claim 1, wherein after step 4, further comprising:
and judging whether n is equal to k, if so, skipping the step 5 and finishing the CRC calculation.
3. An apparatus for implementing parallel CRC calculation is disclosed, wherein the input parallel data D ═ D0 D1…Dn-3Dn-2 Dn-1]CRC initial value C ═ C0 C1…Ck-3 Ck-2 Ck-1]And the input parallel data width n is not more than the CRC width k, and the device for realizing parallel CRC calculation comprises:
a configuration module for obtaining the highest power k of the generator polynomial and the input parallel data width n, and obtaining the permutation e of all powers except 0 and k in the generator polynomial from small to large0<e1<e2<…<em-2<em-1And a number m;
the first intermediate result generation module is used for intercepting the high n bits of the CRC initial value C and carrying out XOR operation with the input parallel data D to generate a first intermediate result X;
a second intermediate result generation module for performing a feedback XOR operation with the first intermediate result X to generate a second intermediate result Y, Y [ i [ ]]＝X[i]⊕Y[i+k-e0]⊕Y[i+k-e1]⊕…⊕Y[i+k-em-1]，i＝{0,1,2,…,n-2,n-1}；
A result output module for performing XOR operation between bits in the second intermediate result Y to obtain a final CRC calculation result Z, Z [ i [ ]]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]I ═ 0,1,2, …, n-2, n-1 }; performing XOR operation between the second intermediate result Y and the CRC initial value C to obtain a CRC final calculation result Z, Z [ i]＝C[i-n]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]，i＝{n,n+1,…,k-2,k-1}；
Wherein the second intermediate result generating module further performs the following operations:
judging the expression i + k-e0，i+k-e1…i+k-em-1Whether the calculation result exceeds the range from 0 to n-1 or not, and if so, assigning the Y of the corresponding bit as 0;
the result output module also executes the following operations:
judging the expression i-e0，i-e1…i-em-1And whether the calculation result exceeds the range from 0 to n-1, and if so, the Y of the corresponding bit is assigned to be 0.
4. An apparatus for implementing parallel CRC computations as in claim 3, wherein said result output module further performs the following operations:
judging whether n is equal to k, if yes, carrying out XOR operation between internal bits of the second intermediate result Y to obtain a CRC final calculation result Z, Z [ i ]]＝Y[i]⊕Y[i-e0]⊕Y[i-e1]⊕…⊕Y[i-em-1]And i is {0,1,2, …, n-2, n-1}, and the CRC calculation is finished.
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