CN109860153B - Integrated circuit device, method for forming alignment measurement pattern and photomask - Google Patents
Integrated circuit device, method for forming alignment measurement pattern and photomask Download PDFInfo
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- CN109860153B CN109860153B CN201910251212.XA CN201910251212A CN109860153B CN 109860153 B CN109860153 B CN 109860153B CN 201910251212 A CN201910251212 A CN 201910251212A CN 109860153 B CN109860153 B CN 109860153B
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Abstract
The invention relates to an integrated circuit device, a method for forming an alignment measurement pattern, and a photomask. The integrated circuit device comprises a plurality of semiconductor layers, at least one semiconductor layer of the plurality of semiconductor layers is provided with an alignment measurement pattern, the alignment measurement pattern comprises a plurality of groups of marks, each group of marks comprises convex strips and grooves which are alternately arranged, and each group of marks is provided with a groove at the outermost side perpendicular to the extending direction of the marks.
Description
Technical Field
The present invention relates to an integrated circuit device, and more particularly, to an integrated circuit device having an alignment measurement pattern, a method of forming the alignment measurement pattern, and a photomask.
Background
Semiconductor integrated circuits have since their birth, undergone a phase of development from small-scale, medium-scale to large-scale and very large-scale integration, and are increasingly becoming one of the most active technical fields in modern scientific technology.
The photoetching process utilizes the characteristic that the photoresist has corrosion resistance after photochemical reaction, and can etch the photoetching pattern on the photomask to the surface of an integrated circuit device.
With the progress of semiconductor integrated circuit manufacturing processes, integrated circuit line widths become smaller and smaller, and the requirement for alignment accuracy in the photolithography process is higher and higher. In the fabrication of integrated circuit devices, Alignment systems of lithography machines are used to align the photomask to the integrated circuit device. Alignment is achieved by placing specific alignment measurement patterns on the photomask and the integrated circuit device, respectively. A common alignment measurement pattern, i.e., alignment marks (marks), also known as fiducial marks or indicators, is a visible pattern placed on the photomask and integrated circuit device to determine their relative positions and orientations. For example, they may be one or more line marks on a photomask or integrated circuit device. The alignment process of a photomask and an integrated circuit device is generally divided into two steps: first, coarse alignment (coarse alignment) and then fine alignment (fine alignment) are performed. Coarse alignment generally requires only two alignment marks, and fine alignment criteria requires the use of multiple alignment marks.
The quality of the alignment measurement pattern formed on the integrated circuit device directly affects the alignment accuracy. It is therefore desirable to continuously improve the quality of the alignment measurement pattern.
Disclosure of Invention
The invention aims to provide an integrated circuit device, which can improve the pattern contour quality of the outermost side of an alignment measurement pattern of the integrated circuit device.
The present invention provides an integrated circuit device including a plurality of semiconductor layers, at least one of the semiconductor layers having an alignment measurement pattern, the alignment measurement pattern including a plurality of sets of marks, each set of marks including alternately arranged ridges and grooves, and each set of marks having a groove at an outermost side perpendicular to an extending direction of the marks.
In an embodiment of the invention, the outermost groove includes a first sidewall and a second sidewall spaced and opposite to the first sidewall, and the first sidewall is an interface between the outermost groove and the convex strip located inside the outermost groove.
In an embodiment of the invention, a boss is located between two adjacent sets of marks, and the second sidewall is an interface between the outermost groove and the boss.
In one embodiment of the present invention, two adjacent sets of marks are parallel to each other.
In an embodiment of the invention, the width of the groove marked on the outermost side of each group is larger than the width of the convex strip adjacent to the groove.
Another aspect of the present invention provides a method of forming an alignment measurement pattern of an integrated circuit device, comprising the steps of: and forming a semiconductor layer, wherein the semiconductor layer is provided with an alignment measurement pattern, the alignment measurement pattern comprises a plurality of groups of marks, each group of marks comprises convex strips and grooves which are alternately arranged, and the outermost side of each group of marks, which is vertical to the extending direction of the marks, is provided with a groove.
In an embodiment of the invention, the outermost groove includes a first sidewall and a second sidewall spaced and opposite to the first sidewall, and the first sidewall is an interface between the outermost groove and the convex strip located inside the outermost groove.
In an embodiment of the invention, a boss is disposed between two adjacent sets of marks, and the second sidewall is an interface between the outermost groove and the protruding strip.
In one embodiment of the present invention, two adjacent sets of marks are parallel to each other.
In an embodiment of the invention, the width of the groove marked on the outermost side of each group is larger than the width of the convex strip adjacent to the groove.
Another aspect of the present invention provides a photomask for manufacturing an integrated circuit device, the photomask having a mask pattern for forming an alignment measurement pattern, the mask pattern including a plurality of sets of lines, each set of lines including a first type of line and a second type of line alternately arranged, and each set of lines having the second type of line at an outermost side perpendicular to an extending direction of the lines, wherein the first type of line is used for forming a convex line of the alignment measurement pattern, and the second type of line is used for forming a concave groove of the alignment measurement pattern.
In an embodiment of the present invention, a first type region is between two adjacent sets of lines, and the first type region is used for forming a boss of the alignment measurement pattern.
In an embodiment of the invention, two adjacent lines are parallel to each other.
In an embodiment of the invention, the width of the second type of lines at the outermost side of each group of lines is greater than the width of the first type of lines adjacent to the second type of lines.
The integrated circuit device provided by the invention can ensure that the pattern outline at the outermost side of the alignment measurement pattern of the area with the changed surface topography of the integrated circuit device is relatively smooth, and is beneficial to improving the alignment precision of the integrated circuit device.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 is a top view structural diagram of an integrated circuit device.
Fig. 2 is a schematic diagram of an alignment measurement pattern of the integrated circuit device shown in fig. 1.
Fig. 3A is a partially enlarged schematic view of the alignment measurement pattern in fig. 2.
Fig. 3B is a side view of the alignment measurement profile shown in fig. 3A.
Fig. 4 is an enlarged image of a portion B of the alignment mark in fig. 3A.
Fig. 5 is another imaged magnified view of portion B of the alignment mark in fig. 3A.
Fig. 6A is a partially enlarged schematic view of an alignment measurement pattern of an integrated circuit device according to an embodiment of the invention.
Fig. 6B is a side view of an alignment measurement pattern of an integrated circuit device in accordance with an embodiment of the present invention.
FIG. 7 is a partial imaged magnified view of an alignment measurement profile according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating a photomask pattern of an integrated circuit device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
In the photolithography process of integrated circuit devices, it is necessary to set specific alignment measurement patterns on the photomask (mask) and the integrated circuit device to achieve alignment therebetween.
Semiconductor chips, which are widely used as integrated circuit devices, are fabricated layer by layer using a Wafer (Wafer) of silicon material as a substrate. Wafers are typically classified into 6 inch, 8 inch, and 12 inch specifications. The larger the wafer, the more chips can be produced on the same wafer, resulting in lower costs, but with higher requirements on materials and production techniques. And cutting the manufactured wafer into bare chips (Die). The bare Chip becomes a Chip (Chip) after the processes of testing, packaging and the like.
For example, in a 12-inch wafer process, in order to obtain a better alignment measurement pattern, a large (e.g., 1.2 μm) alignment measurement pattern is divided during design.
However, in the small line width process, the corresponding alignment measurement pattern needs to be divided into small line widths. This results in the outermost line widths of the segmented alignment measurement patterns being in a relatively sparse pattern environment. Thus, when the topography of some regions of the surface of the integrated circuit device changes, the pattern profile at the outermost side of the alignment measurement pattern in these regions becomes rough. In the contrast technique, the line width of the alignment measurement pattern after being divided is generally increased to reduce the sensitivity to focus and topography, thereby increasing the window (window) of the alignment measurement pattern. However, in the small line width process, the line width of the divided alignment measurement pattern may be too different from the main design pattern of the product, which may result in the risk of the pattern not being exposed easily or the profile being degraded.
Fig. 1 is a top view structural diagram of an integrated circuit device. In the integrated circuit device (wafer) 100 shown in fig. 1, alignment measurement patterns (e.g., the alignment measurement pattern 101 and the alignment measurement pattern 102) are often disposed on scribe lines 110 on the surface of the integrated circuit device (wafer) 100. Fig. 2 is a schematic diagram of an alignment measurement pattern (e.g., alignment measurement pattern 101 or alignment measurement pattern 102) of the integrated circuit device 100 shown in fig. 1. The alignment measurement pattern 200 in fig. 2 shows the alignment relationship between adjacent two layers of alignment measurement patterns. Wherein the alignment measurement pattern 210 of the black pattern is an alignment measurement pattern on a lower semiconductor layer, and the alignment measurement pattern 220 of the white pattern is an alignment measurement pattern on an upper semiconductor layer. Taking the alignment measurement pattern 210 as an example, it may include a plurality of sets of spaced-apart marks.
Fig. 3A is an enlarged schematic view of a portion a of two sets of marks in the alignment measurement pattern 210 of fig. 2. Fig. 3B is a side view of the alignment measurement profile 300 shown in fig. 3A. Corresponding to fig. 3A, fig. 3B only shows the distribution/arrangement of the ribs and grooves of the two sets of marks 310. Referring to fig. 3B, each set of marks (e.g., mark 310) includes alternating ridges (e.g., ridge 311) and grooves (e.g., groove 312). The outermost side of each set of marks (e.g., mark 310) is a rib (e.g., rib 311). Between two adjacent sets of marks 310 are grooves (e.g., grooves 313), which are collectively defined by the outer sidewalls of the ribs 311 of two adjacent sets of marks 310.
The outermost pattern profile of a normal alignment measurement pattern (e.g., alignment measurement pattern 101 of fig. 1) should be relatively smooth. Fig. 4 is an enlarged image of a portion B of the alignment mark in fig. 3A. As can be seen from fig. 4, the outline of the raised line 401 at the outermost (in the left-hand dashed box) mark of a normal alignment measurement pattern (e.g., the alignment measurement pattern 101 in fig. 1) is relatively smooth.
In the prior art, due to the existence of the effects of light diffraction and the like, in the area where the surface topography of the integrated circuit device changes, when an alignment measurement pattern is formed by using a photomask, the pattern profile at the outermost side of the alignment measurement pattern becomes rough, and further, the alignment accuracy of the integrated circuit device is influenced to a certain extent. Fig. 5 is another imaged magnified view of portion B of the alignment mark in fig. 3A. As can be seen from fig. 5, the pattern profile of a set of convex stripes 501 marked on the outermost side (in the left dotted box in the figure) of the alignment measurement pattern (e.g., alignment measurement pattern 102) in the area with the changed surface topography is rougher than the pattern profile of the convex stripes on the inner side. The smoothness or roughness of the pattern profile at the outermost side of the alignment measurement pattern directly affects the alignment accuracy of the integrated circuit device. The rough alignment measurement pattern profile may not allow integrated circuit devices to have high alignment accuracy.
The alignment measurement pattern has a problem that the profile of the outermost (raised line) pattern is relatively rough in the area where the surface topography of the integrated circuit device is changed, thereby reducing the alignment accuracy of the integrated circuit device. Therefore, there is a need for a method to solve the problem of the relatively rough pattern profile at the outermost side of the alignment measurement pattern in the area with the varied surface topography of the integrated circuit device.
Analysis of the above comparison technique shows that, because the outermost line widths of the alignment measurement patterns (as shown in fig. 3A) that are divided into small line widths are in a relatively sparse pattern environment, when the topography of some regions of the surface of the integrated circuit device changes, the outermost pattern profiles of the alignment measurement patterns in these regions become rough. Therefore, it would be desirable to provide an integrated circuit device such that the outermost line widths of the alignment measurement patterns are in a relatively dense pattern environment. Then, when the topography of some regions of the surface of the integrated circuit device changes, the pattern profile at the outermost side of the alignment measurement pattern in these regions becomes smoother.
Based on the above design concept, the following embodiments of the present invention provide an integrated circuit device, which can solve the problem that the outermost pattern profile of the alignment measurement pattern in the region where the surface topography of the integrated circuit device changes is relatively rough, and is helpful for improving the alignment accuracy of the integrated circuit device.
An embodiment of the invention provides an integrated circuit device. The integrated circuit device includes a plurality of semiconductor layers, at least one of which has an alignment measurement pattern.
Illustratively, these semiconductor layers may be silicon (Si) semiconductor layers, silicon germanium (Ge/Si) semiconductor layers, and semiconductor layers composed of other doped, mixed crystals, or combinations thereof. Alternatively, the semiconductor layer may be formed by an epitaxial growth process. For example, it can be achieved by depositing a thin monocrystalline layer on a monocrystalline substrate, but the invention is not limited thereto.
The alignment measurement pattern may be a line-shaped mark or other shape mark or pattern.A common alignment measurement pattern, such as an alignment mark (OV L mark), may include multiple sets of line-shaped marks (marks). FIG. 6A is a partially enlarged schematic view of an alignment measurement pattern for an integrated circuit device according to an embodiment of the invention.FIG. 6B is a side view of an alignment measurement pattern for an integrated circuit device according to an embodiment of the invention.in the alignment measurement pattern 600 of an integrated circuit device shown in FIGS. 6A and 6B, the alignment measurement pattern 600 is a line-shaped mark.
An alignment measurement pattern of an integrated circuit device according to an embodiment of the present invention is further described with reference to fig. 6A and 6B. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.
The alignment measurement pattern 600 of an integrated circuit device shown in fig. 6A and 6B is merely exemplary of two sets of marks. It is understood that the alignment measurement pattern 600 may extend to both sides in the distribution/arrangement shown in fig. 6A and 6B and include two or more sets of marks. Referring to fig. 6A and 6B, each set of marks (e.g., 610) includes alternatively arranged ribs (e.g., ribs 611) and grooves (e.g., grooves 612), and each set of marks (e.g., 610) has grooves (e.g., grooves 612) at the outermost side perpendicular to the extending direction of the marks. As shown in fig. 6B, each set of indicia 610 may have grooves 612 on both sides.
In an embodiment of the present invention, the outermost recess (e.g., recess 612) of the alignment measurement pattern (e.g., alignment measurement pattern 600) of the integrated circuit device includes a first sidewall (e.g., first sidewall 612a) and a second sidewall (e.g., second sidewall 612b) spaced apart from and opposite to the first sidewall (e.g., first sidewall 612 a). First sidewall (e.g., first sidewall 612a) is the interface between the outermost groove (e.g., groove 612) and the rib (e.g., rib 611) located inside the outermost groove (e.g., groove 612).
In an embodiment of the invention, between two adjacent sets of marks of the alignment measurement pattern (e.g., alignment measurement pattern 600) of the integrated circuit device, there may be a mesa (e.g., mesa 613). The second sidewall (e.g., second sidewall 612b) is the interface between the outermost recess (e.g., recess 612) and the boss (e.g., boss 613). It is understood, however, that in some examples, one or more grooves or other patterns (not shown) may be present in the middle portion of the above-described boss (e.g., boss 613).
In an embodiment of the invention, two adjacent sets of marks of the alignment measurement pattern of the integrated circuit device may be parallel to each other. For example, the two sets of indicia 610 shown in FIG. 6B are parallel to each other. In some embodiments of the present invention, the width of each outermost set of grooves (e.g., groove 612) may be greater than the width of the ribs (e.g., rib 611) adjacent to that groove (e.g., groove 612). In other embodiments of the invention, the width of the outermost groove may be equal to the width of the rib adjacent to the groove. In any event, the width of the outermost groove should be less than a threshold value to ensure that the ridges adjacent to the groove (i.e., the outermost line width of the alignment measurement pattern) are in a relatively dense (rather than relatively sparse) pattern environment.
It should be understood that in the present invention, length is defined as the direction in which the indicia extend. Correspondingly, the width is defined as the direction perpendicular to the extension of the mark, i.e. the direction in which the ridges and grooves in the alignment measurement pattern are arranged. For example, for alignment measurement pattern 600 shown in FIG. 6B, groove 612 is located outermost of one of the sets of marks, and the width of groove 612 is greater than the width of rib 611 adjacent to groove 612.
The pattern of the alignment measurement pattern is changed, and the groove is arranged outside the convex strip on the outermost side of the alignment measurement pattern, so that the convex strip on the outermost side is in a relatively dense pattern environment. Therefore, the pattern profile at the outermost side of the alignment measurement pattern in these regions becomes smoother, so that the window of the alignment measurement pattern can be increased. FIG. 7 is a partial imaged magnified view of an alignment measurement profile according to an embodiment of the present invention. Fig. 7 is an enlarged image of a portion C of the alignment measurement profile 600 shown in fig. 6A. Referring to fig. 7, it can be seen that the partial C of the alignment measurement pattern 600 is enlarged to have a smoother pattern profile of the outermost ribs 701 compared to the pattern profile of the outermost ribs 401 of the prior art alignment measurement pattern shown in fig. 5.
The above embodiments of the present invention describe an integrated circuit device that can solve the problem that the outermost pattern profile of the alignment measurement pattern in the region where the surface topography of the integrated circuit device changes is relatively rough, thereby effectively improving the alignment accuracy of the integrated circuit device.
Another aspect of the present invention is directed to a photomask for manufacturing an integrated circuit device, the photomask having a mask pattern for forming an alignment measurement pattern. The mask pattern comprises a plurality of groups of lines, each group of lines comprises first type lines and second type lines which are alternately arranged, and the second type lines are arranged on the outermost side of each group of lines in the direction perpendicular to the extending direction of the lines. The first type of lines are used for forming convex strips aligned with the measurement pattern, and the second type of lines are used for forming grooves aligned with the measurement pattern.
In an embodiment of the present invention, the alignment measurement pattern 600 shown in fig. 6B may be formed by the photomask pattern 800 shown in fig. 8. The photomask pattern 800 in fig. 8 only illustratively shows a set of lines corresponding to the set of marks in fig. 6B (right). The raised bars (e.g., raised bars 611) of the alignment measurement pattern 600 correspond to the first-type lines (e.g., first-type lines 811) of the mask pattern 800 of the photomask, and the recessed bars (e.g., recessed bars 612) of the alignment measurement pattern 600 correspond to the second-type lines (e.g., second-type lines 812) of the mask pattern 800 of the photomask. In the photomask pattern 800, the outermost side perpendicular to the line extending direction is a second-type line (e.g., a second-type line 812) for forming a groove (e.g., a groove 612) at the outermost side of the alignment measurement pattern 600.
In an embodiment of the present invention, a first type region is located between two adjacent sets of lines of the mask pattern 800 of the photomask, and the first type region is used to form a mesa (e.g., the mesa 613) of the alignment measurement pattern 600. In one example, the first-type regions (e.g., the first-type region 812a and the first-type region 812B) of the photomask pattern 800 correspond to the first sidewall (e.g., the first sidewall 612a) or the second sidewall (e.g., the second sidewall 612B) of the alignment measurement pattern 600 shown in fig. 6B. The first type region may form a mesa (e.g., mesa 613) on alignment measurement pattern 600.
In an embodiment of the present invention, two adjacent lines of the mask pattern 800 of the photomask are parallel to each other. In one example, two adjacent sets of marks of the alignment measurement pattern 600 in FIG. 6B formed by the photomask pattern 800 shown in FIG. 8 are parallel to each other.
In an embodiment of the present invention, each set of lines of the mask pattern 800 of the photomask has a width of the second-type line at the outermost side that is greater than a width of the first-type line adjacent to the second-type line. In one example, the outermost recesses (e.g., recess 612) of alignment measurement pattern 600 shown in FIG. 6B are formed by the outermost second-type lines (e.g., second-type lines 812) of photomask pattern 800 in FIG. 8. The raised bars 611 adjacent to the grooves 612 correspond to the first-type lines 811 on the photomask pattern 800 adjacent to the second-type lines 812. The width of the second-type lines (e.g., the second-type lines 812) at the outermost side due to each set of lines on the photomask pattern 800 is greater than the width of the first-type lines (e.g., the first-type lines 811) adjacent to the second-type lines (e.g., the second-type lines 812). In the alignment measurement pattern 600 formed using the photomask pattern 800, the width of the groove 612 is also correspondingly greater than the width of the convex stripe 611.
The above embodiments of the present invention describe a photomask for manufacturing an integrated circuit device, which can solve the problem that the outermost pattern profile of an alignment measurement pattern of an area where the surface topography of the integrated circuit device changes is relatively rough, thereby effectively improving the alignment accuracy of the integrated circuit device.
Another aspect of the invention is directed to a method of forming an alignment measurement pattern for an integrated circuit device. The method includes forming a semiconductor layer on a wafer using a photomask such as that shown in fig. 8. A plurality of semiconductor layers are formed in an integrated circuit device. Illustratively, these semiconductor layers may be silicon (Si) semiconductor layers, silicon germanium (Ge/Si) semiconductor layers, and semiconductor layers composed of other doped, mixed crystals, or combinations thereof. Alternatively, the semiconductor layer may be formed by an epitaxial growth process. For example, it can be achieved by depositing a thin monocrystalline layer on a monocrystalline substrate, but the invention is not limited thereto.
The semiconductor layer has an alignment measurement pattern. Specifically, the integrated circuit device may have one semiconductor layer having the alignment measurement pattern, or may have a plurality of semiconductor layers each having the alignment measurement pattern. For example, specific alignment measurement patterns are provided on the photomask and the integrated circuit device, respectively, to achieve alignment of the two. The alignment measurement pattern may be a line-shaped mark or other shaped marks and patterns. In the alignment measurement pattern 600 of an integrated circuit device as shown in fig. 6A and 6B, the alignment measurement pattern 600 is a line mark. It is to be understood, however, that in other embodiments of the present invention, alignment measurement patterns of non-linear marks remain an alternative implementation.
For example, the alignment measurement pattern 600 of an integrated circuit device shown in FIG. 6B is merely illustrative of two sets of marks, it being understood that the alignment measurement pattern 600 may extend to either side in the distribution/arrangement shown in FIG. 6B and may include two or more sets of marks.
Each set of marks may include alternating ridges and grooves. For example, the alignment measurement pattern 600 shown in FIG. 6B may include a plurality of sets of marks, each set of marks including alternating ridges and grooves. Each group of marks is provided with a groove at the outermost side perpendicular to the extending direction of the marks. Referring to fig. 6B, each set of marks of the alignment measurement pattern 600 has a groove (e.g., groove 612) at the outermost side perpendicular to the extending direction of the marks.
In an embodiment of the present invention, in the method for forming an alignment measurement pattern of an integrated circuit device, the outermost recess (e.g., the recess 612) of the alignment measurement pattern (e.g., the alignment measurement pattern 600) includes a first sidewall (e.g., the first sidewall 612a) and a second sidewall (e.g., the second sidewall 612b) spaced apart from and opposite to the first sidewall (e.g., the first sidewall 612 a). First sidewall (e.g., first sidewall 612a) is the interface between the outermost groove (e.g., groove 612) and the rib (e.g., rib 611) located inside the outermost groove (e.g., groove 612).
In an embodiment of the present invention, in the method for forming an alignment measurement pattern of an integrated circuit device, a mesa (e.g., mesa 613) is located between two adjacent sets of marks of the alignment measurement pattern (e.g., alignment measurement pattern 600). The second sidewall (e.g., second sidewall 612b) is the interface between the outermost recess (e.g., recess 612) and the boss (e.g., boss 613). In some examples of the invention, there may be a groove (not shown) in the middle portion of a boss (e.g., boss 613).
In an embodiment of the invention, two adjacent sets of marks of the alignment measurement pattern of the integrated circuit device may be parallel to each other. For example, the two sets of marks shown in FIG. 6B are parallel to each other. In some embodiments of the invention, the width of the groove marked on the outermost side of each group is greater than the width of the rib adjacent to the groove. It should be understood that in the present invention, length is defined as the direction in which the indicia extend. Correspondingly, the width is defined as the direction perpendicular to the extension of the mark, i.e. the direction in which the ridges and grooves in the alignment measurement pattern are arranged. For example, for alignment measurement pattern 600 shown in FIG. 6B, groove 612 is located outermost of one of the sets of marks, and the width of groove 612 is greater than the width of rib 611 adjacent to groove 612.
The above embodiments of the present invention describe a method of forming an alignment measurement pattern of an integrated circuit device, which can solve the problem that the outermost pattern profile of an alignment measurement pattern of an area where the surface topography of the integrated circuit device changes is relatively rough, thereby effectively improving the alignment accuracy of the integrated circuit device.
This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (9)
1. An integrated circuit device comprises a plurality of semiconductor layers, at least one semiconductor layer of the plurality of semiconductor layers is provided with an alignment measurement pattern, the alignment measurement pattern comprises a plurality of groups of marks, each group of marks comprises convex strips and grooves which are alternately arranged, the convex strips of each group of marks are the same in width, and the outermost side of each group of marks, which is perpendicular to the extending direction of the marks, is provided with the groove; the groove on the outermost side comprises a first side wall and a second side wall opposite to the first side wall at a spacing, and the first side wall is an interface between the groove on the outermost side and the raised line positioned on the inner side of the groove on the outermost side; and the width of the groove of each group of marks on the outermost side is greater than the width of the convex strip adjacent to the groove on the outermost side.
2. The integrated circuit device of claim 1, wherein between adjacent sets of marks is a land, and the second sidewall is an interface between the outermost recess and the land.
3. The integrated circuit device of claim 1, wherein adjacent sets of marks are parallel to each other.
4. A method of forming an alignment measurement pattern for an integrated circuit device, comprising the steps of:
forming a semiconductor layer, wherein the semiconductor layer is provided with an alignment measurement pattern, the alignment measurement pattern comprises a plurality of groups of marks, each group of marks comprises convex strips and grooves which are alternately arranged, the convex strips of each group of marks have the same width, and the outermost side of each group of marks, which is vertical to the extending direction of the marks, is provided with the groove; the groove on the outermost side comprises a first side wall and a second side wall opposite to the first side wall at a spacing, and the first side wall is an interface between the groove on the outermost side and the raised line positioned on the inner side of the groove on the outermost side; and the width of the groove of each group of marks on the outermost side is greater than the width of the convex strip adjacent to the groove on the outermost side.
5. The method of claim 4, wherein a land is located between two adjacent sets of indicia, and the second sidewall is an interface between the outermost groove and the rib.
6. The method of claim 4, wherein adjacent sets of marks are parallel to each other.
7. A photomask for manufacturing an integrated circuit device is provided with a mask pattern used for forming an alignment measurement pattern, wherein the mask pattern comprises a plurality of groups of lines, each group of lines comprises a first type of lines and a second type of lines which are alternately arranged, the first type of lines of each group of lines have the same width, and the second type of lines of each group of lines are arranged on the outermost side perpendicular to the extension direction of the lines, wherein the first type of lines are used for forming convex strips of the alignment measurement pattern, and the second type of lines are used for forming grooves of the alignment measurement pattern; and the width of the second-type lines of each group of lines on the outermost side is greater than that of the first-type lines adjacent to the second-type lines on the outermost side.
8. The photomask of claim 7, wherein a first type region is between two adjacent sets of lines, the first type region being used to form a land of the alignment measurement pattern.
9. The photomask of claim 7 wherein adjacent sets of lines are parallel to each other.
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| CN106959587A (en) * | 2016-01-11 | 2017-07-18 | 中芯国际集成电路制造(上海)有限公司 | Alignment measurement markers, alignment measuring method and measurement apparatus based on diffraction |
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| US6141107A (en) * | 1991-02-28 | 2000-10-31 | Nikon Corporation | Apparatus for detecting a position of an optical mark |
| JP3371852B2 (en) * | 1999-07-09 | 2003-01-27 | 日本電気株式会社 | Reticle |
| KR100500469B1 (en) * | 2001-01-12 | 2005-07-12 | 삼성전자주식회사 | alignment mark, alignment system using ter same and alignment method thereof |
| US7863763B2 (en) * | 2005-11-22 | 2011-01-04 | Asml Netherlands B.V. | Binary sinusoidal sub-wavelength gratings as alignment marks |
| CN101369571B (en) * | 2007-08-17 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, wafer coarse alignment mark and coarse alignment method |
| CN102103336A (en) * | 2011-03-14 | 2011-06-22 | 张雯 | High-accuracy alignment mark structure based on machine vision alignment |
| CN105047647B (en) * | 2015-07-20 | 2018-10-26 | 上海华虹宏力半导体制造有限公司 | The production method of photoetching alignment mark in thick epitaxy technique |
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