CN109860097B - Silicon-on-insulator material and reinforcing method for resisting total dose radiation - Google Patents
Silicon-on-insulator material and reinforcing method for resisting total dose radiation Download PDFInfo
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Abstract
The invention discloses a silicon-on-insulator material and a total dose radiation resistant reinforcing method thereof, wherein the method comprises the following steps: preparing a first dielectric buried layer on a first semiconductor substrate, and preparing a second dielectric buried layer on a second semiconductor substrate; preparing a high-k dielectric layer on the first dielectric buried layer; and overlapping and connecting the high-k dielectric layer and the second dielectric buried layer to form a silicon-on-insulator material. The invention provides the silicon-on-insulator material and the reinforcing method thereof for resisting total dose radiation, which realize radiation reinforcement and simultaneously avoid the damage of the top semiconductor material.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a silicon-on-insulator material and a total dose radiation resistant reinforcing method thereof.
Background
Integrated circuits based on silicon-on-insulator (SOI) technology have the advantages of low power consumption, fast speed, high temperature resistance, latch-up resistance, etc., compared to bulk silicon integrated circuits, and thus are widely used. The advantages of SOI circuits derive from the unique structure of the buried insulating layer of SOI material that completely isolates the top-level device from the substrate. Particularly, the existence of the buried layer reduces the sensitive volume of the device in a single-particle radiation environment, obviously enhances the single-particle event upset (SEU) resistance of the circuit, and enables the SOI material to become a preferred material for manufacturing a high-reliability radiation hardening circuit. However, the presence of the buried layer makes the SOI circuit more sensitive to the total dose of radiation. Because in SOI field effect transistors (MOSFETs) the buried layer as the back gate introduces a parasitic back channel. Under the total dose radiation environment, when the net accumulation of trapped charges in a buried layer caused by radiation reaches a certain degree, a parasitic back channel is opened, so that the leakage current of an SOI circuit is increased, the power consumption is increased, and even the function is failed. Wherein the accumulation of net positive charge in the buried layer will cause the back channel of the n-channel MOSFET to open; the net negative charge accumulation of the buried layer will cause the back channel of the p-channel MOSFET to open. In addition, the Fully Depleted (FD) SOI circuit has more excellent electrical performance and superior anti-SEU capability relative to a Partially Depleted (PD) SOI process circuit. However, due to the presence of the electric coupling between the front and back gate transistors in the FD SOI MOSFET, the total dose radiation damage of the buried layer can have a significant impact on the electrical characteristics of the front gate transistor. Therefore, FD SOI MOSFETs are more sensitive to total dose radiation than PD SOI MOSFETs, and especially for small-sized FD SOI MOSFETs, a smaller threshold shift may lead to a significant degradation of the electrical performance of the device due to their relatively low threshold voltage. Therefore, radiation hardening of the SOI material used is necessary to improve the total dose radiation resistance of SOI devices and circuits.
Currently, the buried insulator layer of commercial SOI materials is a single silicon dioxide dielectric layer. Due to the fabrication process, the buried oxide layer typically contains a large number of hole traps, resulting in a higher density of net positive charge accumulation in the buried layer due to radiation. In order to suppress the net accumulation of trapped charges in the buried oxide layer under the radiation environment, the conventional method is to use an ion implantation process to implant a certain amount of impurity elements, such as Si, N, F, etc., into the buried layer to modify the material, and to introduce electron traps related to the impurity elements into the buried layer to counteract the effect of hole traps, so as to achieve the purpose of radiation-hardening the SOI material. The reinforcing mode takes doping modification of the material buried layer by means of an ion implantation process as a technical characteristic, and since the selected impurity elements are implanted into the buried layer for modification doping through the top silicon film of the SOI material, implantation damage is inevitably caused to the top silicon of the SOI material, and the electrical characteristics of SOI devices and circuits prepared in the top silicon are directly influenced. Especially for small-sized devices and high-density integrated circuit manufacturing, the preservation of the lattice integrity of the top silicon film is a prerequisite for ensuring the chip quality.
Therefore, for the total dose radiation hardening of SOI devices and circuits under advanced process nodes, it is necessary to find a method for radiation hardening of SOI materials without damage to the top silicon film, and research and improvement are urgently needed.
Disclosure of Invention
The invention provides the silicon-on-insulator material and the reinforcing method thereof for resisting total dose radiation, so that the radiation reinforcement is realized, and the damage of the top semiconductor silicon material is avoided.
In one aspect, the present application provides a method for total dose radiation hardening of a silicon-on-insulator (SOI) material, comprising:
preparing a first dielectric buried layer on a first semiconductor substrate, and preparing a second dielectric buried layer on a second semiconductor substrate;
preparing a high-k dielectric buried layer on the first dielectric buried layer or the second dielectric buried layer; high-k dielectric here means a dielectric material with a relative dielectric constant higher than twice that of silicon dioxide, i.e. an insulating dielectric material with a relative dielectric constant greater than 7.8;
and superposing and bonding the high-k dielectric layer and the second or first dielectric buried layer to form a silicon-on-insulator (SOI) material with a multi-dielectric-layer composite structure buried layer.
Optionally, the method further includes: testing to obtain a first relation between the thickness of the materials of the first dielectric buried layer and the second dielectric buried layer and the density and the radiation dose of trapped charges in the first dielectric buried layer and the second dielectric buried layer; testing to obtain a second relation between the thickness of the material of the high-k dielectric layer and the density of trapped charges in the high-k dielectric layer and the radiation dose; determining the thicknesses of the first dielectric buried layer, the second dielectric buried layer and the high-k dielectric layer according to the first relation and the second relation, and determining the material type of the high-k dielectric layer.
Optionally, the theoretical total trapped charge density values of the first dielectric buried layer, the second dielectric buried layer and the high-k dielectric layer under the preset working condition tend to 0.
Optionally, the high-k dielectric layer includes a high-k material having an initial negative charge.
Optionally, the high-k dielectric layer includes multiple high-k dielectric layers of different material types and/or different thicknesses.
Optionally, the overlapping and connecting the high-k dielectric layer and the second dielectric buried layer includes: and bonding and connecting the high-k dielectric layer and the second dielectric buried layer.
In another aspect, a silicon-on-insulator material is provided, including:
the first semiconductor layer, the first medium buried layer, the second medium buried layer and the second semiconductor layer are sequentially stacked;
and a high-k dielectric layer is embedded between the first dielectric buried layer and the second dielectric buried layer.
Optionally, the theoretical total trapped charge density values of the first dielectric buried layer, the second dielectric buried layer and the high-k dielectric layer under the preset working condition tend to 0.
Optionally, the high-k dielectric layer includes a high-k material having an initial negative charge.
Optionally, the high-k dielectric layer includes multiple high-k dielectric layers of different material types and/or different thicknesses.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:
according to the method and the material provided by the embodiment of the application, one or more layers of high dielectric constant (high-k) dielectric materials are embedded in the traditional SOI material buried oxide layers (the first dielectric buried layer and the second dielectric buried layer) to form the composite insulating dielectric buried layer with a laminated structure, and the net accumulation of trapped charges generated by total dose radiation in the SOI material buried layer is inhibited through the action of charge traps in the high-k dielectric materials, so that the technical effect of improving the total dose radiation resistance of the SOI material is realized.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a process diagram illustrating a method for total dose radiation hardening of a silicon-on-insulator material in accordance with an embodiment of the present invention;
FIG. 2 is a first schematic diagram of a silicon-on-insulator material in accordance with an embodiment of the present invention;
FIG. 3 is a second schematic diagram of a silicon-on-insulator material according to an embodiment of the present invention.
Detailed Description
The embodiment of the application provides the silicon-on-insulator material and the reinforcing method thereof for resisting total dose radiation, so that the radiation reinforcement is realized, the damage of the top semiconductor material is avoided, and the reliability of an SOI device is improved.
The technical scheme in the embodiment of the application has the following general idea:
the method comprises the steps of preparing a first medium buried layer on a first semiconductor substrate, preparing a second medium buried layer on a second semiconductor substrate, and preparing a high-k medium layer on the first medium buried layer, so that one or more layers of high-k medium materials are embedded in a traditional SOI material buried oxide layer (the first medium buried layer and the second medium buried layer), and the net accumulation of trapped charges generated due to total dose radiation in the SOI material buried layer is inhibited under the action of charge traps in the high-k medium materials, so that the technical effect of improving the total dose radiation resistance of a device prepared from the SOI material is realized.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
In this embodiment, a method for reinforcing a silicon-on-insulator material against total dose radiation is provided, as shown in fig. 1 to 3, including:
step S101, preparing a first dielectric buried layer 2 on a first semiconductor substrate 1, and preparing a second dielectric buried layer 4 on a second semiconductor substrate 3;
step S102, preparing a high-k dielectric layer 5 on the first dielectric buried layer 2;
and step S103, overlapping and connecting the high-k dielectric layer 5 and the second dielectric buried layer 4 to form a silicon-on-insulator material.
It should be noted that, the step S102 may be performed before the second buried dielectric layer 4 is formed on the second semiconductor substrate 3, or may be performed after or simultaneously with the second buried dielectric layer 4 is formed on the second semiconductor substrate 3, which is not limited herein.
The method for strengthening the silicon-on-insulator against total dose radiation provided by the present application is described in detail below with reference to fig. 1 to 3.
Step S101, a first dielectric buried layer 2 is prepared on a first semiconductor substrate 1, and a second dielectric buried layer 4 is prepared on a second semiconductor substrate 3.
In the embodiment of the present application, the materials of the first semiconductor substrate 1 and the second semiconductor substrate 3 may be the same or different, and may be silicon, germanium, a compound semiconductor, and the like, which is not limited herein. The materials of the first buried dielectric layer 2 and the second buried dielectric layer 4 may be the same or different, and may be silicon dioxide or other oxide dielectrics, which is not limited herein.
The method for preparing the dielectric buried layer on the semiconductor substrate can also be various, and the method can be deposition growth, oxidation growth of a part of the semiconductor substrate, sputtering growth and the like, and is not limited and is not listed.
Step S102, a high-k dielectric layer 5 is prepared on the first dielectric buried layer 2.
In the embodiment of the present application, the high-k dielectric layer 5 may be HfO2Or may be othersType high k materials, and are not limited herein. The method for preparing the high-k dielectric layer on the dielectric buried layer can also be various, and the method can be deposition growth, sputtering growth and the like, and is not limited and is not listed.
In the embodiment of the present application, in view of achieving the optimal effect of suppressing the net accumulation of trapped charges in the SOI material buried layer, the theoretical total trapped charge density values of the first dielectric buried layer 2, the second dielectric buried layer 4 and the high-k dielectric layer 5 under the preset working condition may be set to approach 0.
Specifically, a first relation between the thickness of the materials of the first dielectric buried layer 2 and the second dielectric buried layer 4 and the density of trapped charges in the first dielectric buried layer and the radiation dose can be tested, and a second relation between the thickness of the materials of the high-k dielectric layer 5 and the density of trapped charges in the high-k dielectric buried layer and the radiation dose can be tested. And determining the thicknesses of the first dielectric buried layer 2, the second dielectric buried layer 4 and the high-k dielectric layer 5 according to the first relation and the second relation, and determining the material type of the high-k dielectric layer 5 so as to achieve the effect that the theoretical total trapped charge density value tends to 0.
In the embodiment of the present application, a capacitance-voltage (C-V) technology of a metal-oxide-semiconductor (MOS) structure or other characterization means may be adopted to perform a characterization of a total dose effect on different high- κ materials with different thicknesses prepared under different processes, so as to obtain a magnitude of a trapped charge density and a positive and a negative of the trapped charge inside the material, and draw a first relation curve of the trapped charge density inside the different materials with different thicknesses along with a change of radiation dose. The C-V technology of the MOS structure or other characterization means can be adopted to perform characterization of the total dose effect on the silicon dioxide films with different thicknesses grown on the silicon wafer, so as to obtain the relation between the trapped charge density caused by radiation and the radiation dose, and draw a second relation curve of the trapped charge density corresponding to the silicon oxide films with different thicknesses along with the change of the radiation dose. And according to the obtained relation curve, selecting one or more types of high-k materials and corresponding thicknesses thereof under the condition that the physical thickness range of the buried layer is determined according to the principle that the density of positive charges and negative charges trapped in the dielectric buried layer are mutually balanced because the positive charges and the negative charges are close or equal, and determining the thicknesses of the first dielectric buried layer 2 and the second dielectric buried layer 4, thereby constructing a composite insulating dielectric buried layer with a laminated structure and preparing the radiation-reinforced SOI material with the composite buried layer.
In one embodiment, since the first buried dielectric layer 2 and the second buried dielectric layer 4 are commonly made of silicon dioxide film with many hole traps and the total dose of radiation will cause the inside to present net positive charge accumulation, if the high-k dielectric layer 5 is a single-layer high-k material as shown in fig. 2, the high-k dielectric material with electron traps should be selected to balance the accumulation of trapped holes by the accumulation of trapped electrons to suppress the net accumulation of trapped charges in the buried layers.
In another embodiment, to better satisfy the principle of balancing the net accumulation of trapped charges in the high-k dielectric layer with the net accumulation of trapped charges in the silicon dioxide film, multiple layers of high-k materials with different types and thicknesses can be selected to be matched and combined with silicon dioxide dielectric layers with different thicknesses, that is, as shown in fig. 3, the high-k dielectric layer 5 includes multiple layers of high-k dielectrics with different types and/or different thicknesses, and the nature of the net trapped charges between the different types of high-k dielectric materials can be opposite, that is, positive net charge accumulation can be performed, or negative net charge accumulation can be performed, so as to achieve better radiation strengthening effect of the total dose.
Preferably, when the high-k dielectric layer 5 includes multiple high-k dielectric layers of different material types and/or different thicknesses, at least one high-k dielectric material having an initial negative charge may be included therein. Since the thermally grown silicon dioxide film usually contains initial fixed positive charges, when the requirement on the initial electrical state of the buried dielectric layer is high, a high-k dielectric material with initial negative charges can be selected as one of the layers in the buried composite layer to eliminate the influence of the initial charges in the buried layer on the silicon interface.
Fig. 2 and 3 schematically illustrate the action mechanism of the mutual suppression of the positive and negative trapped charges in the composite buried layer in electrical properties. Wherein the lines with arrows at the buried layer schematically represent the electric field lines starting from positive charges and ending at negative charges. When the positive and negative charges tend to be balanced, the electric field lines are mainly limited in the buried layer, that is, the non-zero high combined field intensity generated by the positive and negative trapped charges is mainly distributed in the buried layer, so that the influence of the trapped charges on the silicon layer is fully inhibited, and the radiation reinforcement of the total dose of the SOI material is realized.
And step S103, overlapping and connecting the high-k dielectric layer 5 and the second dielectric buried layer 4 to form a silicon-on-insulator material.
In this embodiment, there may be a plurality of methods for connecting the high-k dielectric layer 5 and the second dielectric buried layer 4 in an overlapping manner, and the high-k dielectric layer 5 and the second dielectric buried layer 4 may be connected by bonding, or the high-k dielectric layer 5 and the second dielectric buried layer 4 may be connected by pressing by other processes, which are not limited herein and are not listed.
In this embodiment, one or more layers of high-k dielectric materials with high dielectric constants selected by total dose radiation experiments are embedded in a conventional buried silicon dioxide dielectric layer by bonding or the like to form a composite buried insulating dielectric layer with a stacked structure, as shown in fig. 2 and 3, respectively. On one hand, the upper layer and the lower layer in the buried layer structure are both traditional medium buried layers so as to ensure that the contact interfaces of the buried layers and the upper substrate (silicon or germanium) and the lower substrate (silicon or germanium) layers have lower defect density. On the other hand, the effect of charge traps in the high-k material is utilized to inhibit the net accumulation of trapped charges in the buried layer of the composite insulating medium caused by total dose radiation, the absolute value difference between the amount of trapped positive charges and the amount of trapped negative charges in the buried layer is always in a lower range in the total dose radiation process of the SOI material, and the influence of the trapped charges in the buried layer on the electrical properties of the silicon layer interface and the electrical properties near the interface is effectively weakened by the completely opposite effects of the two kinds of trapped charges with opposite charge properties on the outside, so that the radiation reinforcement of the total dose of the SOI material is realized. Because the design principle that the density of positive charges and negative charges trapped in the buried layer are matched is adopted, the composite medium buried layer is constructed by the bonding process and other processes, and the ion implantation process of the buried layer which can damage the integrity of a top silicon lattice of the SOI material is not involved, the quality of the top silicon of the material is fully guaranteed while the total dose radiation resistance of the SOI material is effectively improved, and the high-quality SOI material with excellent total dose radiation resistance is provided.
A specific example is listed below: assuming that the total buried layer thickness is required to be limited to a range of 100nm to 120nm, and the trapped charge densities of the 20nm and 60nm oxide layers determined by C-V experiments are +3.0 × 1011cm-2And + 9.0X 1011cm-2The sum of the positive charge densities of both being trapped is + 1.2X 1012 cm-2If the high-k dielectric material A is, for example, hafnium oxide (HfO)2) The trapped charge density is negative and exists in the thickness range of 20 to 40nm and the value of the trapped charge density is-1.2 x 1012cm-2Very close corresponding thickness values, assumed to be HfO of 30nm2Then, the top SiO layer of the buried layer can be selected according to the principle that the trapped positive and negative charges in the buried layer are mutually suppressed due to balance2The buried dielectric layer is 20nm, and the bottom layer is SiO2The dielectric buried layer is 60nm, the middle high-k dielectric layer is HfO with the thickness of 30nm2So that the net trapped charge density in the buried layer is negligible, thereby effectively limiting the influence of the trapped charges in the buried layer on the electrical properties of the upper and lower silicon dielectric buried layers. The process flow corresponding to this example may employ: (1) firstly, SiO is respectively obtained on two silicon wafers through an oxidation process2Dielectric layers a and b; (2) then, through a deposition process, in SiO2Depositing HfO on the dielectric layer a or b2A layer; (3) finally, HfO is bonded2Layer and SiO2And bonding the dielectric layer materials to prepare the bonded SOI material without top silicon damage and with excellent radiation reinforcement characteristics.
Based on the same inventive concept, the application also provides a material prepared by the method of the first embodiment, which is detailed in the second embodiment.
Example two
The present embodiment provides a silicon-on-insulator material, as shown in fig. 2 and 3, including:
the semiconductor device comprises a first semiconductor layer 1, a first dielectric buried layer 2, a second dielectric buried layer 4 and a second semiconductor layer 3 which are sequentially stacked;
and a high-k dielectric layer 5 is embedded between the first dielectric buried layer 2 and the second dielectric buried layer 4.
In the embodiment of the application, the theoretical total trapped charge density values of the first dielectric buried layer 2, the second dielectric buried layer 4 and the high-k dielectric layer 5 under the preset working condition tend to 0.
In the present embodiment, the high-k dielectric layer 5 comprises a high-k material having an initial negative charge of electron traps.
In the embodiment of the present application, the high-k dielectric layer 5 includes multiple layers of high-k dielectric layers of different material types and/or different thicknesses.
Since the material described in the second embodiment of the present invention is a material prepared by implementing the method of the first embodiment of the present invention, a person skilled in the art can understand the specific structure and deformation of the material based on the method described in the first embodiment of the present invention, and thus the detailed description thereof is omitted. All materials prepared by the method of the first embodiment of the invention belong to the protection scope of the invention.
The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages:
the method comprises the steps of preparing a first medium buried layer on a first semiconductor substrate, preparing a second medium buried layer on a second semiconductor substrate, and preparing a high-k medium layer on the first medium buried layer, so that one or more layers of high-k medium materials are embedded in a traditional SOI material buried oxide layer (the first medium buried layer and the second medium buried layer), and the net accumulation of trapped charges generated due to total dose radiation in the SOI material buried layer is inhibited under the action of charge traps in the high-k medium materials, so that the technical effect of improving the total dose radiation resistance of a device prepared from the SOI material is realized.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (10)
1. A method of reinforcing a silicon-on-insulator material against total dose radiation, comprising:
preparing a first dielectric buried layer on a first semiconductor substrate, and preparing a second dielectric buried layer on a second semiconductor substrate;
preparing a high-k dielectric layer on the first dielectric buried layer, wherein the material of the high-k dielectric layer is an insulating dielectric material with a relative dielectric constant larger than 7.8, the high-k dielectric layer comprises a plurality of layers of high-k dielectric layers with different material types, and the properties of net trapped charges among the high-k dielectric materials with different types are opposite;
and overlapping and connecting the high-k dielectric layer and the second dielectric buried layer to form a silicon-on-insulator material.
2. The method of claim 1, further comprising:
testing to obtain a first relation between the thickness of the materials of the first dielectric buried layer and the second dielectric buried layer and the density and the radiation dose of trapped charges in the first dielectric buried layer and the second dielectric buried layer;
testing to obtain a second relation between the thickness of the material of the high-k dielectric layer and the density of trapped charges in the high-k dielectric layer and the radiation dose;
determining the thicknesses of the first dielectric buried layer, the second dielectric buried layer and the high-k dielectric layer according to the first relation and the second relation, and determining the material type of the high-k dielectric layer.
3. The method of claim 1 or 2, wherein a theoretical total trapped charge density value of the first buried dielectric layer, the second buried dielectric layer, and the high-k dielectric layer under a preset operating condition tends to 0.
4. The method of claim 1, wherein the high-k dielectric layer comprises a high-k material having an initial negative charge of electron traps.
5. The method of claim 1 or 4, wherein the high-k dielectric layer comprises multiple high-k dielectric layers of different thicknesses.
6. The method of claim 1, wherein said overlappingly connecting said high-k dielectric layer and said second buried dielectric layer comprises:
and bonding and connecting the high-k dielectric layer and the second dielectric buried layer.
7. A silicon-on-insulator material, comprising:
the first semiconductor layer, the first medium buried layer, the second medium buried layer and the second semiconductor layer are sequentially stacked;
the high-k dielectric layer is embedded between the first dielectric buried layer and the second dielectric buried layer, the material of the high-k dielectric layer is an insulating dielectric material with a relative dielectric constant larger than 7.8, the high-k dielectric layer comprises a plurality of layers of high-k dielectric layers with different material types, and the properties of net trapped charges among the high-k dielectric materials with different types are opposite.
8. The silicon-on-insulator material of claim 7, wherein the theoretical total trapped charge density value of the first buried dielectric layer, the second buried dielectric layer and the high-k dielectric layer under preset operating conditions tends to 0.
9. The silicon-on-insulator material of claim 7, wherein the high-k dielectric layer comprises a high-k material having an initial negative charge of electron traps.
10. The silicon-on-insulator material of claim 7, wherein the high-k dielectric layer comprises multiple layers of high-k dielectric layers of different thicknesses.
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