CN109859793B - Multi-threshold OTP memory cell and control method - Google Patents
Multi-threshold OTP memory cell and control method Download PDFInfo
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Abstract
The invention discloses a multi-threshold OTP memory unit and a control method, wherein the multi-threshold OTP memory unit comprises: a plurality of thin gate oxide low voltage memory devices interconnected to said thick gate oxide high voltage select device; the thick gate oxide high-voltage selection device controls the breakdown number of the thin gate oxide low-voltage storage device at least based on the programming current, so that the OTP memory cell realizes multi-threshold storage.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a multi-threshold OTP memory unit and a control method thereof.
Background
With the development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to daily life and work of people, and become an indispensable important tool for people at present.
Generally, most electronic devices need to have a data storage function, so that a memory is a main component of the electronic device. In the field of embedded non-volatile memories, OTP (one time programmable) memories based on antifuse structures are widely used in the fields of analog circuit trimming, key and chip ID (identification card) storage, SRAM (static random access memory)/DRAM (dynamic random access memory) redundancy design, RFID (radio frequency identification) and the like because of their advantages of high stability, complete compatibility with CMOS (complementary metal oxide semiconductor) processes, easy programming, and the like.
At present, as the logic nonvolatile OTP memory IP (intellectual property) kernel is applied more and more in the chip fields of SOC (system on chip) and IOT (internet of things), etc., the storage capacity of the OTP IP is also larger and larger, and the area of the OTP IP becomes more and more critical in order to reduce the cost of the whole chip. Therefore, there is a greater market demand for multi-threshold OTP Memories (MLCs).
Disclosure of Invention
In view of this, the present invention provides a multi-threshold OTP memory and a control method thereof, which can enable the OTP memory to realize multi-threshold storage.
In order to achieve the above purpose, the invention provides the following technical scheme:
a multi-threshold OTP memory cell, comprising:
a thick gate oxide high voltage selection device;
a plurality of thin gate oxide low voltage memory devices interconnected to said thick gate oxide high voltage select device;
wherein the thick gate oxide high voltage selection device controls the number of breakdowns of the thin gate oxide low voltage memory device based on controlling the magnitude of the programming current.
Preferably, in the multi-threshold OTP memory cell, the sources of the thin gate oxide low-voltage memory devices are electrically connected to the drain of the thick gate oxide high-voltage selection device;
the substrate of the thin gate oxide low-voltage storage device and the substrate of the thick gate oxide high-voltage selection device are both grounded;
and the drain electrodes of the thin gate oxide low-voltage storage devices are all floating.
Preferably, in the multi-threshold OTP memory cell, the gate of the thick-gate oxide high-voltage selection device is connected to a word line, and the word line is used for inputting a first voltage;
the grid electrode of the thin-grid oxygen low-voltage storage device is used for inputting a programmable voltage and the programming current;
the source electrode of the thick gate oxide high-voltage selection device is connected with a bit line, and the bit line is used for outputting the programming current;
the thin gate oxygen low-voltage memory devices connected in parallel are of an interdigital structure, and the number of the interdigital is more than or equal to 2.
Preferably, in the multi-threshold OTP memory cell, the thick gate oxide high voltage selection device is an NMOS or a PMOS;
the thin gate oxygen low-voltage memory device is NMOS or PMOS.
Preferably, in the multi-threshold OTP memory cell, the programmable voltage is Vpgm, the programming current is Ipgm, the equivalent resistance of the thin gate oxide low voltage memory device after breakdown is Ron, the number of breakdown is N, N is a positive integer,
Ipgm≥(Vpgm/Ron)*N；
wherein the programming current Ipgm is controlled by adjusting the magnitude of the gate voltage of the thick gate oxide high voltage select device.
Preferably, in the multi-threshold OTP memory cell, the thin gate oxide low-voltage memory device and the thick gate oxide high-voltage selection device are located on the same semiconductor substrate;
the plurality of thin gate oxygen low voltage memory devices comprise: the substrate comprises an interdigital active region, a thin gate oxide layer and a grid electrode, wherein the interdigital active region is formed in the substrate, the thin gate oxide layer and the grid electrode are covered on the interdigital active region, the interdigital active region is provided with a plurality of strip regions which are arranged at intervals, and the grid electrode crosses all the strip regions;
and the grid electrode of the thick grid oxygen high-voltage selection device and the grid electrode of the thin grid oxygen low-voltage storage device are on the same layer and are separated.
Preferably, in the multi-threshold OTP memory cell, the gate of the thick-gate-oxide high-voltage selection device and the gate of the thin-gate-oxide low-voltage storage device are both connected to a word line, and the word line inputs the programming current and the programmable voltage; and controlling the breakdown number of the thin gate oxide low-voltage memory device by limiting the programming current in the word line.
Preferably, in the multi-threshold OTP memory cell, the gate of the thick gate oxide high voltage selection device and the gate of the thin gate oxide low voltage storage device are both connected to the word line through a tuning circuit;
the source electrode of the thick gate oxide high-voltage selection device is connected with a bit line;
the adjusting circuit is at least used for adjusting current input to a grid electrode of the thin-grid oxygen low-voltage storage device so as to provide the set programming current for the thin-grid oxygen low-voltage storage device.
Preferably, in the multi-threshold OTP memory cell, the adjusting circuit includes a plurality of parallel branches, and the number of breakdowns is controlled by controlling the number of breakthroughs in the parallel branches.
Preferably, in the above multi-threshold OTP memory cell, the parallel branch includes a switching element and a resistance element connected in series.
Preferably, in the multi-threshold OTP memory cell, the thin gate oxide low-voltage memory device and the thick gate oxide high-voltage selection device are located on the same semiconductor substrate;
the thin gate oxygen low voltage memory device includes: the substrate comprises an interdigital active region, a thin gate oxide layer and a grid electrode, wherein the interdigital active region is formed in the substrate, the thin gate oxide layer and the grid electrode are covered on the interdigital active region, the interdigital active region is provided with a plurality of strip regions which are arranged at intervals, and the grid electrode crosses all the strip regions;
the grid electrode of the thick grid oxygen high-voltage selection device and the grid electrode of the thin grid oxygen low-voltage storage device are on the same layer and are of an integrated structure.
The present invention also provides a control method for a multi-threshold OTP memory cell according to any of the above claims, the control method comprising:
the thick gate oxide high voltage selection device controls the number of breakdowns of the thin gate oxide low voltage memory device based on controlling the magnitude of the programming current.
As can be seen from the above description, in the multi-threshold OTP memory cell and the control method provided in the present invention, the multi-threshold OTP memory cell includes: a plurality of thin gate oxide low voltage memory devices interconnected to said thick gate oxide high voltage select device; the thick gate oxide high-voltage selection device controls the breakdown number of the thin gate oxide low-voltage storage device based on the size of the programming current, so that the OTP memory cell realizes multi-threshold storage. According to the technical scheme, the magnitude of the programming current can be controlled by controlling the gate terminal voltage of the thick gate oxide high-voltage selection device, so that the breakdown number of the interdigital type thin gate oxide low-voltage storage device is controlled, and multi-threshold storage is realized; optionally, the breakdown number of the interdigital type thin gate oxide low-voltage memory device can be controlled by limiting the magnitude of the programming current at the end of the programming word line, so that the multi-threshold programming is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a cross-sectional view of an OTP memory cell according to an embodiment of the invention;
FIG. 2 is an equivalent circuit corresponding to the OTP memory cell shown in FIG. 1;
FIG. 3 is a top view of an OTP memory cell according to an embodiment of the invention;
FIG. 4 is an equivalent circuit corresponding to the OTP memory cell shown in FIG. 3;
FIG. 5 is a timing diagram of a word line WL input signal according to an embodiment of the present invention;
FIG. 6 is an equivalent circuit diagram of a multi-threshold OTP memory cell according to an embodiment of the invention;
FIG. 7 is a top view of a multi-threshold OTP memory cell corresponding to the manner shown in FIG. 6 according to an embodiment of the invention;
FIG. 8 is a schematic diagram of another multi-threshold OTP memory cell according to an embodiment of the invention;
FIG. 9 is a top view of a multi-threshold OTP memory cell corresponding to the manner shown in FIG. 8 according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a cross-sectional view of an OTP memory cell according to an embodiment of the invention, which includes a thin gate oxide low voltage memory device and a thick gate oxide high voltage selection device disposed on a same substrate 1. The thin gate oxygen low voltage memory device includes: an active region 2 formed in a substrate 1, a thin gate oxide layer 4 on the surface of the substrate 1, and a gate 5 on the surface of the thin gate oxide layer 4. The thick gate oxide high voltage selection device comprises: an active region 2 formed in a substrate 1, a thick gate oxide layer 6 on the surface of the substrate 1, and a gate 5. The thin gate oxide low-voltage memory device and the thick gate oxide high-voltage selection device respectively correspond to different active regions 2.
Referring to fig. 2, fig. 2 is an equivalent circuit corresponding to the OTP memory cell shown in fig. 1, wherein the gate 3 of the thin-gate low-voltage memory device M2 is connected to the gate 5 of the thick-gate high-voltage selection device M1, and both are connected to the word line WL. The substrate of the thin gate oxide low voltage memory device M2 and the substrate of the thick gate oxide high voltage selection device M1 are connected and both are connected to a low potential VSS. The source of the thick gate oxide high voltage select device M1 is connected to the bit line BL, its drain is connected to the source of the thin gate oxide low voltage memory device M2, and the drain of the thin gate oxide low voltage memory device M2 is floating. When the OTP memory cell is programmed, a high voltage is applied to the gate 3 and the active region 2 of the thin gate oxide low voltage memory device M2, for example, in a 0.18 μ M process, and after a set time, the thin gate oxide layer 4 is permanently broken down.
As described in the background art, as the application of the IP (intellectual property) kernel of the logic nonvolatile OTP (one time programmable) memory in the chip fields of SOC (system on chip) and IOT (internet of things) is increasing, the storage capacity of the OTP IP is also increasing, and the area of the OTP IP is becoming more and more critical to reduce the cost of the whole chip. Therefore, there is a greater market demand for multi-threshold OTP Memories (MLCs).
With the increasing demand of the market for MTP (multiple time programmable) memories IP, when the device process size is smaller than 40nm, it is more and more difficult to implement MTP based on the floating gate technology. Usually, the MTP is realized by a technology of connecting a plurality of OTP memory cells in parallel, so that a higher requirement is put on the area of a unit bit OTP memory cell. The multi-threshold OTP memory is one of the most effective methods for reducing the unit bit OTP memory cell area. One implementation is shown in fig. 3 and 4.
Referring to fig. 3 and 4, fig. 3 is a top view of an OTP memory cell according to an embodiment of the invention, and fig. 4 is an equivalent circuit corresponding to the OTP memory cell shown in fig. 3, in which a thick gate oxide high voltage selection device M11 and a plurality of thin gate oxide low voltage memory devices M12 electrically interconnected with the thick gate oxide high voltage selection device M11 are disposed on the same substrate 1. The thick gate oxide high voltage select device M11 and the thin gate oxide low voltage memory device M12 are disposed on the same substrate 100. An active region 110 is provided within the substrate 100, the active region 100 being an interdigitated active region. A gate layer is disposed on the active region 110. The gate layer includes: the grid 130 of the thick grid oxygen high-voltage selection device M11 and the grid 120 of the thin grid oxygen low-voltage storage device M12 are made of the same layer of material in a patterning mode, and the grid of the two devices are of an integrated structure and are connected with each other. There is a gate oxide layer (not shown in fig. 3) between the active region 110 and the gate layer. The gate oxide layer includes: a thick gate oxide layer of the thick gate oxide high voltage select device M11 and a thin gate oxide layer of the thin gate oxide low voltage memory device M12.
In fig. 4, only one thick gate oxide high voltage select device M11 is shown, along with 3 thin gate oxide low voltage memory devices M12 electrically interconnected with the thick gate oxide high voltage select device M11. The number of the thin-gate oxygen low-voltage memory devices M12 can be set to any number according to the requirement, and is not limited to the 3 shown in fig. 4. One thin gate oxide low voltage memory device M12 corresponds to one memory cell.
The source of the thick-gate oxygen high-voltage selection device M11 is connected to the bit line BL, the gate 130 thereof is connected to the gate 120 of the thin-gate oxygen low-voltage memory device M12, respectively, and the gate 130 thereof is connected to the word line WL. The word line WL inputs a programming voltage Vpgm and a programming current Ipgm. Fig. 5 shows a timing chart of the input signal of the word line WL according to an embodiment of the invention, where fig. 5 is a timing chart of the input signal of the word line WL, and the duration of the input signal is controlled by controlling the program time Tpgm. The substrate of the thick gate oxide high voltage selection device M11 and the substrate of the thin gate oxide low voltage memory device M12 are both inputted with the low potential VSS, so that both substrates are grounded GND, i.e., the low potential VSS is zero potential. The drains of the thin gate oxide low voltage memory devices M12 are all floating, and their sources are all connected to the drain of the thick gate oxide high voltage select device M11.
In the manner shown in FIG. 4, prior to programming, the gate oxide antifuse dielectric (thin gate oxide layer 120) in the memory cell is nonconductive and represents a memory state of "0". During programming, the word line WL is applied with the signal shown in fig. 5, and only the gate oxide antifuse dielectric of one memory cell is broken down and becomes conductive, representing a memory state "1".
The program breakdown of the gate oxide antifuse is related to a program voltage Vpgm, a program current Ipgm, and a program time Tpgm. When the programming time Tpgm is constant, the thin gate oxide layer can be effectively broken down only when the programming voltage Vpgm and the programming current Ipgm simultaneously satisfy a certain condition, the programming is successful, and the state of the memory cell is rewritten. For example, for a standard 0.13um process, the thin gate oxide thickness of a logic device (thin gate oxide low voltage memory device) is around 2nm, and when Tpgm is 100us, the thin gate oxide can be effectively broken down only when Vpgm >5V and Ipgm >10 uA. However, the circuit structure shown in fig. 4 can only make the thin gate oxide layer of one thin gate oxide low-voltage memory device break down at the same time.
Based on this, an embodiment of the present invention provides a multi-threshold OTP memory cell and a control method, including: a plurality of thin gate oxide low voltage memory devices interconnected to said thick gate oxide high voltage select device; the thick gate oxide high-voltage selection device controls the breakdown number of the thin gate oxide low-voltage storage device based on the control of the magnitude of the programming current, so that the OTP memory cell realizes multi-threshold storage.
Referring to fig. 6, fig. 6 is an equivalent circuit diagram of a multi-threshold OTP memory cell according to an embodiment of the present invention, where the multi-threshold OTP memory cell includes: a thick gate oxide high voltage select device M21; a plurality of thin gate oxide low voltage memory devices M22 interconnected with said thick gate oxide high voltage select device M21; the thick gate oxide high-voltage selection device M21 controls the breakdown number of the thin gate oxide low-voltage storage device M22 based on the control of the size of the programming current Ipgm, so that the OTP memory cell realizes multi-threshold storage.
As shown in fig. 6, the sources of the thin gate oxide low voltage memory devices M22 are all electrically connected to the drain of the thick gate oxide high voltage selection device M21; the substrate of the thin gate oxide low-voltage memory device M22 and the substrate of the thick gate oxide high-voltage selection device M21 are both grounded GND; the drains of the thin gate oxide low voltage memory devices M22 are all floating.
In the manner shown in fig. 6, the gate of the thick gate oxide high voltage selection device M21 is connected to a word line WL for inputting a first voltage Vwl; the gate of the thin gate oxide low voltage memory device M22 is used for inputting a programming voltage Vpgm and the programming current Ipgm, and specifically, the gate thereof may be connected to a signal line PL through which the programming voltage Vpgm and the programming current Ipgm are transmitted; the source of the thick-gate oxide high-voltage select device M21 is connected to a bit line BL for outputting the programming current Ipgm. The sources of all the thin-gate oxygen low-voltage memory devices M22 are at the same potential and are connected with the drain of the thick-gate oxygen high-voltage selection device M21, the drains of all the thin-gate oxygen low-voltage memory devices M22 are floating, and the gates of all the thin-gate oxygen low-voltage memory devices M22 are at the same potential and are connected with the signal line PL, which is equivalent to that all the thin-gate oxygen low-voltage memory devices M22 are connected in parallel. The thin gate oxygen low-voltage memory devices connected in parallel are of an interdigital structure, and the number of the interdigital is more than or equal to 2.
Optionally, the thick gate oxide high voltage selection device 21 may be an NMOS or a PMOS; the thin gate oxide low voltage memory device 22 may be NMOS or PMOS.
In the manner shown in fig. 6, the thick gate oxide high voltage selection device M21 is reasonably sized to operate in the saturation region during programming, and may be equivalent to a current source, and the programming current Ipgm flowing through it may be expressed as:
Ipgm＝Kn(Vwl-Vt)2 (1)
where Vt represents the threshold voltage of the thick gate oxide high voltage select device M21. Setting the equivalent resistance of the thin gate oxide low-voltage memory device 22 after breakdown as Ron, and if the following conditions are met:
Ipgm≥(Vpgm/Ron)*N (2)
the programming current Ipgm is controlled by adjusting the magnitude of the gate voltage of the thick gate oxide high voltage select device 21. The number of the breakdowns is N, N is a positive integer, the programming current Ipgm is controlled by adjusting the first voltage Vwl, and the number of the breakdowns is further controlled to be N. In the mode shown in fig. 6, one thick-gate oxygen high-voltage selection device M21 is interconnected with 3 thin-gate oxygen low-voltage memory devices M22, and in the embodiment of the invention, the number of thin-gate oxygen low-voltage memory devices M22 interconnected by the same thick-gate oxygen high-voltage selection device M21 can be set according to requirements, and is not limited to 3 shown in fig. 6. In the manner shown in fig. 6, 4 non-memory cell breakdown induced post-resistance can be achieved. Each memory cell can store 2bits of data.
Referring to fig. 7, fig. 7 is a top view of a multi-threshold OTP memory cell corresponding to the mode shown in fig. 6, in which the thin-gate-oxide low-voltage memory device and the thick-gate-oxide high-voltage selection device are located on the same semiconductor substrate 200; that is, all the thick-gate-oxide high-voltage selection devices with which the thin-gate-oxide low-voltage memory device is interconnected are fabricated on the same semiconductor substrate 200. The plurality of thin gate oxygen low voltage memory devices comprise: an inter-digitated active region 210 formed in the substrate 200, a thin gate oxide layer (not shown in fig. 7) covering the inter-digitated active region 210, and a gate 220, wherein the inter-digitated active region 210 has a plurality of strip regions arranged at intervals, and the gate 220 crosses all the strip regions; the gate 230 of the thick gate oxide high voltage selection device is at the same level as the gate 220 of the thin gate oxide low voltage memory device, and is separated therefrom.
Alternatively, in the manner shown in fig. 7, the thin gate oxide low voltage memory device and the active region of the thick gate oxide high voltage selection device are integrated.
In the embodiment of the present invention, the gate of the thick gate oxide high voltage selection device 21 and the gate of the thin gate oxide low voltage storage device 22 are both connected to a word line, and the word line inputs the programming current and the programmable voltage; and controlling the breakdown number of the thin gate oxide low-voltage memory device by limiting the programming current in the word line. A specific implementation may be as shown in fig. 8.
Referring to fig. 8, fig. 8 is an equivalent circuit diagram of another multi-threshold OTP memory cell provided in an embodiment of the present invention, where the multi-threshold OTP memory cell includes: a thick gate oxide high voltage select device M21; a plurality of thin gate oxide low voltage memory devices M22 interconnected with said thick gate oxide high voltage select device M21; wherein the thick gate oxide high voltage select device M21 controls the number of breakdowns of the thin gate oxide low voltage memory device M22 based on controlling the magnitude of the programming current Ipgm. Similarly, the sources of the thin gate oxide low-voltage memory devices M22 are all electrically connected with the drain of the thick gate oxide high-voltage selection device M21; the substrate M22 of the thin gate oxide low-voltage memory device and the substrate of the thick gate oxide high-voltage selection device M21 are both grounded GND; the drains of the thin gate oxide low voltage memory devices M22 are all floating.
In the manner shown in fig. 8, the gate of the thick-gate oxide high-voltage selection device M21 and the gate of the thin-gate oxide low-voltage storage device 22 are both connected to a word line WL through the regulator circuit 31, and the word line WL is used for inputting a programmable voltage Vwl; the gate of the thin gate oxide low-voltage storage device M22 is connected with the gate of the thick gate oxide high-voltage selection device M21; the source electrode of the thick gate oxide high-voltage selection device M21 is connected with a bit line BL; the regulating circuit 31 is at least used for regulating the current input to the gate of the thin-gate oxide low-voltage memory device M22 to provide the set programming current Ipgm for the thin-gate oxide low-voltage memory device M22, so that a set number of thin-gate oxide low-voltage memory devices M22 break down.
As shown in fig. 8, the adjusting circuit 31 includes a plurality of parallel branches, and the number of breakdowns is controlled by controlling the number of breakdowns conducted by the parallel branches. The number of the parallel branches can be the same as or different from the number of the thin-gate oxygen low-voltage memory devices M22, the conducting number of the parallel branches is simply controlled, so that the corresponding number of thin-gate oxygen low-voltage memory devices M22 are broken down, and when M parallel branches are conducted, M thin-gate oxygen low-voltage memory devices M22 are broken down, wherein M is a positive integer and is not larger than the number of the thin-gate oxygen low-voltage memory devices M22. Optionally, the parallel branch comprises a switching element S and a resistance element r connected in series.
In the manner shown in fig. 8, the number of thin gate oxide low-voltage memory devices M22 interconnected by the thick gate oxide high-voltage selection device M21 can also be set according to requirements, and is not limited to the 3 thin gate oxide low-voltage memory devices M22 shown in fig. 8. When the number of the thin gate oxide low-voltage memory devices M22 interconnected by the thick gate oxide high-voltage selection device M21 is 3, 3 parallel branches can be arranged, and the switching elements in the 3 parallel branches are S1/S2/S3 in sequence. The series resistance of the first voltage Vwl during programming is adjusted through the switch S1/S2/S3, so that the breakdown number of the inserted antifuse memory device is controlled, and the antifuse unit after programming presents 3 different resistance values. And 2bits of data can be stored in a single storage unit. In the embodiment of the invention, the state for realizing 0 antifuse breakdown is also 1 state.
Assuming Tpgm is constant, the voltage and current required for gate-oxide antifuse breakdown are Vpgm and Ipgm, respectively, the device operates in the linear region, assuming a negligible voltage drop, and when 1 antifuse cell breaks down, the word line WL series resistance can be expressed as:
R＝Rp＝(Vwl-Vpgm)/Ipgm
when 2 antifuse cells break down, the word line WL series resistance can be expressed as:
R＝(Vwl-Vpgm)/(2*Ipgm)＝Rp/2
when 3 antifuse cells break down, the word line WL series resistance can be expressed as:
R＝(Vwl-Vpgm)/(3*Ipgm)＝Rp/3
where Rp is expressed as the resistance representing a single parallel branch.
Referring to fig. 9, fig. 9 is a top view of a multi-threshold OTP memory cell corresponding to the mode shown in fig. 8, in which the thin-gate-oxide low-voltage memory device and the thick-gate-oxide high-voltage selection device are located on the same semiconductor substrate 200; the thin gate oxygen low voltage memory device includes: an inter-digitated active region 210 formed in the substrate, a thin gate oxide layer (not shown in fig. 7) covering the inter-digitated active region 210, and a gate 220, wherein the inter-digitated active region 210 has a plurality of strip regions arranged at intervals, and the gate 220 crosses all the strip regions; the gate 230 of the thick gate oxide high voltage selection device and the gate 220 of the thin gate oxide low voltage storage device are on the same layer and are of an integrated structure. Alternatively, in the manner shown in fig. 9, the thin gate oxide low voltage memory device and the active region of the thick gate oxide high voltage selection device are integrated.
According to the above description, the thick gate oxide high voltage selection device controls the number of breakdowns of the thin gate oxide low voltage memory device at least based on the programming current, so that the OTP memory cell realizes multi-threshold storage. According to the technical scheme of the embodiment of the invention, the thick gate oxide high-voltage selection device and the plurality of interconnected thin gate oxide low-voltage storage devices thereof can be integrated in the same OTP memory unit, and the method is one of the most effective schemes for reducing the unit area of the unit bit OTP memory unit.
Based on the foregoing embodiment, another embodiment of the present invention further provides a control method for a multi-threshold OTP memory cell described in the foregoing embodiment, where the control method includes: the thick gate oxide high voltage selection device controls the number of breakdowns of the thin gate oxide low voltage memory device based on controlling the magnitude of the programming current.
The control method according to the embodiment of the present invention can implement multi-threshold storage in the OTP memory through the multi-threshold OTP memory cell according to the above embodiment, and the control principle can be described with reference to the above embodiment, which is not described herein again, and the control method is simple and has low cost.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the control method disclosed in the embodiment, since it corresponds to the multi-threshold OTP memory cell disclosed in the embodiment, the description is relatively simple, and relevant points can be described with reference to the corresponding part of the multi-threshold OTP memory cell.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. A multi-threshold OTP memory cell, comprising:
a thick gate oxide high voltage selection device;
a plurality of thin gate oxide low voltage memory devices interconnected to said thick gate oxide high voltage select device;
wherein the thick gate oxide high voltage selection device controls the number of breakdowns of the thin gate oxide low voltage memory device based on controlling the magnitude of the programming current;
the grid electrode of the thick gate oxide high-voltage selection device is connected with a word line, and the word line is used for inputting a first voltage; the grid electrode of the thin-grid oxygen low-voltage storage device is used for inputting a programmable voltage and the programming current; the source electrode of the thick gate oxide high-voltage selection device is connected with a bit line, and the bit line is used for outputting the programming current; the thin gate oxygen low-voltage memory devices connected in parallel are of an interdigital structure, and the number of the interdigital is more than or equal to 2.
2. The multi-threshold OTP memory cell of claim 1, wherein the sources of the thin-gate-oxide low-voltage memory devices are each electrically connected to the drain of the thick-gate-oxide high-voltage select device;
the substrate of the thin gate oxide low-voltage storage device and the substrate of the thick gate oxide high-voltage selection device are both grounded;
and the drain electrodes of the thin gate oxide low-voltage storage devices are all floating.
3. The multi-threshold OTP memory cell according to claim 1, said thick gate oxide high voltage select device being either NMOS or PMOS;
the thin gate oxygen low-voltage memory device is NMOS or PMOS.
4. The multi-threshold OTP memory cell of claim 1 wherein the programming voltage is Vpgm, the programming current is Ipgm, the equivalent resistance of the thin gate oxide low voltage memory device after breakdown is Ron, the number of breakdown is N, N is a positive integer,
Ipgm≥(Vpgm/Ron)*N；
wherein the programming current Ipgm is controlled by adjusting the magnitude of the gate voltage of the thick gate oxide high voltage select device.
5. The multi-threshold OTP memory cell of claim 1, wherein the thin-gate-oxide low-voltage memory device and the thick-gate-oxide high-voltage selection device are located on a same semiconductor substrate;
the plurality of thin gate oxygen low voltage memory devices comprise: the substrate comprises an interdigital active region, a thin gate oxide layer and a grid electrode, wherein the interdigital active region is formed in the substrate, the thin gate oxide layer and the grid electrode are covered on the interdigital active region, the interdigital active region is provided with a plurality of strip regions which are arranged at intervals, and the grid electrode crosses all the strip regions;
and the grid electrode of the thick grid oxygen high-voltage selection device and the grid electrode of the thin grid oxygen low-voltage storage device are on the same layer and are separated.
6. The multi-threshold OTP memory cell of claim 1 or 2, wherein the gate of the thick-gate oxide high-voltage selection device and the gate of the thin-gate oxide low-voltage storage device are both connected to a word line, and the word line inputs the programming current and the programmable voltage; and controlling the breakdown number of the thin gate oxide low-voltage memory device by limiting the programming current in the word line.
7. The multi-threshold OTP memory cell of claim 6, wherein the gate of the thick-gate oxide high-voltage select device and the gate of the thin-gate oxide low-voltage memory device are both connected to the word line through a trimming circuit;
the source electrode of the thick gate oxide high-voltage selection device is connected with a bit line;
the adjusting circuit is at least used for adjusting current input to a grid electrode of the thin-grid oxygen low-voltage storage device so as to provide the set programming current for the thin-grid oxygen low-voltage storage device.
8. The multi-threshold OTP memory cell of claim 7, wherein the trimming circuit comprises a plurality of parallel branches, and wherein the number of breakdowns is controlled by controlling the number of breakthroughs of the parallel branches.
9. The multi-threshold OTP memory cell of claim 8, wherein the parallel branch comprises a switching element and a resistive element in series.
10. The multi-threshold OTP memory cell of claim 7, wherein the thin-gate-oxide low-voltage memory device and the thick-gate-oxide high-voltage selection device are located on a same semiconductor substrate;
the thin gate oxygen low voltage memory device includes: the substrate comprises an interdigital active region, a thin gate oxide layer and a grid electrode, wherein the interdigital active region is formed in the substrate, the thin gate oxide layer and the grid electrode are covered on the interdigital active region, the interdigital active region is provided with a plurality of strip regions which are arranged at intervals, and the grid electrode crosses all the strip regions;
the grid electrode of the thick grid oxygen high-voltage selection device and the grid electrode of the thin grid oxygen low-voltage storage device are on the same layer and are of an integrated structure.
11. A control method for a multi-threshold OTP memory cell according to any of claims 1-10, characterized in that the control method comprises:
the thick gate oxide high voltage selection device controls the number of breakdowns of the thin gate oxide low voltage memory device based on controlling the magnitude of the programming current.
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