CN109859687B - Pixel circuit, display circuit and display device - Google Patents
Pixel circuit, display circuit and display device Download PDFInfo
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- CN109859687B CN109859687B CN201910263318.1A CN201910263318A CN109859687B CN 109859687 B CN109859687 B CN 109859687B CN 201910263318 A CN201910263318 A CN 201910263318A CN 109859687 B CN109859687 B CN 109859687B
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Abstract
The application provides a pixel circuit, a display circuit and a display device. The pixel circuit comprises a light emitting module, a light emitting control module and a driving control module. The light emitting module is electrically connected with the first power signal end. The light-emitting control module is electrically connected with the light-emitting module and used for controlling the light-emitting of the light-emitting module, the light-emitting control module comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series, the grid electrode of the first transistor is used for receiving a first light-emitting control signal, and the grid electrode of the second transistor is used for receiving a second light-emitting control signal. The driving control module is electrically connected with the light emitting control module and is used for receiving the first scanning signal and the second scanning signal, the first scanning signal and the first light emitting control signal are in opposite phase, and the second scanning signal and the second light emitting control signal are in opposite phase. The display circuit includes a pixel circuit and a gate driver circuit. The grid drive circuit is connected with the pixel circuit and comprises a scanning signal generation module and an inverting circuit. The display device includes a display circuit.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a pixel circuit, a display circuit and a display device.
Background
A driving signal and a Light Emitting control signal of an existing OLED (Organic Light-Emitting Diode) pixel circuit need to be output from different GOA (Gate Driver on Array, Array substrate line Driver) units respectively, so that the space is occupied, the display frame is wide, and the user experience is affected.
Disclosure of Invention
The application provides a pixel circuit, a display circuit and a display device, which can reduce a display frame.
One aspect of the present application provides a pixel circuit, comprising: the light-emitting module is electrically connected with the first power signal end; the light-emitting control module is electrically connected with the light-emitting module and used for controlling the light-emitting of the light-emitting module, the light-emitting control module comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series, the grid electrode of the first transistor is used for receiving a first light-emitting control signal, and the grid electrode of the second transistor is used for receiving a second light-emitting control signal; and the driving control module is electrically connected with the light-emitting control module, and is used for receiving a first scanning signal and a second scanning signal, the first scanning signal and the first light-emitting control signal are in opposite phase, and the second scanning signal and the second light-emitting control signal are in opposite phase.
Another aspect of the present application provides a display circuit, comprising: the above display circuit; and the grid driving circuit is connected with the pixel circuit and comprises a scanning signal generating module and an inverting circuit, wherein the scanning signal generating module is used for generating the first scanning signal and the second scanning signal, the inverting circuit is used for inverting the first scanning signal to generate the first light-emitting control signal and inverting the second scanning signal to generate the second light-emitting control signal.
Yet another aspect of the present application provides a display device, including: the display circuit is described above.
A first transistor and a second transistor in the pixel circuit are connected in series, a grid electrode of the first transistor is used for receiving a first light-emitting control signal, and a grid electrode of the second transistor is used for receiving a second light-emitting control signal. The display circuit comprises a pixel circuit and a grid electrode driving circuit. The grid driving circuit comprises a scanning signal generating module and an inverting circuit, wherein the scanning signal generating module is used for generating a first scanning signal and a second scanning signal, the inverting circuit is used for inverting the first scanning signal to generate a first light-emitting control signal, and inverting the second scanning signal to generate a second light-emitting control signal. Therefore, the first scanning signal and the first light-emitting control signal are output from the same grid drive circuit, and the second scanning signal and the second light-emitting control signal are output from the same grid drive circuit, so that the display frame can be reduced, and the user experience is improved.
Drawings
FIG. 1 is a block circuit diagram of one embodiment of a display circuit of the present application;
FIG. 2 is a circuit diagram of one embodiment of the first gate driver circuit shown in FIG. 1;
FIG. 3 is a timing diagram of the first gate driving circuit shown in FIG. 2;
FIG. 4 is a circuit diagram of one embodiment of the pixel circuit shown in FIG. 1;
FIG. 5 is a driving timing diagram of the pixel circuit shown in FIG. 4;
fig. 6 is a circuit diagram of another embodiment of the pixel circuit shown in fig. 2.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The pixel circuit of the embodiment of the application comprises a light emitting module, a light emitting control module and a driving control module. The light emitting module is electrically connected with the first power signal end. The light-emitting control module is electrically connected with the light-emitting module and used for controlling the light-emitting of the light-emitting module, the light-emitting control module comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series, the grid electrode of the first transistor is used for receiving a first light-emitting control signal, and the grid electrode of the second transistor is used for receiving a second light-emitting control signal. The driving control module is electrically connected with the light emitting control module and is used for receiving the first scanning signal and the second scanning signal, the first scanning signal and the first light emitting control signal are in opposite phase, and the second scanning signal and the second light emitting control signal are in opposite phase. The display circuit includes a pixel circuit and a gate driver circuit. The grid driving circuit is connected with the pixel circuit and comprises a scanning signal generating module and an inverting circuit, wherein the scanning signal generating module is used for generating a first scanning signal and a second scanning signal, the inverting circuit is used for inverting the first scanning signal to generate a first light-emitting control signal, and inverting the second scanning signal to generate a second light-emitting control signal. The display device includes a display circuit. Therefore, the first scanning signal and the first light-emitting control signal are output from the same grid drive circuit, and the second scanning signal and the second light-emitting control signal are output from the same grid drive circuit, so that the display frame can be reduced, and the user experience is improved.
Fig. 1 is a block circuit diagram of an embodiment of a display circuit 100 of the present application. The display circuit 100 includes a pixel circuit 20 and a gate driver circuit 10. The Gate driving circuit 10 is connected to the pixel circuit 20, and includes a scan signal generating module 13 and an inverter circuit 14, wherein the scan signal generating module 13 is configured to generate a first scan signal Gate1 and a second scan signal Gate2, the inverter circuit 14 is configured to invert the first scan signal Gate1 to generate a first emission control signal EM1, and invert the second scan signal Gate2 to generate a second emission control signal EM 2.
In one embodiment, the Gate driving circuit 10 includes a first Gate driving circuit 11 and a second Gate driving circuit 12, the first Gate driving circuit 11 includes a first scan signal generating module 110 and a first inverter circuit 111, the first scan signal generating module 110 is configured to generate a first scan signal Gate1, the first inverter circuit 111 is configured to invert the first scan signal Gate1 to generate a first emission control signal EM 1; the second Gate driving circuit 12 includes a second scan signal generating module 120 and a second inverter circuit 121, wherein the second scan signal generating module 120 is configured to generate a second scan signal Gate2, and the second inverter circuit 121 is configured to invert the second scan signal Gate2 to generate a second emission control signal EM 2. The first scan signal Gate1, the first emission control signal EM1, the second scan signal Gate2, and the second emission control signal EM2 generated by the Gate driving circuit 10 are output to the pixel circuit 20, and drive the pixel circuit 20.
Fig. 2 is a circuit diagram of an embodiment of the first gate driving circuit 11 shown in fig. 1. The first gate driving circuit 11 includes a first scan signal generating module 110 and a first inverter circuit 111. In the illustrated embodiment, the first gate driving circuit 11 includes a plurality of transistors T1-T11 and a plurality of capacitors C1-C3. Wherein the transistors T1-T11 are P-type transistors.
In the illustrated embodiment, the first scan signal generating module 110 includes transistors T1-T7 and capacitors C1-C2, wherein a drain of the transistor T1 receives the first input signal EI1, gates of the transistors T1, T2, and T3 receive the first clock signal CLK, drains of the transistors T5 and T7 receive the second clock signal CLKB, sources of the transistors T4 and T6 are connected to the high voltage signal terminal VH, and a drain of the transistor T3 is connected to the low voltage signal terminal VL. The source of the transistor T1 is connected to the gate of the transistor T2, the drain of the transistor T7 and the gate of the transistor T5; the source of the transistor T2 is connected to the source of the transistor T3, the gate of the transistor T4 and the gate of the transistor T6; the drain of the transistor T4 is connected to the source of the transistor T5; the drain of the transistor T6 is connected to the source of the transistor T7; the capacitor C1 is connected between the gate and the source of the transistor T5; the capacitor C2 is connected between the gate and the source of the transistor T4. The first scan signal generating module 110 generates a first scan signal Gate1 under the control of a first clock signal CLK and a second clock signal CLKB according to the first input signal EI 1. And outputs the first scan signal Gate1 to the first inverter circuit 111.
In the illustrated embodiment, the first inverter circuit 111 includes transistors T8-T11 and a capacitor C3. The gate of the transistor T8 receives the first clock signal CLK, the drain of the transistor T8 and the drain of the transistor T11 are connected to the low voltage signal terminal VL, and the source of the transistor T9 and the source of the transistor T10 are connected to the high voltage signal terminal VH. The source of the transistor T8 is connected to the drain of the transistor T9 and the gate of the transistor T11; the gate of the transistor T9 is connected to the drain of the transistor T4 and the gate of the transistor T10, and the drain of the transistor T10 is connected to the source of the transistor T11; the capacitor C3 has one terminal receiving the first clock signal CLK and the other terminal connected to the source of the transistor T8. The first inverter circuit 111 generates a first emission control signal EM1 under the control of the first clock signal CLK and the second clock signal CLKB according to the input first scan signal Gate 1. The first gate driving circuit 11 in the illustrated embodiment is an embodiment of a GOA unit.
Fig. 3 is a timing chart of the first gate driving circuit 11 shown in fig. 2. Referring to fig. 2 and 3, in the first phase s1, the first input signal EI1 and the first clock signal CLK are at a low level, the second clock signal CLKB is at a high level, the transistors T1, T2, and T3 are turned on, and further the transistors T4 and T5 are turned on, the first scan signal Gate1 outputs a high level, and is inverted by the first inverter circuit 111, and the first emission control signal EM1 outputs a low level; in the second stage s2, the first input signal EI1 and the first clock signal CLK are at a high level, the second clock signal CLKB is at a low level, the transistors T2 and T5 are turned on, the transistors T1 and T3 are turned off, the first clock signal CLK is written into the Gate of the transistor T4, the transistor T4 is turned off, the second clock signal CLKB is written into the source of the transistor T5, the first scan signal Gate1 outputs a low level, which is inverted by the first inverter circuit 111, the first emission control signal EM1 outputs a high level, and the second clock signal CLKB is coupled to the Gate of the transistor T5 through the capacitor C1, so that the Gate level is lower, and the transistor T5 is ensured to be fully turned on. From the third stage s3, the transistors T4 and T5 are always on, the first scan signal Gate1 is always at a high level, and correspondingly, the first emission control signal EM1 is always at a low level from the third stage.
The second gate driving circuit 12 is similar to the first gate driving circuit 11 shown in fig. 2, and the second gate driving circuit 12 is also an embodiment of a GOA unit. Detailed description reference is made to the above description and no further description is deemed necessary.
Fig. 4 is a circuit diagram illustrating one embodiment of the pixel circuit 20 shown in fig. 1. The pixel circuit 20 may be driven by the first scan signal Gate1 and the first emission control signal EM1 generated by the first Gate driving circuit 11 shown in fig. 2, and by the second scan signal Gate2 and the second emission control signal EM2 generated by the second Gate driving circuit 12 (not shown). The pixel circuit 20 includes a light emitting module 201, a light emitting control module 202, and a driving control module 203. The light emitting module 20 is electrically connected to the first power signal terminal ELVSS.
The light emission control module 202 is electrically connected to the light emitting module 201 and configured to control light emission of the light emitting module 201, the light emission control module 202 includes a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 are connected in series, a gate of the first transistor M1 is configured to receive the first light emission control signal EM1, and a gate of the second transistor M2 is configured to receive the second light emission control signal EM 2. The driving control module 203 is electrically connected to the light emission control module 202, and the driving control module 203 is configured to receive the first scan signal Gate1 and the second scan signal Gate2, and the first scan signal Gate1 and the first light emission control signal EM1 are inverse, and the second scan signal Gate2 and the second light emission control signal EM2 are inverse. In this way, the first scan signal Gate1 and the first emission control signal EM1 may be output by the same Gate driving circuit, and the second scan signal Gate2 and the second emission control signal EM2 may also be output by the same Gate driving circuit, so that a display frame may be reduced, and user experience may be improved.
Referring to fig. 4, in one embodiment, an anode of the light emitting module 201 is connected to a drain of the second transistor M2, and a cathode of the light emitting module 201 is connected to the first power signal terminal ELVSS. In one embodiment, the light emitting module 201 includes an organic light emitting diode.
In one embodiment, the driving control module 203 includes a driving transistor M3, a source of the driving transistor M3 is connected to the second power signal terminal ELVDD, and a drain of the driving transistor M3 is connected to the source of the first transistor M1.
In one embodiment, the driving control module 203 includes a compensation transistor M4, a gate of the compensation transistor M4 is configured to receive the second scan signal, a source of the compensation transistor M4 is connected to the source of the first transistor M1 and the drain of the driving transistor M3, a drain of the compensation transistor M4 is connected to the gate of the driving transistor M3, and a compensation transistor M4 is configured to compensate the driving voltage of the driving transistor M3.
In one embodiment, the driving control module 203 includes a reset transistor M5, a Gate of the reset transistor M5 is used for receiving the first scan signal Gate1, a source of the reset transistor M5 is connected to a Gate of the driving transistor M3, a drain of the reset transistor M5 is used for receiving the reset signal vinitial, and a reset transistor M5 is used for resetting the driving voltage of the driving transistor M3.
In one embodiment, the driving control module 203 comprises a storage capacitor C, a first plate of the storage capacitor C is connected to the gate of the driving transistor M3, and the storage capacitor C is used for storing the driving voltage applied to the driving transistor M3.
In one embodiment, the driving control module 203 includes a voltage holding transistor M6, a source of the voltage holding transistor M6 is connected to the second power signal terminal ELVDD or the reference power signal terminal Vref, and the second power signal terminal ELVDD and the reference power signal terminal Vref are two different power signal terminals. When the source of the voltage holding transistor M6 is connected to the second power supply signal terminal ELVDD, the source of the voltage holding transistor M6 is disconnected from the reference power supply signal terminal Vref; when the source of the voltage holding transistor M6 is connected to the reference power signal terminal Vref, the source of the voltage holding transistor M6 is disconnected from the second power signal terminal ELVDD. The gate of the voltage holding transistor M6 is used for receiving the second light emission control signal EM2, the drain of the voltage holding transistor M6 is connected to the second plate of the storage capacitor C, and the voltage holding transistor M6 is used for providing a stable driving voltage to the driving transistor M3 when it is turned on.
In one embodiment, the driving control module 203 includes a data writing transistor M7, a Gate of the data writing transistor M7 is configured to receive the second scan signal Gate2, a drain of the data writing transistor M7 is configured to receive the data signal VData, a source of the data writing transistor M7 is connected to the second plate of the storage capacitor C, and a data writing transistor M7 is configured to write the data signal VData into the storage capacitor C.
Fig. 5 is a timing chart showing the driving of the pixel circuit 20 shown in fig. 4. The timing chart shows the level states of the first scan signal Gate1, the first emission control signal EM1, the second scan signal Gate2, and the second emission control signal EM2 for three periods. Referring to fig. 4 and 5, the operation of the pixel circuit 20 will be described by taking the example in which the source of the voltage holding transistor M6 in fig. 4 is connected to the reference power signal terminal Vref and all the transistors are P-type transistors. In this case, when the gate driving voltage of each transistor is at a low level, the transistor is turned on, the first power signal terminal ELVSS outputs a low level signal, the second power signal terminal ELVDD outputs a high level signal, and the reset signal vinitial is a low level signal.
First period t 1: the first scan signal Gate1 and the second emission control signal EM2 are at a low level, three transistors, i.e., the reset transistor M5, the voltage holding transistor M6 and the driving transistor M3 are turned on, a high-level signal output from the second power signal ELVDD is written into the drain of the voltage holding transistor M6, and a reset signal Vintial is written into the source of the reset transistor M5, so that the Gate voltage of the driving transistor M3 is initialized, and the driving voltage Vg and Vgs of the driving transistor M3 are Vintial and Vintial-ELVDD, so that any gray-scale picture lit by the pixel circuit 20 starts from the same bias state, and the short-term image retention problem can be improved.
Second period t 2: the second scan signal Gate2 and the first emission control signal EM1 are at a low level, three transistors, i.e., the compensation transistor M4, the data write transistor M7 and the driving transistor M3 are turned on, the data signal VData is written into the source of the data write transistor M7, and the high level signal output from the second power signal terminal ELVDD is written into the Gate of the driving transistor M3 until the driving voltage Vg of the driving transistor M3 becomes ELVDD + Vth.
Third period t 3: first emission control signal EM1 and second emission control signalThe EM2 is at a low level, the voltage holding transistor M6 is turned on, a high level signal output from the second power signal terminal ELVDD is written into the drain of the voltage holding transistor M6, the driving voltage Vg of the driving transistor M3 is changed to Vg + Vth + ELVDD-VData by coupling of the storage capacitor C, the first transistor M1, the second transistor M2, and the driving transistor M3 are simultaneously turned on to form a path, and the light emitting current flows through the light emitting module 201 to emit light. At this time, the light emission current is 1/2K (Vgs-Vth) × 2 1/2K (ELVDD-VData)2Wherein K is a coefficient. It can be seen that the shift of the threshold voltage Vth of the driving transistor M3 does not affect the magnitude of the light emission current, and the compensation of the threshold voltage Vth of the driving transistor M3 is realized.
When the source of the voltage holding transistor M6 is connected to the reference power supply signal terminal Vref, the operation principle of the pixel circuit 20 is the same as the above operation principle, and the main differences are: in the third period t3, the first emission control signal EM1 and the second emission control signal EM2 are at a low level, the voltage holding transistor M6 is turned on, a high level signal outputted from the reference power signal terminal Vref is written into the drain of the voltage holding transistor M6, the driving voltage Vg of the driving transistor M3 is changed to Vg ═ Vref + Vth + ELVDD-VData through the coupling of the storage capacitor C, the first transistor M1, the second transistor M2, and the driving transistor M3 are turned on at the same time, a path is formed, and the emission current flows through the light emitting module 201 to emit light. At this time, the light emission current is I-1/2K (Vgs-Vth) × 2-1/2K (Vref-VData)2Wherein K is a coefficient. It can be seen that the threshold voltage Vth of the driving transistor M3 does not affect the magnitude of the light emission current if it drifts, and the threshold voltage Vth of the driving transistor M3 is also compensated. Fig. 6 is a circuit diagram of another embodiment of the pixel circuit 20 shown in fig. 1. Compared to the gate of the first transistor M1 in fig. 4 receiving the first emission control signal EM1, the gate of the second transistor M2 receives the second emission control signal EM 2. The main difference is that the gate of the first transistor M1 in fig. 6 receives the second emission control signal EM2, and the gate of the second transistor M2 receives the first emission control signal EM 1. The driving timing of the pixel circuit 20 shown in fig. 6 is the same as the driving timing shown in fig. 5, and the detailed description is referred to above and is not repeated herein.
The display device of the embodiment of the application comprises the display circuit, and the display device comprises: a plurality of scan lines for providing scan signals; a plurality of data lines for supplying data signals; and the display circuits are electrically connected with the scanning lines and the data lines and are arranged in an array. The display device of the embodiment of the application comprises any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a navigator and the like.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (9)
1. A pixel circuit, comprising:
the light-emitting module is electrically connected with the first power signal end;
the light-emitting control module is electrically connected with the light-emitting module and used for controlling the light-emitting of the light-emitting module, the light-emitting control module comprises a first transistor and a second transistor, the first transistor and the second transistor are connected in series, the grid electrode of the first transistor is used for receiving a first light-emitting control signal, and the grid electrode of the second transistor is used for receiving a second light-emitting control signal; the drain electrode of the first transistor is connected with the source electrode of the second transistor, and the anode electrode of the light-emitting module is connected with the drain electrode of the second transistor; and
the driving control module is electrically connected with the light-emitting control module, and is used for receiving a first scanning signal and a second scanning signal, the first scanning signal and the first light-emitting control signal are in opposite phase, and the first scanning signal and the first light-emitting control signal are output from the same gate driving circuit; the second scanning signal and the second light-emitting control signal are in opposite phases and are output from the same gate driving circuit; the driving control module comprises a driving transistor, the source electrode of the driving transistor is connected with a second power supply signal end, and the drain electrode of the driving transistor is connected with the source electrode of the first transistor.
2. The pixel circuit according to claim 1, wherein: and the cathode of the light-emitting module is connected with the first power signal end.
3. The pixel circuit according to claim 1, wherein: the driving control module comprises a compensation transistor, wherein the grid electrode of the compensation transistor is used for receiving the second scanning signal, the source electrode of the compensation transistor is connected with the source electrode of the first transistor and the drain electrode of the driving transistor, the drain electrode of the compensation transistor is connected with the grid electrode of the driving transistor, and the compensation transistor is used for compensating the driving voltage of the driving transistor.
4. The pixel circuit according to claim 1, wherein: the drive control module comprises a reset transistor, the grid electrode of the reset transistor is used for receiving the first scanning signal, the source electrode of the reset transistor is connected with the grid electrode of the drive transistor, the drain electrode of the reset transistor is used for receiving the reset signal, and the reset transistor is used for resetting the drive voltage of the drive transistor.
5. The pixel circuit according to claim 1, wherein: the drive control module comprises a storage capacitor, a first polar plate of the storage capacitor is connected with the grid electrode of the drive transistor, and the storage capacitor is used for storing the drive voltage loaded to the drive transistor.
6. The pixel circuit according to claim 5, wherein: the driving control module comprises a voltage holding transistor, the source electrode of the voltage holding transistor is connected with the second power supply signal terminal or the reference power supply signal terminal, the grid electrode of the voltage holding transistor is used for receiving the second light-emitting control signal, the drain electrode of the voltage holding transistor is connected with the second plate of the storage capacitor, and the voltage holding transistor is used for providing stable driving voltage for the driving transistor when the voltage holding transistor is conducted;
and/or the drive control module comprises a data writing transistor, the grid electrode of the data writing transistor is used for receiving the second scanning signal, the drain electrode of the data writing transistor is used for receiving a data signal, the source electrode of the data writing transistor is connected to the second polar plate of the storage capacitor, and the data writing transistor is used for writing the data signal into the storage capacitor.
7. A display circuit, comprising:
a pixel circuit as claimed in any one of claims 1-6; and
and the grid driving circuit is connected with the pixel circuit and comprises a scanning signal generating module and an inverting circuit, wherein the scanning signal generating module is used for generating the first scanning signal and the second scanning signal, the inverting circuit is used for inverting the first scanning signal to generate the first light-emitting control signal and inverting the second scanning signal to generate the second light-emitting control signal.
8. The display circuit of claim 7, wherein: the gate driving circuit comprises a first gate driving circuit and a second gate driving circuit, the first gate driving circuit comprises a first scanning signal generating module and a first phase inverting circuit, the first scanning signal generating module is used for generating the first scanning signal, and the first phase inverting circuit is used for inverting the first scanning signal to generate the first lighting control signal; the second gate driving circuit comprises a second scanning signal generating module and a second inverter circuit, wherein the second scanning signal generating module is used for generating the second scanning signal, and the second inverter circuit is used for inverting the second scanning signal to generate the second light-emitting control signal.
9. A display device comprising the display circuit according to claim 7 or 8.
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| CN111524486A (en) * | 2020-06-04 | 2020-08-11 | 京东方科技集团股份有限公司 | Reset control signal generation circuit, method, module and display device |
| KR20220094916A (en) * | 2020-12-29 | 2022-07-06 | 엘지디스플레이 주식회사 | Gate driving circuit and electroluminescence display device using the same |
| CN113593476A (en) * | 2021-08-02 | 2021-11-02 | 武汉华星光电半导体显示技术有限公司 | Light-emitting control circuit and mobile terminal |
| CN113658553A (en) * | 2021-08-03 | 2021-11-16 | 武汉华星光电半导体显示技术有限公司 | Light-emitting control circuit and mobile terminal |
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| CN106782330A (en) * | 2016-12-20 | 2017-05-31 | 上海天马有机发光显示技术有限公司 | Organic light emissive pixels drive circuit, driving method and organic electroluminescence display panel |
| CN106558287A (en) * | 2017-01-25 | 2017-04-05 | 上海天马有机发光显示技术有限公司 | Organic light emissive pixels drive circuit, driving method and organic electroluminescence display panel |
| CN109493794A (en) * | 2019-01-24 | 2019-03-19 | 鄂尔多斯市源盛光电有限责任公司 | Pixel circuit, image element driving method and display device |
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