CN109858287A - The unclonable structure of a kind of physics based on interconnection line and from scrambling circuit structure - Google Patents
The unclonable structure of a kind of physics based on interconnection line and from scrambling circuit structure Download PDFInfo
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- CN109858287A CN109858287A CN201910079802.9A CN201910079802A CN109858287A CN 109858287 A CN109858287 A CN 109858287A CN 201910079802 A CN201910079802 A CN 201910079802A CN 109858287 A CN109858287 A CN 109858287A
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Abstract
The unclonable structure of of the invention a kind of physics based on interconnection line and from scrambling circuit structure, wherein the unclonable structure of physics is by linear shift register, interconnection network, load buffer array, and digital signature generator is constituted.The unclonable structure of a kind of physics based on interconnection line and from scrambling circuit structure, it is on the basis of the said structure, it further comprise that should be made of from scrambling circuit structure from scrambling circuit structure counter-type mask code generator, nonvolatile memory and circulation scrambling circuit.The invention has the advantages that: there is higher reliability, iPUF is not influenced by transistor ageing effect.The uniqueness of the digital signature of iPUF generation is improved from scrambling circuit structure, and should can be applied to other timing PUF from scrambling circuit.The rate that iPUF generates digital signature is high, and the area and power dissipation overhead of iPUF is smaller.In addition, the interconnecting construction in iPUF can place uncongested metal layer, it is not take up active device layer.
Description
Technical field
The purpose of the present invention is to provide a kind of unclonable structure of physics based on interconnection line and from scrambling circuit structure,
Especially the unclonable structure of the physics is uncertain using the manufacture in ic manufacturing process, generates tool for each chip
There is unique and randomness digital signature, is the important primitive of IC Hardware safety.It should can be used for from scrambling circuit
Promote the uniqueness of digital signature.Belong to microelectronics, technical field of integrated circuits.
Background technique
Integrated circuit (integrated circuit) is a kind of microelectronic device or component.It is through peroxidating, light
The semiconductor fabrication process such as quarter, diffusion, extension, evaporation of aluminum, constitute have certain function circuit needed for semiconductor, resistance,
The elements such as capacitor and the connecting wire between them are fully integrated on a fritter silicon wafer, and then welding is encapsulated in a shell
Electronic device；Wherein all elements have formed a whole in structure, make electronic component towards microminaturization, low-power consumption,
Major step has been strided forward in terms of intelligent and high reliability.Integrated circuit have it is small in size, light-weight, lead-out wire and pad are few,
The advantages that service life is long, high reliablity, and performance is good, at the same it is at low cost, convenient for large-scale production.Integrated circuit presses its function, structure
Difference, Analogous Integrated Electronic Circuits, digital integrated electronic circuit and D/A hydrid integrated circuit three categories can be divided into.
The unclonable structure of physics (Physical Unclonable Function, PUF) has become the integrated electricity of guarantee
The hardware primitive of road safety.Different from security key is stored in the method in nonvolatile memory, work as input signal
When, the unclonable structure of physics can generate dynamic digital signature or key unique, can not replicate for each chip.Object
It is uncertain using the manufacture in chip manufacturing proces to manage unclonable structure, generating has number unique and stability enough
Word signature.Based on above-mentioned characteristic, the unclonable structure of physics is widely used in inexpensive authentication and key generates.
The existing unclonable structure majority of physics is uncertain using the manufacture of active device, therefore will receive work temperature
Degree, power supply noise, the influence of aging effect, digital signature change, and stability reduces.In addition, existing physics can not
There is also potential security threat, such as modeling attacks for clonal structure.Therefore, for promoting the unclonable reliability of physics and peace
The method of full property is suggested.
By carrying out retrieval discovery to existing technical literature, Kan Xiao in 2007 et al. was in the 2014th year IEEE
International Symposium on Hardware-Oriented Security and Trust (HOST) (hardware peace
Entirely with credible meeting) on delivered " Bit selection algorithm suitable for high-volume
Production of sram-puf (method for stablizing position screening in extensive SRAM-PUF) ", proposes and passes through SRAM
Spatial coherence to the methods of all of SRAM-PUF progress stability sequences, however this method can not be applied to it is traditional
The unclonable structure of physics based on time delay.Achiranshu Garg et al. is in 2014 in IEEE International
" Design has been delivered on Symposium on Circuits and Systems (ISCAS) (international circuit and system of IMS conference)
of SRAM PUF with improved uniformity and reliability utilizing device aging
Effect (utilize device aging effect promoted SRAM-PUF uniformity and stability method) ", propose by device into
The pressure aging in two stages of row, the method for promoting the uniformity and stability of SRAM-PUF respectively, however required for difference PUF
Ageing time and aging configuration have differences, materially increase the testing cost of designer.MD.Tauhidur
Rahman et al. is in 2016 in IEEE Transactions on Emerging Topics in Computing (computer
Novel research theme periodical) on delivered " An Aging-Resistant RO-PUF for Reliable Key
Generation (the unclonable structure design of ageing-resistant physics generated for key) ", proposes the biasing when PUF does not work
Wherein the grid voltage of PMOS is supply voltage, and to reduce the NBTI aging effect that it is subject to, the method increase the stabilizations of PUF
Property, but designer is needed to carry out layout design.In conclusion although above-mentioned proposed improved method is able to solve physics not
Can clonal structure there are the problem of, however above-mentioned method for improving has application limitation, and Part Methods largely increase
Processing and the testing cost of designer are added.
Summary of the invention
To solve defect in the prior art, the purpose of the present invention is to provide a kind of physics based on interconnection line can not gram
Grand structure (iPUF), crosstalk signal on interconnection line caused by the unclonable structure of the physics is utilized because of interconnection line manufacture uncertainty
Uncertainty be that chip generates unique digital signature.It is moved in the designed unclonable structure of interconnection line physics using linear
Bit register generates excitation vector, and excitation vector inputs to interconnection network, two-way disturbed signal and number in interconnection network
Word signature generator is connected.Digital signature generator is made of basic digital device, for comparing the speed of two-way disturbed signal
It spends and generates digital signature.
Further, another object of the present invention is to provide one kind from scrambling circuit structure, to promote interconnection line physics
The uniqueness of the digital signature of unclonable structural generation.It should be from scrambling circuit structure to each chip digital signature generated
Step-by-step summation operation is carried out, the result of summation operation carries out the operation of circulation exclusive or as mask to original digital signature.
A kind of unclonable structure of physics based on interconnection line of the invention, by linear shift register, interconnection network,
Load buffer array, digital signature generator are constituted.In addition, there are also the work that control unit is used to control disparate modules.Its
The working method and principle of various pieces are as follows.
Linear shift register, the initial value (seed) using the pumping signal of input as linear shift register, passes through
Its input terminal will be returned to after not isotopic number exclusive or summation in linear shift register, so that linear shift register is each
The value of clock cycle changes, and its ordered series of numbers generated has certain randomness.The position λ in the linear shift register will
Excitation vector as interconnection network.
Interconnection network, interconnection network are made of λ item long interconnection line placed side by side, and two of them interconnection line is disturbed
Line, remaining λ -2 interconnection line is attack line, and every perturbed line two sides share (λ -2)/2 attack line.The input terminal of perturbed line
It is connected with control unit system clock, output end is connected with digital signature generator.The input terminal of attack line is posted with linear displacement
λ -2 output bits are connected in storage, excitation vector of the output of linear shift register as interconnection network.Due to interconnection line
Between there are coupled capacitor and coupling inductance, when excitation vector uploads sowing time in attack line, couple current will occur on perturbed line
And voltage, the final time for influencing the clock signal propagated along perturbed line and reaching digital signature generator.It is uncertain due to manufacturing
The presence of property, attack line has differences the effect size of perturbed line in each chip, and digital signature generator can generate not
Same signal.And manufacture is uncertain different to the response of each excitation vector, by the value and number that change excitation vector
The digital signature of different length can be generated in amount, iPUF.
Preferably, in order to make the manufacture uncertainty of interconnection line become the principal element of decision digital signature, to above-mentioned mutual
The structure of wire net improves, and keeps the signal propagated on the interfering line of two-way perturbed line adjacent position identical, i.e., will
The interfering line input terminal of two-way perturbed line two sides is respectively connected with, and makes it have identical pumping signal.At this point, two-way perturbed line
Excitation vector is identical, and the size of disturbed signal is mainly determined by manufacture uncertainty on perturbed line, i.e. the lines institute of overstriking in Fig. 3
Show connection.
Load buffer array, load buffer array are connected with the attack line in interconnection network, on the one hand make to attack
On the other hand line load having the same reduces the interference that the signal of attack line transmission generates other signals in circuit.
Digital signature generator, digital signature generator are made of two NAND gates.The output of two two input nand gates
It is coupled with the input of another NAND gate, the another way input terminal and the two-way perturbed line in interconnection network of two NAND gates
It is connected.When clock signal travels to digital signature generator along two-way perturbed line, the crosstalk signal of interconnection network makes two
The time that road clock signal reaches digital signature generator is different.When iPUF does not work, the output of digital signature generator is kept
Constant ' 1 '.If the rising edge of perturbed line 1 is ' 0 ' earlier than the rising edge of perturbed line 2, the output of digital signature generator, conversely,
Output is ' 1 '.In the failing edge of clock, digital signature generator is reset to original state ' 1 '.
Preferably, the unclonable structure of a kind of physics based on interconnection line and from scrambling circuit structure, is based on above-mentioned
It further comprise a kind of from scrambling circuit structure on the basis of the unclonable structure of the physics of interconnection line, it should be from scrambling circuit knot
Structure is by counter-type mask code generator, nonvolatile memory (already existing structure in chip, for storing each chip institute
The mask of generation), and circulation scrambling circuit composition.
Counter-type mask code generator, input terminal are the unclonable structure (iPUF) of the physics based on interconnection line
Output, counter-type mask code generator carries out summation operation to the original output of iPUF, the result of operation be stored in it is non-easily
In the property lost memory.
Nonvolatile memory is existing storage organization in circuit, for storing the generation of attribute mask code generator
Mask.When iPUF works, nonvolatile memory sends a mask to circulation scrambling circuit.
Scrambling circuit is recycled, has m register cycle to be connected and constitutes, there are two input selectors before each register,
For selecting data source.Before iPUF is exported every time, the value for recycling register in scrambling circuit is configured as non-volatile memories
The mask value stored in device when iPUF is exported, recycles the original figure label that each circulation in scrambling circuit is generated with iPUF
Famous prime minister's exclusive or, the value of exclusive or is as the digital signature after scrambling and output.
Preferably, the present invention further comprises control unit, controls the work of iPUF, raw for counter-type mask code generator
At enable signal, and the output process of control counter type mask code generator, the control signal of nonvolatile memory is generated, and
The data source of control loop scrambling circuit.
A kind of unclonable structure of physics based on interconnection line and the course of work from scrambling circuit: in task at the beginning of iPUF
When, external input pumping signal, as the seed of linear shift register, linear shift register runs n clock cycle, and
N excitation vector is generated for interconnection network, digital signature generator generates n original digital signatures.Counter-type mask is raw
It grows up to be a useful person and summation operation is carried out to n original digital signatures, generate unique mask for each chip, which is stored in non-
In volatile memory.When iPUF work, user's pumping signal different to iPUF, iPUF generates corresponding original figure
Signature, circulation scrambling circuit carry out step-by-step to original digital signature and mask and recycle exclusive or, the number after the scrambling of iPUF final output
Word signature.Digital signature after scrambling can be used as the key in cryptography.
The unclonable structure of of the invention a kind of physics based on interconnection line and from scrambling circuit, its production method include with
The following steps:
Step 1, iPUF circuit, from the circuit design and synthesis of scrambling circuit and control unit.Initial circuit design,
Comprehensive and netlist generates.Design, synthesis and the netlist generating process of initial integrated circuit are not influenced by iPUF；
Step 2, iPUF circuit and from scrambling circuit placement-and-routing.The placement-and-routing of iPUF circuit requires as follows: interconnection line
Interconnection line in network should be placed side by side, and require the spacing of different interconnection lines as small as possible, to increase the coupling between interconnection line
Effect.Distance of the load buffer array apart from different interconnection line terminals is approximately uniform, makes it have identical load.Number label
Two NAND gates in name generator are answered symmetrically placed, keep it identical apart from the distance of two-way perturbed line, to reduce wire length to letter
The influence of number time delay；
Step 3 carries out increment placement-and-routing to initial integrated circuit.The additional areas that the number of devices of iPUF occupies is opened
It sells smaller, the placement-and-routing of initial circuit is influenced smaller.
Step 4, flow.Test structure designed by the present invention is made of digital device, and flow process is integrated with general
Circuit flow process is consistent；
Step 5, test.The chip of convection rib carries out structural and functional test.Ensuring it, there is no manufacturing defect.
Step 6, iPUF initialization.The initial configuration to iPUF is completed, is generated for improving iPUF output uniqueness
Mask.Collect response signal of all chip iPUF under different excitation signal.
Step 7 authenticates in use.In integrated circuit use process, designer by iPUF input test motivate,
And the response signal for compareing its output whether there is the response signal collected in step 6, and if it exists, prove that the chip is to set
The credible chip of meter person design.
A kind of unclonable structure of physics based on interconnection line that the present invention designs and it is from scrambling circuit advantage:
1. compared to traditional PUF structure being made of active device, the system of passive device (interconnection line) is utilized in iPUF
Uncertainty is made, therefore there is higher reliability.IPUF not by transistor ageing effect (such as negative bias thermal instability,
Hot carrier injection effect and time correlation insulating layer punch-through effect) influence.Although interconnection line may be subjected to electronics and move
The influence of effect is moved, however because the runing time of iPUF is much smaller than the runing time of IC system, the degree of aging
Much smaller than the aging of normal circuit.
2. what is proposed effectively improves the uniqueness of the digital signature of iPUF generation from scrambling circuit structure, and should be certainly
Scrambling circuit can be applied to other timing PUF.
3. the rate that iPUF generates digital signature is high (per 1 bit of clock cycle), the area and power dissipation overhead of iPUF is smaller,
If the linear shift register in iPUF is K rank, iPUF can generate length less than 2KThe digital signature of -1 random length.
In addition, the interconnecting construction in iPUF can place uncongested metal layer, and it is not take up active device layer.
Detailed description of the invention
Fig. 1 is the unclonable structural circuit figure of interconnection line physics of the embodiment of the present invention 1.
Fig. 2 is the unclonable structural circuit figure of interconnection line physics of the embodiment of the present invention 2.
Fig. 3 is the embodiment of the present invention 3 from scrambling circuit structure chart.
Fig. 4 is that the interconnection line physics of the embodiment of the present invention 3 is unclonable and from scrambling circuit diagram showing the structure.
Fig. 5 is to promote schematic diagram to the unique of digital signature from scrambling circuit.
Fig. 6 is to input identical pumping signal to the 500 iPUF samplers generated in simulation process.
Fig. 7 is iPUF and from scrambling circuit production flow diagram.
Fig. 8 is the Hamming distance distribution map of digital signature after the original digital signature and scrambling that iPUF is generated.
Fig. 9 is temperature and when supply voltage changes, the stability of iPUF digital signature.
Figure 10 is the stability of iPUF digital signature after 1 year pressure aging of experience.
Symbol description is as follows in figure:
VDDnormal: chip normal power supply voltage；VDDmin: minimum voltage value in chip testing；VDDmax: chip is surveyed
Maximum supply voltage value in examination；tpnormal: the crucial path delay of time under normal power supply voltage；tpmin: critical path under maximum supply voltage
Diameter time delay；tpmax: crucial path delay of time pressure under minimum supply voltage；α: process-dependent constant；γ: critical path time delay is with power supply
Voltage change ratio；VTE0: the equivalent initial threshold voltage of circuit under test.
Specific embodiment
Below in conjunction with drawings and examples, the present invention is described in further detail.
HSPICE 2014 and IC is used for the software emulation of IC chip in following embodiment of the present invention
Compiler software.HSPICE be Synop company be IC design in steady-state analysis, transient analysis and frequency-domain analysis etc.
The sunykatuib analysis of circuit performance and the commercialization universal circuit simulation program developed.Its SPICE (1972 in Berkeley
Release), on the basis of the PSPICE of MicroSim company (releasing for 1984) and other circuit analysis softwares, and joined one
A little new functions can now be completed in direct current to the microwave frequency range for being higher than 100GHz by constantly improving to circuit
Make accurate emulation, analysis and optimization.In practical applications, HSPICE can provide critical breadboardin and design scheme.
IC Compiler is Synopsys next generation placement-and-routing system, by the way that physical synthesis is expanded to entire place and route mistake
Journey and the design closure of sign-off driving, to guarantee brilliant quality and shorten design time.Previous generation solution is due to cloth
Office, Clock Tree and wiring independent operating, there is its limitation.Extension physical synthesis (XPS) technological break-through of IC Compiler this
One limitation, extends to entire place and route process for physical synthesis.IC Compiler uses the unified shader based on TCL,
Realize several core technologies the most outstanding for innovating and being utilized Synopsys.Placement-and-routing as complete set designs
System, it includes all functions necessary to realizing next-generation design, as physical synthesis, layout, wiring, timing, signal are complete
Whole property (SI) optimization, low-power consumption, design for Measurability (DFT) and yield optimization.
Embodiment 1
As shown in Figure 1, the unclonable structure of the physics in interconnection line (iPUF) that the present invention designs, is deposited by linear displacement
Device, interconnection network, load buffer array, digital signature generator are constituted.
Linear shift register, the initial value (seed) using the pumping signal of input as linear shift register, passes through
Its input terminal will be returned to after not isotopic number exclusive or summation in linear shift register, so that linear shift register is each
The value of clock cycle changes, and its ordered series of numbers generated has certain randomness；The position λ in the linear shift register will
Excitation vector as interconnection network.
Linear shift register is a kind of general circuit structure, when inputting different seeds to linear shift register
When, it can generate the excitation vector that different bit wides is λ -2 in each clock cycle.λ is interconnection line in interconnection network
Number.In simulations, one 23 linear shift registers are utilized, proper polynomial is F (x)=x23+x22+x21+x20
+x19+x7, in addition, the linear shift register that the quasi- random sequence that bit wide is λ -2 arbitrarily can be generated all can be iPUF generation
Excitation vector.Designer can control the length of excitation vector and the characteristic of linear shift register.In addition, for general collection
At circuit, it is integrated with linear shift register in most of chip, in the item for the safety for guaranteeing linear shift register
The area and power dissipation overhead of iPUF can be further decreased under part with linear shift register existing in multiplex circuit.
Interconnection network, the uncertainty of crosstalk signal is each caused by iPUF is utilized because of interconnection line manufacture uncertainty
Chip generates digital signature；The effect of interconnection network is then the uncertainty for maximizing the crosstalk signal between interconnection line.Interconnection
Gauze network is made of λ item long interconnection line placed side by side, and two of them interconnection line is perturbed line, remaining λ -2 interconnection line is to attack
Line is hit, and every perturbed line two sides share (λ -2)/2 attack line.The input terminal of perturbed line and control unit system clock phase
Even, output end is connected with digital signature generator.The input terminal of attack line and λ -2 output bit phases in linear shift register
Even, excitation vector of the output of linear shift register as interconnection network.Due between interconnection line there are coupled capacitor and
Coupling inductance couple current and voltage will occur on perturbed line when excitation vector uploads sowing time in attack line, it is final influence along by
The clock signal for disturbing line propagation reaches the time of digital signature generator.Due to manufacturing probabilistic presence, in each chip
Attack line has differences the effect size of perturbed line, and digital signature generator can generate different signals.And manufacture is not true
The qualitative response to each excitation vector is different, and by changing the value and quantity of excitation vector, difference is can be generated in iPUF
The digital signature of length.Two perturbed lines are driven by clock, remaining attack line is driven by linear shift register.It is negative in order to reduce
The influence to crosstalk signal is carried, the terminal of two-way perturbed line is connected to the digital signature generator of symmetrical configuration.And attack line
Terminal is then connected with buffer array.Therefore, the crosstalk signal size on two-way perturbed line will be mainly by excitation vector and interconnection
The manufacture uncertainty of line determines.In addition, specific input vector should generate foot between two perturbed lines of different chips
Enough crosstalk signal is uncertain so that the digital signature that iPUF is generated has enough uniquenesses, and to all chips into
Row is distinguished.
Load buffer array, load buffer array are connected with the attack line terminal in interconnection network, on the one hand make
On the other hand attack line load having the same reduces the interference that the signal of attack line transmission generates other signals in circuit.
Digital signature generator, digital signature generator is the latch based on NAND gate, by two NAND gate groups
At.For the digital signature generator as speed comparison circuit, the clock signal that can compare along the transmission of two-way perturbed line reaches number
The speed of word signature generator.The output of two two input nand gates is coupled with the input of another NAND gate, two with it is non-
The another way input terminal of door is connected with the two-way perturbed line in interconnection network.When clock signal travels to number along two-way perturbed line
When word signature generator, the crosstalk signal of interconnection network makes two-way clock signal reach the time of digital signature generator not
Together.When iPUF does not work, digital signature generator exports ' 1 ' kept constant.If the rising edge of perturbed line 1 is earlier than perturbed line
2 rising edge, the output of digital signature generator is ' 0 ', conversely, output is ' 1 '.In the failing edge of clock, digital signature is generated
Device is reset to original state ' 1 '.Reset operation guarantees not related between two adjacent outputs.If linear in iPUF
Shift register is K rank, and for given input signal, random length is can be generated less than 2 in linear shift registerK- 1 swash
Vector is encouraged, random length then can be generated less than 2 in digital signature generatorK- 1 digital signature.
Embodiment 2
In the structure of embodiment 1 (Fig. 1), uncertain interconnection line manufacture is not the deciding factor for being digital signature.
The size of crosstalk signal also suffers from signal rising delay, fall delay, the influence of the factors such as leakage path charge and discharge, therefore,
Crosstalk signal is difficult to be predicted or clone, therefore the unclonable structure of the physics can take precautions against modeling attack.However due to interconnection
Adjacent interconnection line has shielding action, the crosstalk signal that adjacent interconnection line generates in disturbed signal to perturbed line in gauze network
The crosstalk signal size generated much larger than the attack line being spaced further apart with perturbed line.
In order to make the uncertain principal element for becoming decision digital signature of manufacture of interconnection line, to above-described embodiment 1
The structure of interconnection network improves, and keeps the signal propagated on the interfering line of two-way perturbed line adjacent position identical, i.e.,
The interfering line input terminal of two-way perturbed line two sides is respectively connected with, identical pumping signal is made it have.At this point, two-way perturbed line
Excitation vector it is identical, on perturbed line the size of disturbed signal mainly by manufacture uncertainty determine, i.e. the lines of overstriking in Fig. 2
Shown connection.
Embodiment 3
In order to promoted the unclonable structural generation of interconnection line physics digital signature uniqueness, the present invention provides
The unclonable structure of a kind of physics based on interconnection line and from scrambling circuit structure, being can not in the above-mentioned physics based on interconnection line
On the basis of clonal structure, one kind is further increased from scrambling circuit structure, as shown in figure 3, should be from scrambling circuit structure to every
A chip digital signature generated carries out step-by-step summation operation, and the result of summation operation is as mask to original digital signature
Carry out the operation of circulation exclusive or.It is described from scrambling circuit by counter-type mask code generator, nonvolatile memory is (in chip
Already existing structure, for storing each chip mask generated), and circulation scrambling circuit composition.
The counter-type mask code generator, input terminal are the unclonable structure of the physics based on interconnection line
(iPUF) output, counter-type mask code generator carry out summation operation to the original output of iPUF, and the result of operation is stored
In nonvolatile memory.
The nonvolatile memory is existing storage organization in circuit, for storing attribute mask code generator
The mask of generation.When iPUF works, nonvolatile memory sends a mask to circulation scrambling circuit.
The circulation scrambling circuit has m register cycle to be connected and constitutes, and has one two input choosing before each register
Device is selected, for selecting data source.Before iPUF is exported every time, the value of register is configured as non-volatile in circulation scrambling circuit
The mask value stored in memory when iPUF is exported, recycles the original number that each circulation in scrambling circuit is generated with iPUF
Word is signed different or, the value of exclusive or is as the digital signature after scrambling and output.The circulation scrambling circuit is by m head and the tail phase
Trigger even is constituted, and the mask of each chip is stored in the m trigger, which moves to right in each clock cycle, each
Position successively carries out xor operation with the corresponding position in original digital signature, and the result of operation is equivalent to every m original digital signature
With m bitmask exclusive or one by one, the output is as the digital signature after scrambling.In iPUF use process, control unit first will
Mask in nonvolatile memory is loaded into setting out wherein in circulation scrambling circuit, when iPUF generates digital signature, follows
Ring scrambling circuit carries out xor operation to Ruan Shi digital signature.The digital signature that different chip iPUF are generated can be improved in the operation
Uniqueness, to distinguish all chips.
Further, the present embodiment further includes control unit, and in iPUF configuration phase, control unit receives external iPUF
The work of output gate clock control iPUF after enable signal, while enable signal, control are generated for counter-type mask code generator
Counter-type mask code generator processed generates mask, and then, control unit, which generates the access address of nonvolatile memory and writes, to be made
Energy signal, mask is stored in nonvolatile memory.In iPUF authentication phase, control unit generates nonvolatile memory
Access address and read enable signal, using mask selection signal by mask be loaded into circulation scrambling circuit in, then, starting
IPUF makes to recycle scrambling circuit to the iPUF original digital signature generated and mask progress exclusive or behaviour using mask selection signal
Make.
Shown in Figure 4, the present embodiment is electric for the unclonable structure of physics (iPUF) based on interconnection line and from scrambling
Road, wherein nonvolatile memory is existing structure in circuit, remaining six part can be embedded in existing ic core on piece.
It is shown in Figure 4, in the iPUF course of work, kind of user's input signal as linear shift register
Son, linear shift register output drive sequence vector, the input as interconnection network.Above-mentioned excitation vector is along interconnection line
λ -2 attack lines in network (interconnection network is made of λ Parallel interconnection line) are propagated.The signal propagated on attack line will
Crosstalk signal is generated on 2 perturbed lines, and the size of crosstalk signal is activated that the manufacture of vector sum interconnection line is probabilistic
It influences.Digital signature generator can compare speed (and the crosstalk signal of the arrival time for the two paths of signals propagated along perturbed line
Size), and generate ' 0/1 ' sequence.Counter-type mask code generator is every according to the original digital signature that each chip generates
A chip generates unique mask, the original number that circulation scrambling circuit utilizes the unique mask of each chip to generate each chip
Word signature carries out xor operation, to improve the uniqueness of the digital signature of different chips.
As shown in figure 5, the unique principle that circulation scrambling circuit promotes digital signature is as follows: assuming that the position of two chips
Width be m mask in there are p difference, the bit wide of two chips be in the original digital signature of n there are q be difference, n-q phases
Together.By carrying out xor operation to original digital signature using mask, in original digital signaturePosition output will be by
To influence, in these affected output bits, whereinPosition will have identical value to overturn for different values, make
The unique of iPUF is obtained to improve.On the other hand, in affected position, will haveIt is turned over from by original different value position
Switch to identical value, so that the unique of iPUF reduces.Therefore, shown in the unique result such as formula (1) promoted.
For the case where difference position q/n < 0.5, circulation adds in two whole digital signature it can be seen from formula (1)
Disturb the effect that circuit is improved to uniqueness.For iPUF, the uniqueness of digital signature is most of less than 50%.This
Outside, the uniqueness of original digital signature is smaller, and circulation scrambling circuit is more obvious unique promotion effect.It is worth mentioning
It is that the unstable potential drop of in mask causes the output after scrambling that the 1/m bit error rate occurs, eventually leads to the stability drop of iPUF
It is low.For this purpose, the value of mask needs to be stored in the Verification System outside nonvolatile memory or chip.
It is imitated the following are the unclonable structure of the physics based on interconnection line designed using the present invention and from scrambling circuit
Very with test:
It is tested using 2014 software of HSPICE, which is emulated using 28nm technology library, and utilizes VCS pairs
Test macro carries out functional emulation.There is manufacture not using the Monte Carlo simulation method validation test circuit in Hspice
Measuring accuracy under certainty, the standard configuration and manufacture of interconnection line are uncertain as shown in table 1 in test.According to shown in table 1
Uncertainty, generates 500iPUF sample, and the working frequency of iPUF is 125MHz.The type of device used in digital signature generator
Number be NAND2X4_LVT.In simulation process, had input to the linear shift register in 500 iPUF samples identical sharp
Signal is encouraged, as shown in Figure 6.The supply voltage of iPUF is 1.05V, and operating temperature is 25 DEG C, and the length of digital signature is 1024.Its
In, W is grid width, and L is grid length, VThFor the threshold voltage of metal-oxide-semiconductor.
IPUF standard design standard and manufacture are uncertain:
Table 1
Some standards are inserted by the physics based on the interconnection line unclonable structure of the invention designed and from scrambling circuit
Test circuit (ITC benchmark) and 64 in open source SPARC processor (OpenSPARCT2 SPARCT core) core
Floating-point and graphic element.
Firstly, carrying out RTL design, synthesis using circuit of the eda software to insertion iPUF.By applying IC Compiler
The domain that software is laid out wiring to iPUF, carries out increment placement-and-routing to ifq circuit, ultimately generates circuit.It obtains and is based on
The unclonable structure of the physics of interconnection line and the gross area and power dissipation overhead occupied after being inserted into reference circuit from scrambling circuit, such as
Shown in table 2.Because the interconnection line network in iPUF can be placed on not crowded metal layer, the significant area expense of iPUF
From linear shift register and from the area of scrambling circuit.Linear shift register bit wide in experiment in iPUF is 23,
Mask bit wide is 10 (corresponding to from the flip flop number in scrambling circuit is 10).There is in table 2 the area overhead range as it can be seen that iPUF
For 0.08%-1.86%.
On piece critical path latency measurement system accounts for circuit significant area overhead ratio:
| Standard testing circuit | b19 | FGU | Leon3s | S35932 | VGA-LCD |
| Area overhead (%) | 0.19 | 0.08 | 0.15 | 1.86 | 0.16 |
Table 2
Next, carrying out unique analysis to the digital signature that 500 iPUF are generated.The unique calculating side of digital signature
Method is to input identical pumping signal to all iPUF, all iPUF generate the average value of Hamming distance between digital signature.Figure
The distribution map of digital signature uniqueness after 8 original digital signatures and scrambling generated for iPUF, using from scrambling circuit, iPUF is raw
Unique at digital signature is promoted to 48.63%.Fig. 9 is when temperature and supply voltage change, and iPUF generates number
The stability of word signature is respectively 99.06% and 96.09%.Figure 10 is the stability of iPUF after undergoing 1 year pressure aging, number
The ratio for the position being flipped in word signature is 0.36%.
As shown in fig. 7, the unclonable structure of of the invention a kind of physics based on interconnection line and from scrambling circuit, its production
Method includes with the following steps:
Step 1, iPUF circuit, from the circuit design and synthesis of scrambling circuit and control unit.Initial circuit design,
Comprehensive and netlist generates.Design, synthesis and the netlist generating process of initial integrated circuit are not influenced by iPUF；
Step 2, iPUF circuit and from scrambling circuit placement-and-routing.The placement-and-routing of iPUF circuit requires as follows: interconnection line
Interconnection line in network should be placed side by side, and require the spacing of different interconnection lines as small as possible, to increase the coupling between interconnection line
Effect.Distance of the load buffer array apart from different interconnection line terminals is approximately uniform, makes it have identical load.Number label
Two NAND gates in name generator are answered symmetrically placed, keep it identical apart from the distance of two-way perturbed line, to reduce wire length to letter
The influence of number time delay；
Step 3 carries out increment placement-and-routing to initial integrated circuit.The additional areas that the number of devices of iPUF occupies is opened
It sells smaller, the placement-and-routing of initial circuit is influenced smaller.
Step 4, flow.Test structure designed by the present invention is made of digital device, and flow process is integrated with general
Circuit flow process is consistent；
Step 5, test.The chip of convection rib carries out structural and functional test.Ensuring it, there is no manufacturing defect.
Step 6, iPUF initialization.The initial configuration to iPUF is completed, is generated for improving iPUF output uniqueness
Mask.Collect response signal of all chip iPUF under different excitation signal.
Step 7 authenticates in use.In integrated circuit use process, designer by iPUF input test motivate,
And the response signal for compareing its output whether there is the response signal collected in step 6, and if it exists, prove that the chip is to set
The credible chip of meter person design.
Claims (6)
1. a kind of unclonable structure of physics based on interconnection line, it is characterised in that: the structure is by linear shift register, interconnection
Gauze network, load buffer array, digital signature generator are constituted；
The linear shift register, using the pumping signal of input as the initial value of linear shift register, by by line
Property shift register in not isotopic number exclusive or summation after return to its input terminal so that linear shift register is in each clock
The value in period changes, and its ordered series of numbers generated has certain randomness；The position λ in the linear shift register is by conduct
The excitation vector of interconnection network；
The interconnection network, interconnection network are made of λ item long interconnection line placed side by side, two of them interconnection line be by
Line is disturbed, remaining λ -2 interconnection line is attack line, and every perturbed line two sides share (λ -2)/2 attack line；The input of perturbed line
End is connected with system clock, and output end is connected with digital signature generator；In the input terminal and linear shift register of attack line
λ -2 output bits are connected, excitation vector of the output of linear shift register as interconnection network；Due to being deposited between interconnection line
In coupled capacitor and coupling inductance, when excitation vector uploads sowing time in attack line, couple current and voltage will occur on perturbed line,
The final time for influencing the clock signal propagated along perturbed line and reaching digital signature generator；Due to manufacturing probabilistic deposit
Attack line has differences the effect size of perturbed line in each chip, and digital signature generator can generate different letters
Number；And manufacture is uncertain different to the response of each excitation vector, by changing the value and quantity of excitation vector, iPUF
The digital signature of different length can be generated；
The load buffer array, load buffer array are connected with the attack line in interconnection network, on the one hand make to attack
Line load having the same is hit, the interference that the signal of attack line transmission generates other signals in circuit is on the other hand reduced；
The digital signature generator, digital signature generator are made of two NAND gates；Two two input nand gates it is defeated
It is coupled with the input of another NAND gate out, the another way input terminal and the two-way in interconnection network of two NAND gates are disturbed
Line is connected；When clock signal travels to digital signature generator along two-way perturbed line, the crosstalk signal of interconnection network makes
The time that two-way clock signal reaches digital signature generator is different；When iPUF does not work, the output of digital signature generator is protected
Hold constant ' 1 '；If the rising edge of perturbed line 1 is ' 0 ' earlier than the rising edge of perturbed line 2, the output of digital signature generator, instead
It, exporting is ' 1 '；In the failing edge of clock, digital signature generator is reset to original state ' 1 '.
2. the unclonable structure of a kind of physics based on interconnection line according to claim 1, it is characterised in that: to make to interconnect
The manufacture of line is uncertain to become the principal element for determining digital signature, improves, makes to the structure of the interconnection network
The signal propagated on the interfering line of two-way perturbed line adjacent position is identical, i.e., inputs the interfering line of two-way perturbed line two sides
End is respectively connected with, and makes it have identical pumping signal；At this point, the excitation vector of two-way perturbed line is identical, it is disturbed on perturbed line
The size of signal is mainly determined by manufacture uncertainty.
3. the unclonable structure of a kind of physics based on interconnection line and from scrambling circuit structure, be the physics based on interconnection line not
It can further increase a kind of from scrambling circuit structure on the basis of clonal structure, it is characterised in that: described based on interconnection line
The unclonable structure of physics is by linear shift register, interconnection network, load buffer array, digital signature generator structure
At；Described by counter-type mask code generator, nonvolatile memory and recycles scrambling circuit structure from scrambling circuit structure
At；
Counter-type mask code generator, input terminal are the output of the unclonable structure of the physics based on interconnection line, meter
Number type mask code generator carries out summation operation to the original output of iPUF, and the result of operation is stored in nonvolatile memory
In；
Nonvolatile memory is existing storage organization in circuit, for storing the mask of attribute mask code generator generation；
When iPUF works, nonvolatile memory sends a mask to circulation scrambling circuit；
Scrambling circuit is recycled, has m register cycle to be connected and constitutes, there are two input selectors before each register, be used for
Select data source；Before iPUF is exported every time, the value for recycling register in scrambling circuit is configured as in nonvolatile memory
The mask value of storage, when iPUF is exported, each recycled in scrambling circuit recycles the original digital signature phase generated with iPUF
Exclusive or, the value of exclusive or is as the digital signature after scrambling and output.
4. the unclonable structure of a kind of physics based on interconnection line according to claim 3 and from scrambling circuit structure,
It is characterized in that: further comprising control unit, control the work of iPUF, generate enable signal for counter-type mask code generator,
And the output process of control counter type mask code generator, the control signal of nonvolatile memory is generated, and control loop adds
Disturb the data source of circuit.
5. a kind of unclonable structure of physics based on interconnection line and the course of work from scrambling circuit, specifically: at the beginning of iPUF
When task, external input pumping signal, as the seed of linear shift register, linear shift register runs n clock
Period, and n excitation vector is generated for interconnection network, digital signature generator generates n original digital signatures；Counter-type
Mask code generator carries out summation operation to n original digital signatures, generates unique mask for each chip, which is deposited
It is stored in nonvolatile memory；When iPUF work, user's pumping signal different to iPUF, iPUF generates corresponding original
Beginning digital signature, circulation scrambling circuit carry out step-by-step to original digital signature and mask and recycle exclusive or, the scrambling of iPUF final output
Digital signature afterwards；Digital signature after scrambling can be used as the key in cryptography.
6. a kind of unclonable structure of physics based on interconnection line and the production method from scrambling circuit, including with the following steps:
Step 1, iPUF circuit, from the circuit design and synthesis of scrambling circuit and control unit；Initial circuit design, synthesis
And netlist generates；Design, synthesis and the netlist generating process of initial integrated circuit are not influenced by iPUF；
Step 2, iPUF circuit and from scrambling circuit placement-and-routing
The placement-and-routing of iPUF circuit requires as follows: the interconnection line in interconnection network should be placed side by side, and require different interconnection
The spacing of line is as small as possible, to increase the coupling between interconnection line；Load buffer array is apart from different interconnection line terminals
Apart from approximately uniform, identical load is made it have；Two NAND gates in digital signature generator answer it is symmetrically placed, make its away from
It is identical with a distance from two-way perturbed line, to reduce influence of the wire length to signal time delay；
Step 3 carries out increment placement-and-routing to initial integrated circuit；
Step 4, flow；
The chip of step 5, convection rib carries out structural and functional test, it is ensured that manufacturing defect is not present in it；
Step 6, iPUF initialization
The initial configuration to iPUF is completed, is generated for improving the unique mask of iPUF output；Collect all chip iPUF
Response signal under different excitation signal；
Step 7 authenticates in use
In integrated circuit use process, designer compares the response signal of its output by motivating to iPUF input test
With the presence or absence of the response signal collected in step 6, and if it exists, prove the credible chip that the chip designs for designer.
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