CN109842182B

CN109842182B - Power supply system

Info

Publication number: CN109842182B
Application number: CN201910135525.9A
Authority: CN
Inventors: 叶忠
Original assignee: Inventchip Technology Co Ltd
Current assignee: Inventchip Technology Co Ltd
Priority date: 2019-01-08
Filing date: 2019-02-22
Publication date: 2020-12-04
Anticipated expiration: 2039-02-22
Also published as: CN109842182A

Abstract

The present disclosure relates to a power supply system, the system comprising: the power factor converter PFC of the current source, connect electrically to the external power, is used for receiving the electric energy of the external power, and output the transformation current and transformation voltage according to the power needed; the adjustable gain converter is electrically connected with the current source PFC and the load, and is used for receiving the load voltage of the load, adjusting the gain of the adjustable gain converter by using the load voltage, outputting the power supply voltage by using the conversion voltage and the gain, and outputting the power supply current by using the conversion current and the gain; and the feedback controller is electrically connected with the load and the current source PFC and used for receiving the load current and the target current flowing through the load and adjusting the conversion current according to the load current and the target current. Through the system, the conversion current can be controlled, the conversion voltage can be clamped in a set range, and the power supply system can work efficiently in a wide output voltage range with constant power.

Description

Power supply system

Technical Field

The present disclosure relates to power supply technologies, and particularly to a power supply system.

Background

As is well known, as new energy is developed and applied, battery charging technology becomes a key element restricting the development of new energy, and an Electric Vehicle (EV) is one of the most important new energy applications, and different EVs are equipped with batteries of different capacities and voltages. Batteries of EVs have different voltage levels, for example, small passenger cars typically use low voltage batteries, while buses typically use high voltage batteries. The battery voltage may swing between a wide range of deep discharge states to full charge states (e.g., the voltage range may be from 330V to 750V). In order to reduce the battery charging time of the charging device, the charging device of the charging station needs to operate in a constant power mode over the full voltage range, which can become very expensive and bulky if the requirements have to be met.

In the related art, most PFC topologies used are vienna three-phase boost converters, and the DC/DC stages are LLC and phase-shift converters. And the PFC and DC/DC stages are independently controlled, which requires large DC capacitors and does not achieve all the advantages at the system level. Furthermore, the DC/DC stage must operate at a very low duty cycle at low voltage outputs, or the switching frequency of the LLC converter is increased substantially. These methods increase power consumption at low voltage output. To address this problem, some solutions use high power relays to mechanically switch winding connections to accommodate a wide output voltage range, but obviously it adds cost and takes up a lot of space.

Therefore, it is urgently needed to provide a new technical solution, which can implement constant power high-efficiency power conversion in a wide voltage range on the aspect of topology and system.

Disclosure of Invention

In view of this, the present disclosure proposes a power supply system, the system comprising:

the power factor converter PFC of the current source, connect electrically to the external power, is used for receiving the electric energy of the said external power, and output the conversion current and transformation voltage according to the power needed;

the adjustable gain converter is electrically connected with the current source PFC and the load, and is used for receiving the load voltage of the load, adjusting the gain of the adjustable gain converter by using the load voltage, outputting the power supply voltage by using the conversion voltage and the gain, and outputting the power supply current by using the conversion current and the gain;

and the feedback controller is electrically connected with the load and the current source PFC and used for receiving the load current and the target current flowing through the load and adjusting the conversion current according to the load current and the target current.

In one possible embodiment, the adjustable gain converter includes a first full bridge circuit, a second full bridge circuit, a first secondary circuit and a second secondary circuit, the first full bridge circuit is connected in series to the second full bridge circuit, the first secondary circuit is coupled to the first full bridge circuit, the second secondary circuit is coupled to the second full bridge circuit, and the gain of the adjustable gain converter is adjusted by changing a phase shift between the first full bridge circuit and the second full bridge circuit.

In one possible implementation, the first full bridge circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a first primary winding, a first end of the first transistor is electrically connected to an output terminal of the current source PFC and a first end of the third transistor, a second end of the first transistor is electrically connected to a first end of the second transistor and a first end of the first primary winding, a second end of the third transistor is electrically connected to a first end of the fourth transistor and a second end of the first primary winding, and a second end of the second transistor is electrically connected to a second end of the fourth transistor.

In a possible implementation manner, the second full-bridge circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second primary winding, a first end of the fifth transistor is electrically connected to the first end of the seventh transistor, a second end of the fifth transistor is electrically connected to the first end of the sixth transistor and the first end of the second primary winding, a second end of the second primary winding is electrically connected to the second end of the seventh transistor and the first end of the eighth transistor, and a second end of the sixth transistor is electrically connected to the other output terminal of the current source PFC and the second end of the eighth transistor.

In one possible embodiment, the first secondary circuit comprises a first rectifier circuit and a second rectifier circuit, and the second secondary circuit comprises a third rectifier circuit and a fourth rectifier circuit, wherein:

the first rectifying circuit is used for positive half-wave rectification of the first full-bridge circuit;

the second rectifying circuit is used for negative half-wave rectification of the first full-bridge circuit;

the third rectifying circuit is used for positive half-wave rectification of the second full-bridge circuit;

the fourth rectifying circuit is used for negative half-wave rectification of the second full-bridge circuit.

In one possible embodiment, the first secondary circuit includes a first secondary winding, a first diode, and a second diode, the second secondary circuit includes a second secondary winding, a third diode, and a fourth diode, the first secondary circuit and the second secondary circuit both include a fifth diode and a sixth diode, the first rectifying circuit includes the first diode and the fifth diode, the second rectifying circuit includes the second diode and the sixth diode, the third rectifying circuit includes the third diode and the fifth diode, and the fourth rectifying circuit includes the fourth diode and the sixth diode, wherein:

the first end of the first secondary winding is electrically connected to the anode of the first diode and the cathode of the second diode, and the cathode of the first diode is electrically connected to the cathode of the third diode and the cathode of the fifth diode; the anode of the third diode is electrically connected to the first end of the second secondary winding and the cathode of the fourth diode; the second end of the second secondary winding is electrically connected to the second end of the first secondary winding, the anode of the fifth diode and the cathode of the sixth diode, and the anode of the fourth diode is electrically connected to the anode of the second diode and the anode of the sixth diode.

In a possible embodiment, the first and third rectifier circuits are configured as two interleaved power rectifiers, and/or

The second and fourth rectifier circuits are configured as two interleaved power rectifiers.

In one possible implementation, the first secondary circuit and the second secondary circuit further include a first inductor and a second inductor in common, where:

a first end of the first inductor is electrically connected to a cathode of the first diode, a cathode of the third diode and a cathode of the fifth diode, and a first end of the second inductor is electrically connected to an anode of the sixth diode, an anode of the second diode and an anode of the fourth diode; the second end of the first inductor and the second end of the second inductor are used for outputting the power supply voltage and the power supply current.

In a possible implementation manner, the adjustable gain converter further includes a first capacitor and a second capacitor, a first end of the first capacitor is electrically connected to the second end of the first inductor, and a second end of the first capacitor is electrically connected to the first end of the second capacitor, the second end of the first secondary winding, and the second end of the second secondary winding; the second end of the second capacitor is electrically connected to the second end of the second inductor.

In one possible embodiment, the gain is adjusted by adjusting a phase shift of the first full-bridge circuit and the second full-bridge circuit or by pulse width modulation, PWM, when the duty cycle of the first full-bridge circuit and/or the second full-bridge circuit is less than or equal to 50%.

In one possible embodiment, the gain is adjusted by adjusting the phase shift between the first full-bridge circuit and the second full-bridge circuit when the duty cycle of the first full-bridge circuit and/or the second full-bridge circuit is equal to 50%.

In one possible embodiment, the adjusting the gain by adjusting a phase shift between the first full-bridge circuit and the second full-bridge circuit comprises:

the phase shift is determined by the following equation:

β is 180 ° ((Vo-V1)/(V2-V1)), where β represents the magnitude of the phase shift, Vo represents the load voltage, V1 represents the minimum value of the load voltage, and V2 represents the maximum value of the load voltage.

In one possible embodiment, the adjustable gain converter further comprises: the first end of the third capacitor is electrically connected to one end of the current source PFC, the second end of the third capacitor is electrically connected to the first end of the fourth capacitor and a connection point of the first full-bridge circuit and the second full-bridge circuit, and the second end of the fourth capacitor is electrically connected to the other end of the current source PFC.

In one possible implementation, the feedback controller includes an operational amplifier and a current loop compensator,

the first end of the operational amplifier is used for receiving the load current, and the second end of the operational amplifier is used for receiving the target current;

the current loop compensator is electrically connected to the first end and the output end of the operational amplifier, and is configured to adjust the conversion current output by the current source PFC according to a comparison result between the load current output by the operational amplifier and the target current to adjust the supply current.

According to another aspect of the present disclosure, a charging device is provided, which includes the power supply system.

The method realizes the series and parallel connection of the outputs of the two open-loop converters of the adjustable gain converter and the stepless regulation of the output voltage through phase shift control. According to the power supply system architecture and the novel adjustable gain converter topology disclosed by the invention, the power density of the converter can be greatly improved, the magnetic element is fully utilized, the current pressure of a semiconductor device is reduced, and the good power conversion efficiency can be kept in a wide output voltage range.

Through the system, the conversion current output by the current source PFC can be controlled according to the target current required by the load, and the gain of the adjustable gain converter can be adjusted according to the load voltage so that the conversion voltage output by the current source PFC can be clamped in a set range, so that the power supply system can work efficiently in a wide output voltage range with constant power.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic diagram of a power supply system according to an embodiment of the present disclosure.

Fig. 2a shows a schematic diagram of a current source PFC and an adjustable gain converter according to an embodiment of the present disclosure.

Fig. 2b shows a further schematic diagram of a current source PFC and an adjustable gain converter according to an embodiment of the present disclosure.

Fig. 3 shows waveforms of three-phase voltage input, three-phase current, and converted current output by the current source PFC of the external power supply according to an embodiment of the present disclosure.

Fig. 4 shows a diagram of a phase-supply voltage-converted voltage correspondence according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of an adjustable gain converter according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of various waveforms in an adjustable gain converter according to an embodiment of the present disclosure.

Fig. 7a shows a schematic diagram of a first full-bridge circuit and a first secondary circuit according to an embodiment of the present disclosure, and fig. 7b shows a control schematic diagram of the first full-bridge circuit according to an embodiment of the present disclosure.

Fig. 8a shows a control schematic diagram when the duty cycle of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B is less than or equal to 50% when the gain of the adjustable gain converter 20 is less than or equal to 0.5 according to an embodiment of the present disclosure, and fig. 8B shows a Phase shift control schematic diagram of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B when the gain of the adjustable gain converter 20 is greater than or equal to 0.5 according to an embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of the control signals for the various transistors between gains 0-1 of the adjustable gain converter.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a power supply system according to an embodiment of the disclosure.

As shown in fig. 1, the system includes:

the power factor converter PFC10 of the current source, connect electrically to external power supply 50, is used for receiving the electric energy of the said external power supply 50, and output and vary current and vary voltage according to the power needed;

an adjustable gain converter 20 electrically connected to the current source PFC10 and the load 40, for receiving a load voltage of the load 40, and adjusting a gain of the adjustable gain converter 20 by using the load voltage, so as to output a supply voltage by using the conversion voltage and the gain, and output a supply current by using the conversion current and the gain;

and a feedback controller 30 electrically connected to the load 40 and the current source PFC10, for receiving a load current and a target current flowing through the load 40, and adjusting the switching current according to the load current and the target current. .

In one possible embodiment, the external power source 50 may be an ac power source, which may be a three-phase input. In other embodiments, the external power source 50 may be a dc power source, or other suitable power source, which is not limited by this disclosure.

In one possible embodiment, the load 40 may be a battery pack of the electric vehicle EV, or may be a battery pack of other equipment or devices.

In one possible embodiment, the gain may be equivalent to a transformer transformation ratio (turn ratio).

In one possible embodiment, the feedback controller 30 may include an operational amplifier 32 and a current loop compensator 31,

a first terminal of the operational amplifier 32 is configured to receive the load current, and a second terminal of the operational amplifier is configured to receive a target current;

the current loop compensator 31 is electrically connected to the first end and the output end of the operational amplifier 32, and is configured to control the current source power factor converter PFC10 to adjust the conversion current after being compensated by the current loop compensator 31 according to the comparison result of the operational amplifier 32 on the load current and the target current.

In a possible implementation, the operational amplifier 32 and the current loop compensator 31 included in the feedback controller 30 may be implemented by digital circuits or digital operations.

In one possible embodiment, the target current may be a reference current or a current command that the load 40 needs to be charged.

For example, when the load current is less than the target current, the current loop compensator may increase the value of the switching current so that the output supply current gradually approaches the target current. When the load current is larger than the target current, the current loop compensator can also perform reduction processing on the conversion current, so that the output supply circuit is gradually reduced to be close to the target current.

The current loop compensator 31 can be designed according to practical situations, and the specific structure of the current loop compensator 31 is not limited by the present disclosure.

It is to be understood that the above description is illustrative, and is not to be construed as limiting the present disclosure.

Referring to fig. 2a, fig. 2a is a schematic diagram illustrating a current source PFC and an adjustable gain converter according to an embodiment of the present disclosure.

As shown in fig. 2a, when the input power is three-phase ac power, the current source PFC10 may include inductors LA, LB and LC, and transistors Q1-Q6, wherein one end of the inductor LA receives the a-phase ac power, and the other end of the inductor LA is electrically connected to the source of the transistor Q1 and the drain of the transistor Q2. One end of the inductor LB receives the phase-B alternating current, and the other end of the inductor LB is electrically connected to the source of the transistor Q3 and the drain of the transistor Q4. One end of the inductor LC receives the C-phase alternating current, and the other end of the inductor LC is electrically connected to the source of the transistor Q5 and the drain of the transistor Q6. The drains of the transistors Q1, Q3 and Q5 are electrically connected, the sources of the transistors Q2, Q4 and Q6 are grounded, and the gates of the transistors Q1-Q6 are used for receiving control signals and are turned on or off according to the control signals to adjust the electric energy.

In one possible embodiment, the current source PFC10 may be configured to boost (boost) the input ac power, for example, when the input ac power is three-phase 380V, the current source PFC10 may boost the ac power from 380V to 660V (Vbus voltage) or other voltage values.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating waveforms of a three-phase voltage input, a three-phase current input, and a conversion current output by the current source PFC of the external power source 50 according to an embodiment of the disclosure.

As shown in fig. 3, the horizontal axis of fig. 3 may represent time intervals, and the three vertical axes represent, from top to bottom, three-phase voltage inputs, three-phase currents, and output conversion currents, respectively.

As shown in fig. 3, voltage Va and current ia of phase a change in phase, voltage Vb and current ib of phase b change in phase, and voltage Vc and current ic of phase c change in phase. The converted current output by the current source PFC10 has a very small ripple, the ripple of the converted current is less than 10% of the average current, and the ripple frequency is 6 times the frequency of the input alternating current.

For example, the frequency of the alternating current input by the external power source may be between 50Hz and 60Hz, and correspondingly, the frequency of the ripple wave may be between 300Hz and 360 Hz. Since the battery pack of the load has a characteristic of a large capacitance, the battery pack can be charged at a current having a frequency of several hundred Hz and a small amplitude ripple (e.g., less than 10%). Also, in some possible embodiments, a smaller capacitor may be used for filtering, and compared to the related art in which a large capacitor (electrolytic capacitor) is used for filtering, the present disclosure may greatly save space, thereby optimizing the circuit structure and reducing the cost, which will be described later.

It should be understood that the above description of the current source PFC10 is exemplary, and the current source PFC may have other circuit configurations, such as vienna three-phase PFC, etc., and the disclosure is not limited thereto.

With continued reference to fig. 2a, in one possible embodiment, the adjustable gain converter 20 may include a first full-bridge circuit Phase a, a second full-bridge circuit Phase B, a first secondary circuit and a second secondary circuit, the first full-bridge circuit Phase a is connected in series with the second full-bridge circuit Phase B, the first secondary circuit is coupled to the first full-bridge circuit, the second secondary circuit is coupled to the second full-bridge circuit, and the gain of the adjustable gain converter 20 is adjusted by changing the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B. .

In one possible implementation, the first secondary circuit is coupled to the first full-bridge circuit Phase a, and at this time, the first secondary circuit and the first full-bridge circuit Phase a may be regarded as a dc transformer. Similarly, the second secondary circuit is coupled to the second full-bridge circuit Phase B, and the second secondary circuit and the second full-bridge circuit Phase B can also be regarded as a dc transformer.

In one possible embodiment, the "coupling" described above may be a magnetic coupling.

In a possible implementation manner, the first full-bridge circuit Phase a may include a first transistor Q1a, a second transistor Q2a, a third transistor Q3a, a fourth transistor Q4a and a first primary winding T1a, a first end of the first transistor Q1a is electrically connected to an output terminal of the current source PFC10 and a first end of the third transistor Q3a, a second end of the first transistor Q1a is electrically connected to a first end of the second transistor Q2a and a first end of the first primary winding T1a, a second end of the third transistor Q3a is electrically connected to a first end of the fourth transistor Q4a and a second end of the first primary winding T1a, and a second end of the second transistor Q2a is electrically connected to a second end of the fourth transistor Q4 a.

In one possible implementation, the first ends of the first transistor Q1a, the second transistor Q2a, the third transistor Q3a and the fourth transistor Q4a may be drains, and the second ends of the first transistor Q1a, the second transistor Q2a, the third transistor Q3a and the fourth transistor Q4a may be sources. It should be understood that in a practical use scenario, the transistor mentioned herein may be a MOSFET, an IGBT, etc., and when the transistor is a MOSFET, each end of the transistor includes a gate, a source, a drain; when the transistor is an IGBT, each terminal may include a collector, an emitter, and a base. Therefore, the present disclosure does not limit the type of the transistor, and the first and second terminals of the transistor are not limited by the present disclosure.

In one possible implementation, the second full-bridge circuit Phase B includes a fifth transistor Q1B, a sixth transistor Q2B, a seventh transistor Q3B, an eighth transistor Q4B and a second primary winding T1B, a first end of the fifth transistor Q1B is electrically connected to a first end of the seventh transistor Q3B, a second end of the fifth transistor Q1B is electrically connected to a first end of the sixth transistor Q2B and a first end of the second primary winding T1B, a second end of the second primary winding T1B is electrically connected to a second end of the seventh transistor Q3B and a first end of the eighth transistor Q4B, and a second end of the sixth transistor Q2B is electrically connected to the other output terminal of the current source PFC and a second end of the eighth transistor Q4B.

In one possible implementation, the first terminals of the fifth transistor Q1b, the sixth transistor Q2b, the seventh transistor Q3b and the eighth transistor Q4b may be drains, and the second terminals of the fifth transistor Q1b, the sixth transistor Q2b, the seventh transistor Q3b and the eighth transistor Q4b may be sources. It should be understood that, in a practical use scenario, the source and the drain of the transistor may be used interchangeably, and therefore, the first terminal and the second terminal of the transistor are not limited by the present disclosure.

In one possible embodiment, one output terminal of the current source PFC10 is connected to the drains of the transistor Q1, the transistor Q3, and the transistor Q5, and the other output terminal of the current source PFC10 is connected to the sources of the transistor Q2, the transistor Q4, and the transistor Q6.

In one possible implementation, the gates of the first transistor Q1a, the second transistor Q2a, the third transistor Q3a, the fourth transistor Q4a, the fifth transistor Q1b, the sixth transistor Q2b, the seventh transistor Q3b, and the eighth transistor Q4b may be configured to receive a control signal and be turned on or off according to the control signal.

In a possible embodiment, when the gain (i.e. the equivalent duty cycle) of the adjustable gain converter 20 is less than or equal to 50%, the duty cycle of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B is also less than or equal to 50% (which may represent the duty cycle of the DC transformer voltage), and the gain may be adjusted by PWM (pulse width modulation) or its own Phase shift control, which is mainly used for starting the DC/DC converter. If Phase shift control is used for starting, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are usually operated in the same Phase, i.e. their Phase shift β is equal to 0 °, and as the duty cycle increases, the output voltage rises. When the effective duty cycle reaches 50%, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are each operated at full duty cycle, i.e. the most efficient DC/DC transformer (DC transformer) open-loop operation mode.

In one possible embodiment, when the gain (equivalent duty cycle) of the adjustable gain converter 20 is equal to or greater than 50%, the gain is adjusted by adjusting the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B. When the Phase shift between them is zero (β ═ 0 °), the outputs of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are operated in parallel; when the Phase shift between them is 180 degrees (β ═ 180 °), the outputs of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are operated in series. The gain of the adjustable gain converter 20 can be adjusted steplessly by changing the phase shift between them. In this embodiment, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are both operated in the most efficient open-loop operation mode of the DC/DC converter.

In one possible implementation, the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B may be controlled by controlling the on and off times of the first transistor Q1a, the second transistor Q2a, the third transistor Q3a, the fourth transistor Q4a, the fifth transistor Q1B, the sixth transistor Q2B, the seventh transistor Q3B, and the eighth transistor Q4B. The first full-bridge circuit Phase a and the second full-bridge circuit Phase B may operate at different phases.

In one possible implementation, the first secondary circuit Phase a may include a first secondary winding T1a, a first diode D1a, and a second diode D2a, and the second secondary circuit Phase B includes a second secondary winding T1B, a third diode D1B, and a fourth diode D2B, and the first secondary circuit and the second secondary circuit each include a fifth diode DF1 and a sixth diode DF2, where:

a first end of the first secondary winding T1a is electrically connected to an anode of the first diode D1a and a cathode of the second diode D1b, and a cathode of the first diode D1a is electrically connected to a cathode of the third diode D2a and a cathode of the fifth diode DF 1; an anode of the third diode D2a is electrically connected to the first end of the second secondary winding T1b and a cathode of the fourth diode D2 b; a second end of the second secondary winding T1b is electrically connected to the second end of the first secondary winding T1a, an anode of a fifth diode DF1, and a cathode of a sixth diode DF2, and an anode of the fourth diode D2b is electrically connected to an anode of the second diode D1b and an anode of the sixth diode DF 2.

In one possible embodiment, the first diode D1a and the fifth diode DF1 constitute a first rectifying circuit for positive half-wave rectification of the first full-bridge circuit. The second diode D1b and the sixth diode DF2 constitute a second rectifying circuit for negative half-wave rectification of the first full-bridge circuit. The third diode D2a and the fifth diode DF1 constitute a third rectifying circuit for positive half-wave rectification of the second full-bridge circuit. The fourth diode D2b and the sixth diode DF2 constitute a fourth rectifying circuit for negative half-wave rectification of the second full-bridge circuit.

Functionally, the first secondary circuit comprises a first rectifying circuit and a second rectifying circuit, and the second secondary circuit comprises a third rectifying circuit and a fourth rectifying circuit.

In one possible implementation, the first secondary circuit and the second secondary circuit further include a first inductor Lo1 and a second inductor Lo2 in common, where:

a first end of the first inductor Lo1 is electrically connected to the cathode of the first diode D1a, the cathode of the third diode D2a, and the cathode of the fifth diode DF1, a first end of the second inductor Lo2 is electrically connected to the anode of the sixth diode DF2, the anode of the second diode D1b, and the anode of the fourth diode D2b, and a second end of the first inductor Lo1 and a second end of the second inductor Lo2 are configured to output the supply voltage and the supply current.

In a possible embodiment, the adjustable gain converter 20 further includes a first capacitor Co1 and a second capacitor Co2, a first end of the first capacitor Co1 is electrically connected to the second end of the first inductor Lo1, a second end of the first capacitor Co1 is electrically connected to the first end of the second capacitor Co2 and the second ends of the first secondary winding T1a and the second secondary winding T1b, and a second end of the second capacitor Co2 is electrically connected to the second end of the second inductor Lo 2.

In a possible implementation manner, the capacitors of the first capacitor Co1 and the second capacitor Co2 may be small capacitors, and may be configured to absorb high-frequency switching current ripples, and compared to a related art that large electrolytic capacitors are used to eliminate line-frequency current ripples, the area occupied by components may be greatly reduced by the present disclosure, so as to optimize the circuit structure and significantly reduce the cost.

In one possible embodiment, the adjusting the gain by adjusting the phase shift between the first full-bridge circuit and the second full-bridge circuit may include:

the phase shift is determined by the following equation:

In one possible embodiment, the phase shift may be a phase difference of the second full-bridge circuit relative to the first full-bridge circuit.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a phase-supply voltage-conversion voltage relationship according to an embodiment of the disclosure.

In the example of fig. 4, the minimum value V1 of the load voltage is 330V, the maximum value V2 of the load voltage is 750V, and the load voltage Vo can vary between 330V-750V. In this case, the phase shift may be determined by the formula:

β＝180°*((Vo-330)/420)。

when the load voltage Vo is obtained, the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B can be determined according to the above formula. The first full-bridge circuit Phase a and the second full-bridge circuit Phase B may be configured to operate at the same Phase, and at this time, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are Phase-shifted by 0 °, in this case, the first secondary circuit coupled to the first full-bridge circuit Phase a and the second secondary circuit coupled to the second full-bridge circuit Phase B are connected in parallel, and at this time, the power supply system outputs high current and low voltage. The first full-bridge circuit Phase a and the second full-bridge circuit Phase B may be configured to operate in opposite phases, in which case the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are 180 ° Phase shifted, in which case the first secondary circuit coupled to the first full-bridge circuit Phase a and the second secondary circuit coupled to the second full-bridge circuit Phase B are connected in series, and the power supply system outputs a low current and a high voltage.

For example, when the load voltage Vo is 330V, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are configured to operate at the same Phase. When the load voltage Vo is 750V, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are configured to operate at opposite phases, and at this time, the Phase difference therebetween is 180 °.

When the load voltage Vo is between 330V and 750V, the Phase shift β between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B can also be obtained by the above method to adjust the gain of the adjustable gain converter. In this case, the first secondary circuit and the second secondary circuit may be regarded as being partially connected in parallel and partially connected in series. By such control, the conversion voltage output by the current source PFC can be limited within a required range, thereby improving the working efficiency of the power supply system.

After the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B is determined, the equivalent turns ratio N of the adjustable gain converter 20 can be obtained (as shown in fig. 1, N ═ f (vo)).

It should be understood that the load voltage Vo according to the present disclosure may be a charging voltage initially required by the load 40, or may be a received power supply voltage of the load 40 during a charging process, and when the battery pack of the load 40 is charged, the voltage of the battery pack of the load 40 may gradually increase, for example, from about 330V to about 420V within 1-2 hours, so that the load voltage has a dynamic variation process.

As can be seen from fig. 4, the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B can be determined according to the load voltage V, and the magnitude of the converted voltage that the current source PFC10 needs to output can also be obtained.

For example, when the turn ratio of the primary side and the secondary side of the transformers T1a and T1b is 1: 1, the conversion voltage that the voltage bus of the current source PFC can output may be:

Vbus＝660+90*(Vo-330)/420。

it can be seen that the voltage on the voltage bus Vbus may be in the range of 600V to 750V.

With continuing reference to fig. 2a, in one possible implementation, the adjustable gain converter 20 may further include: a third capacitor Ca and a fourth capacitor Cb, wherein a first end of the third capacitor Ca is electrically connected to one end of the current source PFC10, a second end of the third capacitor Ca is electrically connected to a first end of the fourth capacitor Cb and a connection point between the first full bridge circuit Phase B and the second full bridge circuit Phase B, and a second end of the fourth capacitor Cb is electrically connected to the other end of the current source PFC 10.

In a possible implementation manner, the capacitors of the third capacitor Ca and the fourth capacitor Cb may be small capacitors, and may be configured to absorb the switching frequency current ripple of the voltage bus Vbus, and compared with a method that a large electrolytic capacitor is used to eliminate the line frequency current ripple in the related art, the area occupied by components may be greatly reduced in the present disclosure, so as to optimize the circuit structure and significantly reduce the cost. In this case, the current source PFC and the adjustable gain converter are not controlled independently, but controlled at a system level, and the current source PFC and the adjustable gain converter operate more efficiently.

It should be understood that the above description of the adjustable gain converter is exemplary, and should not be construed as limiting the present disclosure, and the skilled in the art may consider that components may be added, reduced or the connection relationship of the components may be changed on the basis of the present disclosure, as long as the change of the supply voltage is realized through a plurality of transformer structures and through the phase control of different transformers, and such change should be regarded as a modification based on the present disclosure, and the modification should be regarded as being within the protection scope of the present disclosure.

The output stage of the present disclosure presents a voltage doubling circuit connection (fig. 2a), and the dc transformer shown in fig. 2a may not have a center tap, and the design of the transformer may be simplified and the cost may be reduced. Of course, in other embodiments, the transformer may also be implemented by using a current doubler circuit with a center tap (fig. 2b), which also implements the function of the adjustable gain converter, and should also be regarded as a variation based on the present disclosure, and the variation should be regarded as being within the protection scope of the present disclosure.

Referring to fig. 5, fig. 5 is a schematic diagram of an adjustable gain converter according to an embodiment of the disclosure.

The adjustable gain converter 20 can adjust the gain by adjusting the Phase shift between the first full bridge circuit Phase a and the second full bridge circuit Phase B, the adjustable gain converter 20 of the present disclosure can achieve automatic power balance between the first full bridge circuit Phase a and the second full bridge circuit Phase B, the first full bridge circuit Phase a and the second full bridge circuit Phase B operate in parallel when outputting a low supply voltage Vo and in series when outputting a high supply voltage Vo, and within a useful supply voltage range (e.g. 330V-750V) of the output, the first full bridge circuit Phase a and the second full bridge circuit Phase B both operate in the most efficient DC/transformer open-loop operation mode, stress variation of each component of the adjustable gain converter is small, the Phase shift between the first full bridge circuit Phase a and the second full bridge circuit Phase B can be seamlessly changed, in order to adapt the output of the supply voltage Vo between a minimum value (e.g. 330V) and a maximum value (e.g. 750V), in such a way that a high and smooth power conversion efficiency of the AC/DC converter is achieved over the whole voltage regulation range.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating various waveforms in an adjustable gain converter according to an embodiment of the disclosure.

The waveforms include voltage waveforms of the secondary nodes VF1 and VF2, waveforms of the currents Io1 and Io2 flowing through the inductors Lo1 and Lo2, waveforms of the voltage Vsa and the current Isa of the first secondary winding, and waveforms of the voltage Vsb and the current Isb of the second secondary winding.

In one possible implementation, both the first full-bridge circuit Phase a and the second full-bridge circuit Phase B may operate at full duty cycle, and both may implement ZVS over a wide range (e.g., 330V-750V). Because the respective voltages and currents of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B work in the same Phase, the circulating currents of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are almost zero, the working efficiency of the adjustable gain converter can be greatly improved, and high-efficiency and high-density work is realized.

As shown in fig. 6, as the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B changes, the voltage and current waveforms at the nodes of the adjustable gain converter change accordingly. Taking the current Isa as an example, when the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are switched from the parallel operation mode to the series operation mode (the Phase shift is changed from 0 ° to 180 °), the current value of the current Isa is reduced to half of the original value.

It should be noted that, for a specific description of the adjustable gain converter, please refer to the above description, and the detailed description is omitted here.

Referring to fig. 7a and 7b, fig. 7a shows a schematic diagram of a first full-bridge circuit and a first secondary circuit according to an embodiment of the disclosure, and fig. 7b shows a control schematic diagram of the first full-bridge circuit according to an embodiment of the disclosure.

As shown in fig. 7b, when the duty cycle of the first full-bridge circuit is equal to 50% (full duty cycle), the operating state of the first full-bridge circuit can be controlled by phase shift control or PWM control. At this time, the two controls are fully equivalent.

In the phase shift control, the turn-on and turn-off of the respective transistors of the first full bridge circuit may be phase shift controlled so that the first transistor Q1a, the second transistor Q2a, the third transistor Q3a, and the fourth transistor Q4a are turned on at different times.

In the PWM control, the first transistor Q1a, the second transistor Q2a, the third transistor Q3a and the fourth transistor Q4a may be turned on at different times by PWM pulses, so as to control the operating condition of the first full-bridge circuit.

In one possible implementation, fig. 7b shows the voltages Vsa, VF1, VF2 of the first secondary winding T1a controlled by phase shift control and PWM.

Similarly, when the duty cycle of the second full-bridge circuit is equal to 50%, the operating states of the fifth transistor Q1b, the sixth transistor Q2b, the seventh transistor Q3b and the eighth transistor Q4b in the second full-bridge circuit can also be controlled by phase shift control and PWM control.

It should be understood that fig. 7B is exemplary, and those skilled in the art can set the operation states of the transistors of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B according to practical situations, and the disclosure is not limited thereto.

Referring to fig. 8a and 8B, fig. 8a shows a control schematic diagram when the gain of the adjustable gain converter 20 is less than or equal to 0.5 (i.e. equivalent duty cycle, taking the transformation ratio of the transformer as 1) and the duty cycle of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B is less than or equal to 50% according to an embodiment of the disclosure, and fig. 8B shows a Phase shift control schematic diagram of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B when the gain of the adjustable gain converter 20 is greater than or equal to 0.5 (taking the transformation ratio of the transformer as 1) according to an embodiment of the disclosure.

As shown in fig. 8a, when the Phase duty cycle of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B is less than or equal to 50%, the operation states of the transistors of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B may be controlled by Phase shift control or PWM.

As shown in fig. 8B, after the Phase shift β is obtained by the adjustable gain converter, the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B can be adjusted according to the Phase shift β, so that the first full-bridge circuit Phase a and the second full-bridge circuit Phase B operate in parallel and in series, thereby adjusting the power supply voltage. At this time, the first full-bridge circuit Phase a and the second full-bridge circuit Phase B each operate in the full duty state.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating control signals of each transistor between gains 0-1 of the adjustable gain converter.

It can be seen that when the duty cycle of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B is below 50%, the operation states of the transistors of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B can be controlled by PWM. When the duty cycles of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B both reach the full duty cycle of 50%, the gain of the adjustable gain converter may be continuously adjusted by controlling the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B, and the operating states of the transistors of the first full-bridge circuit Phase a and/or the second full-bridge circuit Phase B are controlled as shown in fig. 9.

For example, when the duty ratios of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B are 50% of the full duty ratio, the operation states of the transistors of the first full-bridge circuit Phase a may be controlled by delaying the Phase shift β and then outputting the control signal to control the operation states of the transistors of the second full-bridge circuit Phase B, in such a manner that the gain of the adjustable gain converter is controlled from 0.5 to 1, and the first full-bridge circuit Phase a and the second full-bridge circuit Phase B may be gradually changed from the parallel state to the series state to increase the supply voltage.

It should be noted that the above control of the transistors of the first full-bridge circuit Phase a and the second full-bridge circuit Phase B is exemplary, and the above description should not be considered as a limitation of the present disclosure, as long as the technical solution of adjusting the output supply voltage by controlling the Phase shift between the first full-bridge circuit Phase a and the second full-bridge circuit Phase B is realized, should be regarded as being within the scope of the present disclosure.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A power supply system, characterized in that the system comprises:

an adjustable gain converter electrically connected to the current source PFC and the load for receiving a load voltage of the load and adjusting a gain of the adjustable gain converter by using the load voltage to output a supply voltage by using the transformed voltage and the gain and output a supply current by using the transformed current and the gain, the adjustable gain converter includes a first full bridge circuit, a second full bridge circuit, a first secondary circuit and a second secondary circuit, the first full bridge circuit is connected in series with the second full bridge circuit, the first secondary circuit is coupled to the first full bridge circuit, the second secondary circuit is coupled to the second full bridge circuit, the first secondary circuit includes a first secondary winding, a first diode, a second diode, a first rectifying circuit and a second rectifying circuit, the second secondary circuit includes a second secondary winding, a second rectifying circuit, a second, The first secondary circuit and the second secondary circuit comprise a fifth diode and a sixth diode, the first rectifying circuit comprises the first diode and the fifth diode, the second rectifying circuit comprises the second diode and the sixth diode, the third rectifying circuit comprises the third diode and the fifth diode, and the fourth rectifying circuit comprises the fourth diode and the sixth diode, wherein the first end of the first secondary winding is electrically connected to the anode of the first diode and the cathode of the second diode, and the cathode of the first diode is electrically connected to the cathode of the third diode and the cathode of the fifth diode; the anode of the third diode is electrically connected to the first end of the second secondary winding and the cathode of the fourth diode; the second end of the second secondary winding is electrically connected to the second end of the first secondary winding, the anode of a fifth diode and the cathode of a sixth diode, and the anode of the fourth diode is electrically connected to the anode of the second diode and the anode of the sixth diode;

2. The system of claim 1, wherein the gain of the adjustable gain converter is adjusted by changing a phase shift between the first full-bridge circuit and the second full-bridge circuit.

3. The system of claim 2, wherein the first full bridge circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first primary winding, a first terminal of the first transistor is electrically connected to an output terminal of the current source PFC and a first terminal of the third transistor, a second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first primary winding, a second terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a second terminal of the first primary winding, and a second terminal of the second transistor is electrically connected to a second terminal of the fourth transistor.

4. The system according to claim 2, wherein the second full-bridge circuit comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a second primary winding, a first end of the fifth transistor is electrically connected to a first end of the seventh transistor, a second end of the fifth transistor is electrically connected to a first end of the sixth transistor and a first end of the second primary winding, a second end of the second primary winding is electrically connected to a second end of the seventh transistor and a first end of the eighth transistor, and a second end of the sixth transistor is electrically connected to the other output terminal of the current source PFC and a second end of the eighth transistor.

5. The system according to claim 2, wherein the first rectification circuit is used for positive half-wave rectification of the first full-bridge circuit;

6. The system of claim 5, wherein the first and third rectification circuits are configured as two interleaved power rectifiers, and/or

7. The system of claim 1, wherein the first secondary circuit and the second secondary circuit further collectively comprise a first inductance and a second inductance, wherein:

8. The system of claim 7, wherein the adjustable gain converter further comprises a first capacitor and a second capacitor, a first end of the first capacitor is electrically connected to the second end of the first inductor, and a second end of the first capacitor is electrically connected to the first end of the second capacitor, the second end of the first secondary winding, and the second end of the second secondary winding; the second end of the second capacitor is electrically connected to the second end of the second inductor.

9. The system according to claim 2, characterized in that the gain is adjusted by adjusting the phase shift of the first full-bridge circuit and the second full-bridge circuit or by pulse width modulation, PWM, when the duty cycle of the first full-bridge circuit and/or the second full-bridge circuit is less than or equal to 50%.

10. The system according to claim 2, characterized in that the gain is adjusted by adjusting the phase shift between the first full-bridge circuit and the second full-bridge circuit when the duty cycle of the first full-bridge circuit and/or the second full-bridge circuit is equal to 50%.

11. The system of claim 10, wherein said adjusting the gain by adjusting a phase shift between the first full-bridge circuit and the second full-bridge circuit comprises:

the phase shift is determined by the following equation:

12. The system of claim 2, wherein the adjustable gain converter further comprises: the first end of the third capacitor is electrically connected to one end of the current source PFC, the second end of the third capacitor is electrically connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is electrically connected to the other end of the current source PFC.

13. The system of claim 1, wherein the feedback controller comprises an operational amplifier and a current loop compensator,

14. A charging device, characterized in that it comprises a power supply system according to any one of claims 1-13.