CN109841685B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN109841685B
CN109841685B CN201811375094.5A CN201811375094A CN109841685B CN 109841685 B CN109841685 B CN 109841685B CN 201811375094 A CN201811375094 A CN 201811375094A CN 109841685 B CN109841685 B CN 109841685B
Authority
CN
China
Prior art keywords
contact hole
insulating layer
semiconductor substrate
layer
interlayer insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811375094.5A
Other languages
Chinese (zh)
Other versions
CN109841685A (en
Inventor
长谷川贵史
斋藤浩一
工藤千秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Publication of CN109841685A publication Critical patent/CN109841685A/en
Application granted granted Critical
Publication of CN109841685B publication Critical patent/CN109841685B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

The invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device in one embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source wiring. The gate insulating layer is positioned on the surface of the semiconductor substrate. The gate electrode is located on the gate insulating layer. An interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer to expose a part of the surface of the semiconductor substrate, and has an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers at least a portion of the upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and a portion of the surface of the exposed semiconductor substrate. The source wiring is connected to a portion of the metal layer that covers at least a part of the exposed surface of the semiconductor substrate via the contact hole. In the semiconductor device, the thickness of a portion of the metal layer covering at least the lower portion of the inner side surface of the contact hole is 35nm or more.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same.
Background
The power semiconductor device is a semiconductor element used for applications where high withstand voltage and large current flow, and is desired to have low loss. Conventionally, a power semiconductor device using a silicon (Si) substrate has been mainly used, but recently, a power semiconductor device using a silicon carbide (SiC) substrate has been attracting attention and development has been advanced.
Silicon carbide has a dielectric breakdown voltage higher by one digit than silicon, and therefore has a feature that it can maintain withstand voltage even if the depletion layer in the pn junction or schottky junction is thinned. Therefore, if silicon carbide is used, the thickness of the device can be reduced, and the doping concentration can be increased, so that silicon carbide is expected as a material for forming a power semiconductor device having low on-resistance, high withstand voltage, and low loss.
In recent years, vehicles using a motor as a driving source, such as hybrid vehicles, electric vehicles, and fuel cell vehicles, have been developed. Since the above-described features are advantageous for switching elements of inverter circuits for driving motors of these vehicles, silicon carbide power semiconductor devices for vehicles have been developed.
It is known that in a power semiconductor device using a silicon carbide substrate, the threshold voltage of a gate electrode may vary under a high temperature environment. For example, patent document 1 discloses a semiconductor device that suppresses variation in threshold voltage of such a gate.
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2012-129503
Disclosure of Invention
The present invention provides a novel technique for improving the reliability of a semiconductor device such as a power semiconductor device. Hereinafter, the power semiconductor device is referred to as a semiconductor device.
The semiconductor device according to one aspect of the present invention includes: the semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source wiring. The gate insulating layer is positioned on the surface of the semiconductor substrate. The gate electrode is located on the gate insulating layer. An interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer to expose a part of the surface of the semiconductor substrate, and has an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers at least a portion of the upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and the surface of the exposed semiconductor substrate. The source wiring is connected to a portion of the metal layer that covers at least a part of the surface of the exposed semiconductor substrate via the contact hole. In a cross section perpendicular to the surface of the semiconductor substrate, the inner side surface of the contact hole faces the opening of the contact hole. The inner side surface of the contact hole is provided with a first inner side surface close to the surface of the semiconductor substrate and a second inner side surface close to the opening of the contact hole. The first inner side surface of the contact hole forms an angle with the surface of the semiconductor substrate smaller than the second inner side surface of the contact hole forms an angle with the surface of the semiconductor substrate.
A method for manufacturing a semiconductor device according to another aspect of the present invention includes first to tenth steps. In the first step, a semiconductor substrate is prepared. In the second step, a gate insulating layer is provided on the surface of the semiconductor substrate. In the third step, a gate electrode is provided on the gate insulating layer. In the fourth step, the gate electrode is covered with an interlayer insulating layer. In the fifth step, a mask layer is provided on the interlayer insulating layer. In the sixth step, the interlayer insulating layer and the gate insulating layer are etched using the mask layer to provide a contact hole which exposes a part of the surface of the semiconductor substrate and has an inner surface defined by the side surface of the interlayer insulating layer and the side surface of the gate insulating layer. In the seventh step, the mask layer is removed. In the eighth step, a part of the surface of the semiconductor substrate exposed through the contact hole is covered with a metal, and an annealing treatment is performed to form a silicide layer. In the ninth step, a metal layer is provided, which covers at least a part of the silicide layer, the upper surface of the interlayer insulating layer, the inner surface of the contact hole, and the silicide layer. In the tenth step, a source wiring is provided, and the source wiring is connected to a portion of the metal layer that covers at least a part of the silicide layer via the contact hole. The metal layer has a thickness of 35nm or more at least in a portion covering the lower portion of the inner side surface of the contact hole.
The above summary or detailed description may also be implemented by a system, method, integrated circuit, computer program, or recording medium. Alternatively, the present invention may be implemented by any combination of systems, apparatuses, methods, integrated circuits, computer programs, and recording media.
According to the technique of the present invention, the reliability of the semiconductor device can be improved.
Drawings
Fig. 1 is a cross-sectional view schematically showing a configuration example of a semiconductor device 100 according to the embodiment.
Fig. 2 is a view showing an example of a photograph of a scanning electron microscope of a cross section of the semiconductor device 100 according to the embodiment.
Fig. 3 shows an inner side surface 23s of a lower portion of a contact hole in the semiconductor device 100 according to the embodiment 1 A graph showing an example of a graph of the relationship between the thickness of the metal layer 20 and the failure rate in the gate life reliability test.
FIG. 4 shows an inner side surface 23s depicting the taper angle and the upper portion of the contact hole 2 A graph of an example of a graph of the relationship between the thicknesses of the metal layers 20.
Fig. 5 is a diagram showing an example of a graph in which the thickness of the metal layer 20 is normalized with respect to the taper angle 0 ° in fig. 4 and expressed as coverage (coverage).
Fig. 6A is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 6B is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 6C is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 in the embodiment.
Fig. 6D is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 6E is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 6F is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 6G schematically illustrates an example of a process for manufacturing the semiconductor device 100 according to the embodiment.
Fig. 6H schematically illustrates an example of a process for manufacturing the semiconductor device 100 according to the embodiment.
Fig. 6I is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 6J is a diagram schematically showing an example of a manufacturing process of the semiconductor device 100 according to the embodiment.
Fig. 7 is a graph showing an example of a graph depicting the relationship between the wafer in-plane uniformity of the etching rate and the taper angle in the case of using a 6-inch wafer when the interlayer insulating layer 38 is etched in fig. 6F.
Fig. 8 is a graph showing an example of a graph depicting the relationship between the measured position and the etching rate in a 6-inch wafer at various etching times.
Symbol description
11: semiconductor substrate, 11s: surface of semiconductor substrate, 17: gate insulating layer, 17s: side of gate insulation layer, 18: gate electrode, 19: source wiring, 20: metal layer, 21: silicide layer, 23: contact hole, 23o: opening portion of contact hole, 23s: inner side surface of contact hole, 23s 1 : inner side surface of lower portion of contact hole, 23s2: inner side surface of upper portion of contact hole, 31: mask layer, 31o: opening portion of mask layer, 38: interlayer insulating layer, 38s: side surfaces of the interlayer insulating layer, 38u: upper surface of interlayer insulating layer, 38su: surface of interlayer insulating layer, 38fl: flat portions of the surface of the interlayer insulating layer, 38sl: inclined portion of surface of interlayer insulating layer, 100: a semiconductor device.
Detailed Description
As a result of the studies by the present inventors, it has been found that the semiconductor device of patent document 1 may not sufficiently suppress the variation in threshold voltage of the gate electrode in a high-temperature environment.
Patent document 1 discloses a semiconductor device in which a barrier metal layer is provided between an interlayer insulating layer and a source wiring, thereby suppressing a decrease in threshold voltage of a gate with time and preventing a short circuit between a gate and a source.
The threshold voltage of the gate electrode varies due to the penetration of mobile ions into the gate insulating layer. Therefore, it is considered that if the barrier metal layer has a sufficient thickness, variation in threshold voltage of the gate electrode can be suppressed.
In the semiconductor device of patent document 1, the barrier metal layer covers a side surface of the interlayer insulating layer which is substantially perpendicular to the semiconductor substrate. However, for reasons described later, in this structure, it is difficult for the barrier metal layer to have a sufficient thickness on the vertical side surface. As a result, the threshold voltage of the gate may not be sufficiently suppressed.
Based on the above-described studies, the present inventors have conceived a semiconductor device and a method for manufacturing the same described in the following items.
[ item 1]
The semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source wiring.
The gate insulating layer is positioned on the surface of the semiconductor substrate.
The gate electrode is located on the gate insulating layer.
An interlayer insulating layer covers the gate electrode.
The contact hole penetrates the gate insulating layer and the interlayer insulating layer to expose a part of the surface of the semiconductor substrate, and has an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer.
The metal layer covers at least a portion of the upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and a portion of the surface of the exposed semiconductor substrate.
The source wiring is connected to a portion of the metal layer that covers at least a part of the surface of the exposed semiconductor substrate via the contact hole.
In the semiconductor device, a thickness of a portion of the metal layer, which covers at least an inner side surface of the contact hole and is in the vicinity of the semiconductor substrate, is 35nm or more.
[ item 2]
In the semiconductor device according to item 1, when the thickness of the portion of the metal layer covering the lower portion of the inner side surface of the contact hole is a first thickness and the thickness of the portion of the metal layer covering the upper surface of the inter-layer insulating layer is a second thickness, the first thickness is 35% or more of the second thickness.
[ item 3]
The semiconductor device according to item 1 or 2, wherein an inner surface of the contact hole faces an opening of the contact hole in a cross section perpendicular to a surface of the semiconductor substrate, and an angle formed between the surface of the semiconductor substrate and a lower portion of the inner surface of the contact hole is 75 degrees or less.
[ item 4]
The semiconductor device according to item 3, wherein the inner surface of the contact hole has a first inner surface close to the surface of the semiconductor substrate and a second inner surface farther from the surface of the semiconductor substrate than the first inner surface, a first angle formed between the first inner surface of the contact hole and the surface of the semiconductor substrate is smaller than a second angle formed between the second inner surface of the contact hole and the surface of the semiconductor substrate, and the first angle is 75 degrees or less.
[ item 5]
The semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source wiring.
The gate insulating layer is positioned on the surface of the semiconductor substrate.
The gate electrode is located on the gate insulating layer.
An interlayer insulating layer covers the gate electrode.
The contact hole penetrates the gate insulating layer and the interlayer insulating layer to expose a part of the surface of the semiconductor substrate, and has an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer.
The metal layer covers at least a portion of the upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and a portion of the surface of the exposed semiconductor substrate.
The source wiring is connected to a portion of the metal layer that covers at least a part of the exposed surface of the semiconductor substrate via the contact hole.
In a cross section perpendicular to the surface of the semiconductor substrate, the inner side surface of the contact hole faces the opening of the contact hole. The inner side surface of the contact hole has a first inner side surface near the surface of the semiconductor substrate and a second inner side surface near the opening of the contact hole. Moreover, the angle formed by the first inner side surface of the contact hole and the surface of the semiconductor substrate is smaller than the angle formed by the second inner side surface of the contact hole and the surface of the semiconductor substrate.
[ item 6]
The semiconductor device according to any one of items 1 to 5, wherein a part of the surface of the exposed semiconductor substrate is a silicide layer formed of silicide.
[ item 7]
In the semiconductor device according to item 6, a part of the silicide layer covers a side surface of the gate insulating layer.
[ item 8]
The semiconductor device according to any one of items 1 to 7, wherein the metal layer has a double-layer structure formed of two different metals.
[ item 9]
The semiconductor device according to any one of items 1 to 8, wherein the semiconductor device is a MOSFET.
[ item 10]
The method for manufacturing a semiconductor device includes the following first to tenth steps.
The first step is a step of preparing a semiconductor substrate.
The second step is a step of providing a gate insulating layer on the surface of the semiconductor substrate.
The third step is a step of providing a gate electrode on the gate insulating layer.
The fourth step is a step of covering the gate electrode with an interlayer insulating layer.
The fifth step is a step of providing a mask layer on the interlayer insulating layer.
The sixth step is a step of forming a contact hole by etching the interlayer insulating layer and the gate insulating layer using the mask layer, the contact hole exposing a part of the surface of the semiconductor substrate and having an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer.
The seventh step is a step of removing the mask layer.
The eighth step is a step of forming a silicide layer by covering a part of the surface of the semiconductor substrate exposed through the contact hole with a metal and performing an annealing treatment.
The ninth step is a step of providing a metal layer covering at least a part of the silicide layer, the inner side surface of the contact hole, and the upper surface of the interlayer insulating layer.
The tenth step is a step of providing a source wiring connected to a portion of the metal layer that covers at least a part of the silicide layer through the contact hole.
In the method for manufacturing a semiconductor device, a thickness of a portion of the metal layer covering at least a lower portion of the inner side surface of the contact hole is 35nm or more.
[ item 11]
The method for manufacturing a semiconductor device includes the following first to tenth steps.
The first step is a step of preparing a semiconductor substrate.
The second step is a step of providing a gate insulating layer on the surface of the semiconductor substrate.
The third step is a step of providing a gate electrode on the gate insulating layer.
The fourth step is a step of covering the gate electrode with an interlayer insulating layer.
The fifth step is a step of providing a mask layer on the interlayer insulating layer.
The sixth step is a step of forming a contact hole by etching the interlayer insulating layer and the gate insulating layer using the mask layer, the contact hole exposing a part of the surface of the semiconductor substrate and having an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer.
The seventh step is a step of removing the mask layer.
The eighth step is a step of forming a silicide layer by performing an annealing treatment while covering a part of the surface of the semiconductor substrate exposed through the contact hole with a metal.
The ninth step is a step of providing a metal layer covering at least a part of the silicide layer, the inner side surface of the contact hole, and the upper surface of the interlayer insulating layer.
The tenth step is a step of providing a source wiring connected to a portion of the metal layer that covers at least a part of the silicide layer through the contact hole.
In the method for manufacturing a semiconductor device, the inner surface of the contact hole faces the opening of the contact hole in a cross section perpendicular to the surface of the semiconductor substrate. The inner side surface of the contact hole has a first inner side surface near the surface of the semiconductor substrate and a second inner side surface near the opening of the contact hole. In addition, an angle formed between the first inner side surface of the contact hole and the surface of the semiconductor substrate is smaller than an angle formed between the second inner side surface of the contact hole and the surface of the semiconductor substrate.
[ item 12]
The method for manufacturing a semiconductor device according to item 11, wherein the surface of the interlayer insulating layer covering the gate electrode in the fourth step includes a flat portion and an inclined portion. The mask layer in the fifth step has an opening for defining a contact hole. In the opening portion of the mask layer, there are a flat portion and an inclined portion in the surface of the interlayer insulating layer.
[ item 13]
The method for manufacturing a semiconductor device according to any one of items 10 to 12, wherein in the sixth step, CHF is used 3 、CF 4 And a mixed gas of Ar.
[ item 14]
The method for manufacturing a semiconductor device according to item 13, wherein the step of performing etching for 60 seconds and the step of performing cooling after etching are repeated in the sixth step.
Thereby, the reliability of the semiconductor device can be improved.
Hereinafter, more specific embodiments of the present invention will be described. However, the above detailed description may be omitted. For example, a detailed description of known matters may be omitted, and a repeated description of substantially the same structure may be omitted. This is to avoid that the following description becomes unnecessarily lengthy, so that it will be readily understood by those skilled in the art. The drawings and the following description are provided for a thorough understanding of the present invention by those skilled in the art, and are not intended to limit the subject matter recited in the claims. In the following description, the same reference numerals are given to constituent elements having the same or similar functions.
(embodiment)
Hereinafter, the present invention will be described in general with reference to schematic drawings. The present invention relates to a relationship between a shape of an inner surface of a contact hole to be described later and a thickness of a metal layer located on the inner surface. The semiconductor device of the present embodiment is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: metal oxide semiconductor field effect transistor).
Fig. 1 is a cross-sectional view schematically showing a configuration example of a semiconductor device 100 according to the present embodiment. Fig. 2 is a view showing an example of a photograph of a scanning electron microscope of a cross section of the semiconductor device 100 according to the present embodiment. In the example shown in fig. 1 and 2, the semiconductor device 100 is a MOSFET. Hereinafter, the same structure as the conventional structure may be omitted.
The semiconductor device 100 of the present embodiment includes a semiconductor substrate 11, a gate insulating layer 17, a gate electrode 18, an interlayer insulating layer 38, a contact hole 23, a metal layer 20, and a source wiring 19.
The semiconductor substrate 11 is formed of silicon carbide, but may be formed of a semiconductor material other than silicon carbide.
The gate insulating layer 17 is located on the surface 11s of the semiconductor substrate. The gate insulating layer 17 is, for example, an insulating layer obtained by thermally oxidizing the surface 11s of the semiconductor substrate.
A gate electrode 18 is located on the gate insulating layer 17. The gate electrode 18 is, for example, polysilicon.
An interlayer insulating layer 38 covers the gate electrode 18. The interlayer insulating layer 38 is, for example, undoped silicon oxide glass (NSG).
The contact hole 23 penetrates the gate insulating layer 17 and the interlayer insulating layer 38 to expose a part of the surface 11s of the semiconductor substrate. The hole at the upper portion of the contact hole 23 is an opening 23o of the contact hole. The inner side surface 23s of the contact hole is defined by the side surface 38s of the interlayer insulating layer and the side surface 17s of the gate insulating layer.
A part of the surface 11s of the exposed semiconductor substrate may be a silicide layer 21 formed of silicide which is a compound of silicon and metal. The silicide layer 21 realizes ohmic contact. The silicide layer 21 is formed of NiSi, which is a compound of Si and Ni, for example. Hereinafter, a part of the surface 11s of the exposed semiconductor substrate is referred to as a silicide layer 21.
The metal layer 20 covers the upper surface 38u of the interlayer insulating layer,The inner side 23s of the contact hole and at least a portion of the silicide layer 21. The metal layer 20 covers at least an inner surface 23s of a lower portion of a contact hole to be described later 1 The thickness of the part of (C) is 35nm or more. Inner side surface 23s of lower portion of contact hole 1 Is present in a range of 0nm to 600nm in the vertical direction from the surface 11s of the semiconductor substrate. The metal layer 20 may be provided with a double layer construction formed of two different metals. The metal layer 20 is, for example, a double layer structure formed of a Ti layer and a TiN layer.
The metal layer 20 can cover the side 17s of the gate insulating layer. In addition, in the case where the silicide layer 21 is formed to be raised from the surface 11s of the original semiconductor substrate, a part of the silicide layer 21 can cover the side surface 17s of the gate insulating layer.
The source wiring 19 is connected to a portion of the metal layer 20 that covers at least the above-mentioned at least a portion of the silicide layer 21 via the contact hole 23. At this time, the portion of the semiconductor substrate 11 in contact with the silicide layer 21 corresponds to a source electrode not shown. The source wiring 19 may entirely cover the metal layer 20. The source wiring 19 is, for example, aluminum (Al). Other conductive materials may be further provided on the source wiring 19.
In practice, a drain electrode, not shown, is located on the opposite side of the semiconductor substrate 11 from the surface on which the gate insulating layer 17 and the like are located. Other wiring may also be located on the drain electrode.
In a conventional semiconductor device having a thin metal layer 20, it is known that the threshold voltage of the gate electrode fluctuates in a high-temperature environment. As a cause of this fluctuation, the following two reasons are considered.
(reason 1) if the metal layer 20 is thin, mobile ions existing in the external environment of the semiconductor device under a high-temperature environment intrude from at least one of the side face 17s of the gate insulating layer and the side face 38s of the interlayer insulating layer through the thin portion of the metal layer 20. A part of the mobile ions intruded is trapped between the semiconductor substrate 11 and the gate electrode 18 in the gate insulating layer 17. As a result, the threshold voltage of the gate may vary.
(reason 2) the mobile ions included in the interlayer insulating layer 38 are trapped in the metal layer 20. However, when the metal layer 20 is thin, the trapping amount of mobile ions is small. Therefore, the mobile ions remaining in the interlayer insulating layer 38 are trapped between the semiconductor substrate 11 and the gate electrode 18 in the gate insulating layer 17. As a result, the threshold voltage of the gate may vary.
In order to suppress the fluctuation of the threshold voltage of the gate electrode due to the intrusion of the mobile ions into the gate insulating layer 17, the metal layer 20 may have a sufficient thickness on the inner surface 23s of the contact hole. That is, the metal layer 20 functions as a barrier metal or a trapping layer that prevents the intrusion of mobile ions into the gate insulating layer 17. It is considered that if the metal layer 20 is on the lower inner side surface 23s of the contact hole among the inner side surfaces 23s of the contact hole 1 With a sufficient thickness, the effect of suppressing the variation in threshold voltage of the gate can be obtained.
However, in the conventional semiconductor device, it is difficult to provide the metal layer 20 with a sufficient thickness on the inner side surface 23s of the contact hole. This is because, in the conventional semiconductor device, the inner surface 23s of the contact hole is substantially perpendicular to the surface 11s of the semiconductor substrate.
In general, the metal layer 20 is provided on the inner side surface 23s of the contact hole by sputtering metal. The metal particles are sputtered to fly out from the vertical direction and the oblique direction toward the interlayer insulating layer 38 with respect to the surface 11s of the semiconductor substrate. At this time, the portion of the upper surface 38u of the inter-layer insulating layer in the metal layer 20 is formed of metal particles flying from both the vertical direction and the oblique direction. Among the vertical direction and the oblique direction, the contribution of the vertical direction to the thickness of the stacked layer is extremely large. Typically, the number of metal particles parallel to the vertical direction is the greatest. As the angle becomes larger from the vertical direction, the metal particle count decreases. On the other hand, the portion of the metal layer 20 covering the inner surface 23s of the vertical contact hole is formed mainly of metal particles flying from an oblique direction because the projected area with respect to the vertical direction is small. Therefore, the thickness of the metal layer 20 at the inner side surface 23s of the vertical contact hole is smaller than the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer.
Further, the thickness of the metal layer 20 at the inner side surface 23s of the contact hole becomes smaller as it is away from the opening 23o of the contact hole. This is because the angle of the metal particles flying from the oblique direction with respect to the vertical direction increases as the opening 23o of the contact hole is separated, and the contribution of the metal particles decreases. Therefore, in the conventional semiconductor device, it is difficult for the metal layer 20 to have a sufficient thickness at the inner side surface 23s of the vertical contact hole.
Therefore, in the semiconductor device 100 of the present embodiment, the inclination of the inner surface 23s of the contact hole is made gentle with respect to the surface 11s of the semiconductor substrate. The more gradual the inclination, the larger the projected area with respect to the vertical direction becomes when the metal layer 20 is provided, the greater the contribution of the metal particles flying out from the vertical direction becomes. Therefore, the metal layer 20 is expected to have a sufficient thickness on the inner surface 23s of the contact hole.
In the example shown in fig. 1 and 2, in order to slow down the inclination of the inner side surface 23s of the contact hole, in a cross section perpendicular to the surface 11s of the semiconductor substrate, the inner side surface 23s of the contact hole faces the opening 23o of the contact hole, and has an angle smaller than 90 degrees with respect to the surface 11s of the semiconductor substrate. The thickness of the metal layer 20 at the inner side surface 23s of the contact hole is smaller than the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer. Further, the thickness of the metal layer 20 at the inner side surface 23s of the contact hole becomes smaller as it is away from the opening 23o of the contact hole. The reason for this is the same as the reason described above in the conventional semiconductor device.
In the example shown in fig. 1 and 2, the inner surface 23s of the contact hole has an inner surface 23s near the lower portion of the surface 11s of the semiconductor substrate 1 And an inner side surface 23s near the upper portion of the opening 23o of the contact hole 2 . Inner side surface 23s of lower portion of contact hole 1 An angle θ formed with the surface 11s of the semiconductor substrate is smaller than an inner side surface 23s of an upper portion of the contact hole 2 Angle with the surface 11s of the semiconductor substrateLittle->I.e. contact holesInner side surface 23s of lower part 1 Is inclined from the upper inner side surface 23s of the contact hole 2 Is slowly inclined. Angle theta, & gt>Corresponding to the tilt angle.
In the example shown in fig. 1 and 2, the inner side surface 23s of the lower portion of the contact hole 1 The thickness of the metal layer 20 is greater than the thickness of the inner side surface 23s of the upper portion of the contact hole 2 The thickness of the metal layer 20 is small. However, since the inclination of the lower portion is slower than in the case where the inclination of the upper portion and the lower portion is the same, the inner side surface 23s of the lower portion of the contact hole can be suppressed to some extent 1 The thickness of the metal layer 20 is reduced.
Hereinafter, the inner side surface 23s of the lower portion of the contact hole 1 The thickness of the metal layer 20 is described as the center. The thickness of the metal layer 20 at other portions is greater than the inner side surface 23s of the lower portion of the contact hole 1 The thickness of the metal layer 20 is large.
Fig. 3 shows an inner side surface 23s of a lower portion of a contact hole in the semiconductor device 100 according to the present embodiment 1 A graph showing an example of a graph of the relationship between the thickness of the metal layer 20 and the failure rate in the gate life reliability test. In the gate life reliability test of the present embodiment, the semiconductor element was sealed in a plastic package, and a voltage of 25V was applied to the gate electrode 18 while keeping the temperature in the plastic package at 175 degrees. The failure rate indicates a ratio of the semiconductor element in which the leakage current between the source and the drain increases in the case where the electrical characteristics are measured after being held for 1000 hours under such conditions. The increase in drain-to-source leakage current is due to the decrease in threshold voltage of the gate electrode in at least a portion of the lower portion of the gate electrode 18. The metal layer 20 has a double-layer structure in which an upper layer is made of TiN and a lower layer is made of Ti. The ratio of the thickness of the upper layer to the lower layer is typically 2:1.
As shown in fig. 3, the inner side surface 23s of the lower portion of the contact hole 1 The thickness of the metal layer 20 at this point becomes large, and the failure rate of the gate lifetime reliability test decreases. Gold at side 17s of gate insulating layer When the thickness of the sub-layer 20 is 35nm or more, the failure rate in the gate lifetime reliability test is almost 0%. That is, if at least the inner side surface 23s of the lower portion of the contact hole among the inner side surfaces 23s of the contact hole 1 The thickness of the metal layer 20 is 35nm or more, so that the variation of the threshold voltage of the gate can be suppressed in a high-temperature environment. Thereby, the reliability of the semiconductor device 100 is improved.
The thickness of the metal layer 20 at the side 17s of the gate insulating layer increases as the inclination of the side 17s of the gate insulating layer becomes gentle. The inner side surface 23s of the lower portion of the contact hole is defined by the angle θ 1 Is shown (see fig. 1). Hereinafter, the angle θ is referred to as "taper angle".
FIG. 4 shows an inner side surface 23s depicting the taper angle and the upper portion of the contact hole 2 A graph of an example of a graph of the relationship between the thicknesses of the metal layers 20. In the example shown in fig. 4, a case where a metal layer 20 having a thickness of 60nm is deposited on the upper surface 38u of the interlayer insulating layer as a flat portion and a case where a metal layer 20 having a thickness of 55nm is deposited are shown. As shown in fig. 4, it is clear that the taper angle increases from 0 ° and the inner side surface 23s of the upper portion of the contact hole 2 The thickness of the metal layer 20 is reduced. Further, it is understood that even if the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer as the flat portion varies, the relationship between the taper angle and the thickness of the metal layer 20 varies in substantially the same curve. The taper angle 0 ° indicates a case where the contact hole 23 is not formed, that is, a case where the portion of the interlayer insulating layer 38 where the metal layer 20 is deposited is parallel to the surface 11s of the semiconductor substrate. The thickness of the metal layer 20 at the taper angle 0 ° corresponds to the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer.
Fig. 5 is a diagram showing an example of a graph in which the thickness of the metal layer 20 is normalized with respect to the taper angle 0 ° in fig. 4 and is expressed as a coverage rate. The circles, diamonds, triangles represent cases where the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer as a flat portion is 60nm, 90nm, and 120nm, respectively. The black mark indicates the inner side surface 23s of the upper portion of the contact hole 2 Coverage at the point, grey marks indicate the inner side surface 23s of the lower portion of the contact hole 1 Coverage at the site.
As shown in fig. 5, the inner side surface 23s of the upper portion of the contact hole 2 The coverage at this point does not depend on the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer as a flat portion, but varies in a curve depending on the taper angle. On the other hand, it can be seen that the inner side surface 23s of the lower portion of the contact hole 1 Coverage ratio at the upper inner side surface 23s of the contact hole as described above 2 The coverage is small, i.e. the thickness of the metal layer 20 is at the inner side 23s of the lower part of the contact hole 1 At a position higher than an inner side surface 23s at an upper portion of the contact hole 2 Thin. An inner side surface 23s of an upper portion of the contact hole 2 Lower inner side surface 23s 1 The metal layer 20 at this point exhibits approximately the same variation with respect to the taper angle. Therefore, the inner side surface 23s of the upper portion of the contact hole among the inner side surfaces 23s of the contact hole 2 Lower inner side surface 23s 1 Both of these can thicken the metal layer 20 by reducing the taper angle.
In the example shown in fig. 1 and 2, the inner side surface 23s of the lower portion of the contact hole is formed 1 The thickness of the metal layer 20 is 35nm or more, and there are a method of reducing the taper angle and a method of thickening the deposited metal layer 20.
In the conventional semiconductor device, the taper angle can be smaller than 90 ° in practice. However, if the inclination of the inner side surface 23s of the contact hole is not intentionally made gentle, a taper angle of, for example, 85 ° or less smaller than 90 ° cannot be achieved.
In addition, in the case where the taper angle is 90 °, the inner side surface 23s is located at the lower portion of the contact hole 1 Since the coverage is 25%, the thickness of the metal layer 20 on the upper surface 38u of the interlayer insulating layer as the flat portion may be 140nm (=35 nm/0.25) or more. However, the thickness of the metal layer 20 acts as a series resistance on a path through which a current of the semiconductor device flows. Therefore, there is a side effect that an increase in resistance occurs. In general, when a part of the aluminum layer that is the source wiring 19 is removed by etching, the metal layer 20 located under the source wiring 19 is also removed by dry etching. However, if the metal layer 20 is thick, there is a side effect that dry etching of the metal layer 20 becomes difficult . Therefore, it is preferable that the increase in thickness of the metal layer 20 is small.
In the experiments of the present inventors, the taper angle that can be controlled was 70 °. Considering the tolerance and the deviation in production, it is sufficient to know that the thickness of the metal layer 20 is set to 75 ° with respect to the taper angle. In this sense, a taper angle of 75 ° or less can be an index for suppressing threshold variation of the gate electrode in a high-temperature environment.
In the case of the taper angle of 75 °, the coverage becomes 35%. Therefore, the thickness of the metal layer 20 at the upper surface 38u of the interlayer insulating layer as the flat portion may be 100nm (=35 nm/0.35) or more. It is known that if the thickness of the metal layer 20 is about 100nm, the metal layer 20 at the upper surface 38u of the interlayer insulating layer can be removed by adjusting the overetching amount when the source wiring 19 is removed by etching, and the increase in series resistance is small.
Next, a method for manufacturing the semiconductor device 100 in this embodiment will be described. Hereinafter, the same steps as those in the conventional process may be omitted.
Fig. 6A to 6J are diagrams schematically showing an example of a manufacturing process of the semiconductor device 100 in the present embodiment.
The manufacturing process of the semiconductor device 100 in this embodiment includes the following steps.
In the first step shown in fig. 6A, a semiconductor substrate 11 is prepared. The semiconductor substrate 11 may be provided by epitaxial growth of a semiconductor. Although not shown, the first step includes a step of forming a predetermined region on the semiconductor substrate 11 by masking, a step of implanting impurities into the predetermined region, and a step of activating the impurities by heat treatment, similarly to a general method for manufacturing a silicon carbide semiconductor device. Thereby, a body region, a contact region connecting the body region, a source region, and the like are formed.
In the second step shown in fig. 6B, a gate insulating layer 17 is provided on the surface 11s of the semiconductor substrate. The gate insulating layer 17 may be provided by thermally oxidizing the surface 11s of the semiconductor substrate, or may be provided by depositing an insulating layer on the surface 11s of the semiconductor substrate.
In the third step shown in fig. 6C, a gate electrode 18 is provided on the gate insulating layer 17. The gate electrode 18 may be provided by patterning a conductive layer formed of polysilicon or a metal material.
In the fourth step shown in fig. 6D, the gate electrode 18 is covered with the interlayer insulating layer 38. The surface 38su of the interlayer insulating layer has a flat portion 38fl and an inclined portion 38sl in a region immediately below the gate insulating layer 17.
In the fifth step shown in fig. 6E, the mask layer 31 is provided on the interlayer insulating layer 38. The mask layer 31 includes an opening 31o for defining the contact hole 23. In the opening 31o of the mask layer, a flat portion 38fl and an inclined portion 38sl are present. The mask layer 31 may also be provided by patterning a photo-etchant.
In the sixth step shown in fig. 6F, the interlayer insulating layer 38 and the gate insulating layer 17 are etched using the mask layer 31, whereby the contact hole 23 exposing a part of the surface 11s of the semiconductor substrate is provided. As described above, the inner side surface 23s of the contact hole is defined by the side surface 38s of the interlayer insulating layer and the side surface 17s of the gate insulating layer. As the etching gas, CHF is used, for example 3 、CF 4 And a mixed gas of Ar. After etching was performed in the chamber for 60 seconds, the etching was stopped and the chamber was cooled while allowing the gas to flow for 60 seconds. The contact hole 23 is provided by repeating this operation.
In the seventh step shown in fig. 6G, the mask layer 31 is removed.
In the eighth step shown in fig. 6H, a part of the surface 11s of the semiconductor substrate exposed through the contact hole 23 is covered with a metal such as Ni, and an annealing treatment is performed to form the silicide layer 21.
In the ninth step shown in fig. 6I, a metal layer 20 is provided, and the metal layer 20 covers at least a part of the silicide layer 21, the upper surface 38u of the interlayer insulating layer, the inner side surface 23s of the contact hole, and the metal layer. The metal layer 20 may also be provided by sputtering a metal.
In a tenth step shown in fig. 6J, the source wiring 19 is provided to be connected to a portion of the metal layer 20 that covers at least the portion of the silicide layer 21 via the contact hole 23.
Next, the reason why the inner side surface 23s of the contact hole has two different inclinations will be described.
As shown in fig. 6E, a level difference is generated on the surface 38su of the interlayer insulating layer by the flat portion 38fl and the inclined portion 38 sl. The etching method is different depending on the level difference. Therefore, as shown in fig. 6F, the inner surface 23s of the contact hole includes the lower inner surface 23s 1 An upper inner side surface 23s 2 . Inner side surface 23s of lower portion of contact hole 1 Is inclined at an angle greater than the inner side surface 23s of the upper portion of the contact hole 2 Is small. This is caused by the fact that the inclination angle of the flat portion 38fl is 0 °, and the inclination angle of the inclined portion 38sl is large to some extent.
In the manufacturing method of the present embodiment, it is not necessary to additionally increase an etching step in order to provide the inclination to the inner side surface 23s of the contact hole. The inner side surface 23s of the contact hole is provided with an inclination only by the sixth step shown in fig. 6F. Therefore, the metal layer 20 can be provided with a sufficient thickness on the inner surface 23s of the contact hole in the same number of steps as in the conventional manufacturing method. This can suppress the variation in threshold voltage of the gate electrode in a high-temperature environment. As a result, the reliability of the semiconductor device 100 is improved.
In the conventional manufacturing method, in order to make the inner surface 23s of the contact hole almost perpendicular to the surface 11s of the semiconductor substrate, only the flat portion 38fl is exposed in the mask layer 31 in the fifth step shown in fig. 6E.
Next, the relationship between the wafer in-plane uniformity of the etching rate and the taper angle when the interlayer insulating layer 38 is etched will be described. The in-wafer uniformity of the etching rate is defined by a value obtained by dividing the difference between the maximum value and the minimum value in the etching rate at a plurality of positions in the wafer plane by 2 times the average value of all the points.
Fig. 7 is a graph showing an example of a graph depicting the relationship between the wafer in-plane uniformity of the etching rate and the taper angle in the case where a 6-inch wafer is used for etching the interlayer insulating layer 38 in fig. 6F. Various indications shown in FIG. 7 indicate changes in the flow rate and pressure of the etching gasForce or electric power, etc. The results shown in fig. 7 are experimental results when etching a flat substrate. Therefore, the taper angle shown in FIG. 7 is equivalent to the inner side surface 23s of the upper portion of the contact hole 2 Inclination angle at (c).
As shown in fig. 7, when the etching time is 150 seconds, which is the time during which the interlayer insulating layer 38 can be etched together, the wafer in-plane uniformity of the etching rate and the taper angle are inversely related to each other. That is, a small taper angle and good uniformity cannot be achieved at the same time.
Therefore, the inventors examined the relationship between the in-wafer distribution of etching rate and etching time.
Fig. 8 is a graph showing an example of a graph depicting the relationship between the measured position and the etching rate in a 6-inch wafer at various etching times. As shown in fig. 8, it is seen that as the etching time becomes longer, the etching rate decreases, and the variation in the etching rate in the wafer plane becomes larger. Further, it is also known that if the etching time is 60 seconds or less, deterioration of the in-wafer uniformity of the etching rate can be suppressed. This is mainly due to the fact that when the interior of the etching chamber is overheated by discharge and products are deposited on the side wall of the etching chamber, the deposition amount of the products varies according to the etching time.
In the example shown in fig. 7, the relationship between the wafer in-plane uniformity of the etching rate and the taper angle at this time is shown in the case where the etching time is 60 seconds as understood from fig. 8. By setting the etching time to 60 seconds, the taper angle of 70 ° and the in-wafer uniformity of a good etching rate of 5% or less can be simultaneously achieved.
In the etching time of 60 seconds, the interlayer insulating layer 38 cannot be entirely etched. Accordingly, the inventors have found that an etching method having a low taper angle and good uniformity can be simultaneously achieved even when the interlayer insulating layer 38 is thick by repeating the etching step for 60 seconds and the cooling step for cooling while stopping the discharge while holding the wafer in the etching chamber. This makes it possible to realize a highly reliable and high-quality semiconductor device 100 in which variations in the threshold voltage of the gate electrode in a high-temperature environment are suppressed.
Industrial applicability
The semiconductor device and the method for manufacturing the same in this embodiment mode can be applied to applications such as power devices.

Claims (12)

1. A semiconductor device is provided with:
a semiconductor substrate;
a gate insulating layer located on the surface of the semiconductor substrate;
a gate electrode on the gate insulating layer;
an interlayer insulating layer having a single-layer structure covering the gate electrode;
a contact hole penetrating the gate insulating layer and the interlayer insulating layer to expose a part of the surface of the semiconductor substrate, the contact hole having an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
a metal layer covering an upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and at least a portion of the surface of the semiconductor substrate exposed; and
a source wiring connected to a portion of the metal layer covering at least the at least a portion of the surface of the semiconductor substrate exposed through the contact hole,
the thickness of the metal layer at least covering the portion of the inner side surface of the contact hole near the surface of the semiconductor substrate is 35nm or more,
In a cross section perpendicular to the surface of the semiconductor substrate, the inner side surface of the contact hole is a part of an opening of the contact hole,
the inner side face of the contact hole has a first inner side face including a portion of a side face of the interlayer insulating layer and a side face of the gate insulating layer, and a second inner side face farther from the surface of the semiconductor substrate than the first inner side face,
a first angle formed by the first inner side surface of the contact hole and the surface of the semiconductor substrate is smaller than a second angle formed by the second inner side surface of the contact hole and the surface of the semiconductor substrate,
the first angle is 75 degrees or less.
2. The semiconductor device according to claim 1, wherein,
the thickness of the portion of the metal layer covering the inner side surface of the contact hole near the surface of the semiconductor substrate is set to a first thickness,
when the thickness of the portion of the metal layer covering the upper surface of the interlayer insulating layer is set to a second thickness, the first thickness is 35% or more of the second thickness.
3. A semiconductor device is provided with:
A semiconductor substrate;
a gate insulating layer located on the surface of the semiconductor substrate;
a gate electrode on the gate insulating layer;
an interlayer insulating layer having a single-layer structure covering the gate electrode;
a contact hole penetrating the gate insulating layer and the interlayer insulating layer to expose a part of the surface of the semiconductor substrate, the contact hole having an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
a metal layer covering an upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and at least a part of the exposed portion of the surface of the semiconductor substrate; and
a source wiring connected to a portion of the metal layer covering at least the at least a portion of the surface of the semiconductor substrate exposed through the contact hole,
in a cross section perpendicular to the surface of the semiconductor substrate, the inner side surface of the contact hole faces an opening portion of the contact hole,
the inner side face of the contact hole is provided with a first inner side face close to the surface of the semiconductor substrate and a second inner side face close to the opening portion of the contact hole, the first inner side face includes a part of a side face of the interlayer insulating layer and a side face of the gate insulating layer,
A first angle formed by the first inner side surface of the contact hole and the surface of the semiconductor substrate is smaller than a second angle formed by the second inner side surface of the contact hole and the surface of the semiconductor substrate,
the first angle is 75 degrees or less.
4. The semiconductor device according to claim 1 or 3, wherein,
the portion of the surface of the semiconductor substrate exposed is a silicide layer formed of silicide.
5. The semiconductor device according to claim 4, wherein,
a portion of the silicide layer covers the side of the gate insulating layer.
6. The semiconductor device according to claim 1 or 3, wherein,
the metal layer has a double layer structure formed of two different metals.
7. The semiconductor device according to claim 1 or 3, wherein,
the semiconductor device is a MOSFET.
8. A method of manufacturing a semiconductor device, comprising:
a first step of preparing a semiconductor substrate;
a second step of providing a gate insulating layer on the surface of the semiconductor substrate;
a third step of providing a gate electrode on the gate insulating layer;
a fourth step of covering the gate electrode with an interlayer insulating layer having a single-layer structure;
A fifth step of providing a mask layer on the interlayer insulating layer;
a sixth step of forming a contact hole by etching the interlayer insulating layer and the gate insulating layer using the mask layer, the contact hole exposing a part of the surface of the semiconductor substrate and having an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
a seventh step of removing the mask layer;
an eighth step of forming a silicide layer by performing an annealing treatment while covering the part of the surface of the semiconductor substrate exposed through the contact hole with a metal;
a ninth step of providing a metal layer covering an upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and at least a part of the silicide layer; and
a tenth step of providing a source wiring connected to a portion of the metal layer covering at least the portion of the silicide layer via the contact hole,
the metal layer has a thickness of 35nm or more at least in a portion covering a lower portion of the inner side surface of the contact hole,
in a cross section perpendicular to the surface of the semiconductor substrate, the inner side surface of the contact hole is a part of an opening of the contact hole,
The inner side face of the contact hole has a first inner side face including a portion of a side face of the interlayer insulating layer and a side face of the gate insulating layer, and a second inner side face farther from the surface of the semiconductor substrate than the first inner side face,
a first angle formed by the first inner side surface of the contact hole and the surface of the semiconductor substrate is smaller than a second angle formed by the second inner side surface of the contact hole and the surface of the semiconductor substrate,
the first angle is 75 degrees or less.
9. A method of manufacturing a semiconductor device, comprising:
a first step of preparing a semiconductor substrate;
a second step of providing a gate insulating layer on the surface of the semiconductor substrate;
a third step of providing a gate electrode on the gate insulating layer;
a fourth step of covering the gate electrode with an interlayer insulating layer having a single-layer structure;
a fifth step of providing a mask layer on the interlayer insulating layer;
a sixth step of forming a contact hole by etching the interlayer insulating layer and the gate insulating layer using the mask layer, the contact hole exposing a part of the surface of the semiconductor substrate and having an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer;
A seventh step of removing the mask layer;
an eighth step of forming a silicide layer by performing an annealing treatment while covering the part of the surface of the semiconductor substrate exposed through the contact hole with a metal;
a ninth step of providing a metal layer covering an upper surface of the interlayer insulating layer, the inner side surface of the contact hole, and at least a part of the silicide layer;
a tenth step of providing a source wiring connected to a portion of the metal layer covering at least the portion of the silicide layer via the contact hole,
in a cross section perpendicular to the surface of the semiconductor substrate, the inner side surface of the contact hole faces an opening portion of the contact hole,
the inner side face of the contact hole is provided with a first inner side face close to the surface of the semiconductor substrate and a second inner side face close to the opening portion of the contact hole, the first inner side face includes a part of a side face of the interlayer insulating layer and a side face of the gate insulating layer,
a first angle formed by the first inner side surface of the contact hole and the surface of the semiconductor substrate is smaller than a second angle formed by the second inner side surface of the contact hole and the surface of the semiconductor substrate,
The first angle is 75 degrees or less.
10. The method for manufacturing a semiconductor device according to claim 9, wherein,
the surface of the interlayer insulating layer covering the gate electrode in the fourth step includes a flat portion and an inclined portion, the mask layer in the fifth step includes an opening portion for defining the contact hole,
within the opening portion of the mask layer, the flat portion and the inclined portion in the surface of the interlayer insulating layer are present.
11. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein,
in the sixth step, CHF is used 3 、CF 4 And Ar.
12. The method for manufacturing a semiconductor device according to claim 11, wherein,
in the sixth step, the step of performing the etching for 60 seconds and the step of cooling after the etching are repeated.
CN201811375094.5A 2017-11-28 2018-11-19 Semiconductor device and method for manufacturing the same Active CN109841685B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017227649A JP7054797B2 (en) 2017-11-28 2017-11-28 Semiconductor devices and their manufacturing methods
JP2017-227649 2017-11-28

Publications (2)

Publication Number Publication Date
CN109841685A CN109841685A (en) 2019-06-04
CN109841685B true CN109841685B (en) 2024-03-12

Family

ID=66632714

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811375094.5A Active CN109841685B (en) 2017-11-28 2018-11-19 Semiconductor device and method for manufacturing the same

Country Status (3)

Country Link
US (1) US10439034B2 (en)
JP (1) JP7054797B2 (en)
CN (1) CN109841685B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365932B1 (en) * 1999-08-20 2002-04-02 Denso Corporation Power MOS transistor
CN102610639A (en) * 2010-11-25 2012-07-25 三菱电机株式会社 Semiconductor device
CN106463541A (en) * 2014-05-23 2017-02-22 松下知识产权经营株式会社 Silicon carbide semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476915A (en) * 1990-07-19 1992-03-11 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US5940732A (en) * 1995-11-27 1999-08-17 Semiconductor Energy Laboratory Co., Method of fabricating semiconductor device
JP3842852B2 (en) * 1995-11-27 2006-11-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4260334B2 (en) * 1999-03-29 2009-04-30 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
TW546846B (en) * 2001-05-30 2003-08-11 Matsushita Electric Ind Co Ltd Thin film transistor and method for manufacturing the same
US7696024B2 (en) * 2006-03-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP6168732B2 (en) * 2012-05-11 2017-07-26 株式会社日立製作所 Silicon carbide semiconductor device and manufacturing method thereof
JP6296970B2 (en) * 2014-12-12 2018-03-20 三菱電機株式会社 Semiconductor device and manufacturing method thereof
WO2016114057A1 (en) * 2015-01-16 2016-07-21 富士電機株式会社 Silicon carbide semiconductor device and method for producing silicon carbide semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365932B1 (en) * 1999-08-20 2002-04-02 Denso Corporation Power MOS transistor
CN102610639A (en) * 2010-11-25 2012-07-25 三菱电机株式会社 Semiconductor device
CN106463541A (en) * 2014-05-23 2017-02-22 松下知识产权经营株式会社 Silicon carbide semiconductor device

Also Published As

Publication number Publication date
US10439034B2 (en) 2019-10-08
JP7054797B2 (en) 2022-04-15
US20190165119A1 (en) 2019-05-30
JP2019096848A (en) 2019-06-20
CN109841685A (en) 2019-06-04

Similar Documents

Publication Publication Date Title
US9356138B2 (en) Semiconductor device
JP4180800B2 (en) Super self-aligned trench DMOSFET with reduced on-resistance
US7838946B2 (en) Method for fabricating semiconductor structure and structure of static random access memory
EP2015364A2 (en) SiC semiconductor device with BPSG insulation film and method for manufacturing the same
US11145711B2 (en) Capacitor and method for manufacturing capacitor
KR101047947B1 (en) Trench Metal Oxide Semiconductor
TWI502742B (en) Semiconductor device formed on semiconductor substrate having substrate top surface and preparation method thereof
US11063123B2 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
JP2004266140A (en) Semiconductor device and its manufacturing method
US8420421B2 (en) Method for fabricating a GaN-based thin film transistor
CN111613665A (en) Semiconductor device and method for manufacturing the same
US10763329B2 (en) Semiconductor device
CN107403838B (en) Power metal oxide semiconductor field effect transistor
TW201947766A (en) High electron mobility transistor
US20200251565A1 (en) Gate structure of split-gate metal oxide semiconductor field effect transistor and manufacturing method thereof
US9640438B2 (en) Integrated circuits with inactive gates and methods of manufacturing the same
CN109841685B (en) Semiconductor device and method for manufacturing the same
JP2004288890A (en) Silicon carbide semiconductor device
US10032894B2 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
JP4878739B2 (en) Manufacturing method of semiconductor device
US20230261084A1 (en) Fabrication method of forming silicon carbide mosfet
US11469175B2 (en) Semiconductor device with programmable unit and method for fabricating the same
JP6926261B2 (en) Semiconductor devices and their manufacturing methods
US20230178663A1 (en) Semiconductor device and method for manufacturing semiconductor device
US10644166B2 (en) Method for forming semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant