CN109840215A - The processing of unjustified write-in - Google Patents

Abstract

Entitled " processing of unjustified write-in " of the invention.The invention discloses a kind of one or more control circuits of storage system, one or more of control circuits of the storage system are configured as merging sensing and transmission, wherein sensing for for the pre-filled of unjustified writing commands and/or after fill data, be transmitted as previous sensor another unjustified writing commands pre-filled and/or after fill data.By merging the sensing and the transmission, a large amount of time is saved when the data to one group of two or more unjustified writing commands are programmed.In addition, in one aspect, executing single programming operation to multiple unjustified writing commands.Some conventional solutions may need to execute programming operation to each unjustified writing commands.Therefore, the storage system saves a large amount of programming time.In addition, the storage system can reduce write-in amplification.

Description

The processing of unjustified write-in

Background technique

When host device is written data and reads data from memory device to memory device, host is according to logical block address (LBA) be written and read data.Master data transmission unit between host and memory device is referred to herein as " sector ". " basic unit " means the minimum data transmission size of read or write command.Therefore, read or write request be read or The request of the sector of some integer amounts is written.The size of sector can be between a specific implementation and next specific implementation Have a difference, but sector-size another example is 512 bytes.It may be noted that as used herein, term " sector " does not refer to hard disk Physical sector etc. on driver.It is further noted that the corresponding sector each LBA.

Memory device usually has storage control, which is converted to LBA the storage list on memory device The physical address of member.For example, flush memory device, which has, executes logical address to the flash memory transport layer (FTL) of physical address translations or matchmaker Body management level (MML).

Before writing data into storage unit, storage control usually forms code word by the data from host.Code word Including host data and one or more parity check bits.The quantity of parity check bit can have difference according to the intensity of error correction. Code word is referred to herein as " ECC page face ".ECC page face is formed by one or more both host data sectors.For example, ECC page face can To be formed by four both host data sectors.Therefore, if sector-size is 512 bytes, ECC page face may include 2K byte Host data, outer Parity bits.ECC page face is the programming unit in memory device.

Storage control has smallest addressable unit, is usually one or more ECC pages face.Therefore, minimum can be sought Location unit corresponds to the sector of some quantity.Terms used herein " segment ", which in this article refers to the minimum in memory device, to seek Location storage unit.For example, smallest addressable unit is 4kB (assuming that fan if smallest addressable unit is two ECC page faces Area is sector there are four 512 bytes and each ECC page faces).

Herein, alignment write-in is defined as wherein originating LBA and size of data is the multiple of number of sectors in segment Write-in.For example, if there is eight sectors in segment, the starting LBA that being aligned write-in has is eight multiple, and it has Size of data is the integral multiple of eight sectors.

It herein, is not that the write-in that alignment is written is known as unjustified write-in.Therefore, unjustified write-in: the 1) starting having LBA is not the multiple of sector number in segment；Or 2) size of data having is not the multiple of sector number in segment.

When host sends alignment writing commands, storage tube can be written simply as one or more segments in data Core.However, when host sends unjustified writing commands, storage control need pre-filled and/or rear filling host data with It is formed " align data ".Align data means to form complete segment.Storage control may need to read from storage unit It is pre-filled and/or after fill data.Therefore, storage control may need to be implemented read-modify-write.Read-modify-is write Enter refer to from storage tube core on storage unit read it is pre-filled and/or after fill data, form the segment of align data, and By the segment write-in storage tube core of align data.

Executing read-modify-write may be very time-consuming.It is put in addition, executing read-modify-write and can increase write-in Greatly.Write-in amplification means that the data volume for being actually written into memory device is greater than the data volume for the host to be written.Write-in amplification can To shorten the service life of memory device.

Detailed description of the invention

Figure 1A is the block diagram for being shown connected to an embodiment of memory device for host device.

Figure 1B is the perspective view for the nonvolatile semiconductor memory member that three-dimensional (3D) is stacked.

Fig. 1 C is the functional block diagram of the 3D stacked non-volatile memory part of exemplary storage device such as Figure 1B.

Fig. 2 is the block diagram of exemplary memory system, shows the more details of an embodiment of controller.

Fig. 3 A show for communicating between storage tube core to N of controller and each memory package 0 N+1 deposit Reservoir encapsulation (encapsulation 0 to encapsulation N) and N+1 channel (channel 0 to channel N).

Fig. 3 B is the block diagram for showing an embodiment of sensing block SB1 of Fig. 1 C.

Fig. 4 A shows the exemplary structure of memory cell array.

Fig. 4 B shows an example for having dihedral storage tube core.

Fig. 5 illustrate how to carry out the data of the unjustified writing commands in data buffer it is pre-filled and/or after fill out It is filled with to form complete segment.

Fig. 6 is the flow chart for handling the process of unjustified writing commands.

Fig. 7 is the flow chart of an embodiment of the process for the align data to form unjustified writing commands.

Fig. 8 is the figure of the timing in the embodiment shown for the programming data of multiple unjustified writing commands.

Fig. 9 is that the mistake for handling unjustified writing commands is executed during the folding from SLC storage unit to MLC memory cell The flow chart of one embodiment of journey.

Specific embodiment

This document describes memory device and its application methods.Such memory device may include flash memory (non-volatile memories Device), random access memory (RAM), and the storage control communicated with flash memory and RAM.According to some implementations of this technology Scheme, one or more control circuits of storage system be configured as merge sensing and transmission, wherein sensing for for one not Alignment writing commands pre-filled and/or after fill data, be transmitted as another unjustified writing commands for previous sensor It is pre-filled and/or after fill data.By merging sensing and transmission, to one group of two or more unjustified writing commands Data save a large amount of time when being programmed.Moreover, in one embodiment, the number of multiple unjustified writing commands According to being typically programmed simultaneously.Some conventional solutions may need to execute programming operation to each unjustified writing commands.Some In embodiment, only for one group, two or more unjustified writing commands execute a programming operation.Therefore, it is by storage The embodiment of system saves a large amount of programming time.Moreover, by the number for reducing programming operation, by the implementation of storage system Scheme saves sizable power.In addition, write-in amplification can be reduced by the embodiment of storage system.It therefore, can be with Extend the service life of storage system.

In the following detailed description, with reference to the attached drawing of a part for forming this specification, and in the accompanying drawings with illustration Mode shows specific exemplary implementation scheme.It should be appreciated that other embodiments can be used, and machinery can be carried out With electrical change.Therefore, described in detail below to be not be considered in a limiting sense.In the following description, identical number Or reference label will be used to indicate identical component or element throughout.In addition, first number of three digital reference numbers The first two number of word and four digit reference numerals mark first appears the attached drawing of the reference label.

Figure 1A is a reality for being shown connected to the storage system 100 of host device 140 (or in insertion host device 140) Apply the block diagram of scheme, the embodiment that this technology described below may be implemented in the host device.With reference to Figure 1A, host device 140 are stored data into storage system 100 by sending write-in and reading order and retrieve number from storage system 100 According to.Storage system 100 can be embedded in host device 140, or can be can be removed by mechanical connector and electric connector Ground is connected to the card of host device 140, universal serial bus (USB) driver or other removable driver such as solid-state disks (SSD) form exists.Host device 140 can be many fixations or portable data generating device such as personal computer, Appoint whichever in smart phone, personal digital assistant (PDA), server, set-top box etc..More generally, host device 140 can be with Host logic including executing the function of smart phone, PDA, laptop computer, server, set-top box etc..Although not having Body is shown, but host may include read-only memory (ROM) and/or communicate with read-only memory.

The host device 140 of host 140 can be more compactly known as may include one or more host-processors 10.It is main Machine processor can run one or more application program.When will in storage system 100 storing data or from the storage system When retrieving data, application program passes through one or more operating system application programming interfaces (API) and file system carries out Communication.File system can be the software module executed on processor 10, and manage the file in storage system 100.File Data clustering in system administration logical address space.Include creation by the common operation that file system executes, open, write-in (storage) data, search for specific location, movement, duplication and the operation for deleting file at reading (retrieval) data hereof.File System can be the combination of circuit, software or circuit and software.

Communication channel 56 between host 140 and storage system 100 can be used for transmitting order, data etc..For by logical The interface that letter channel 56 is communicated can be many known interfaces such as secure data (SD), multimedia card (MMC), general string It is any in row bus (USB) memory device, Serial Advanced Technology Attachment (SATA) and small computer system interface (SCSI) Person.Host 140 can safeguard the ranges of logical addresses for distributing to all logical block address (LBA) of data via host 140. Other than for referring to the communication channel between host 140 and storage system 100, reference label 56 can be also used for referring to logical Cross the host interface signals of the transmission of communication channel 56.

Host 140 carrys out the file stored in addressable storage system 100 using file system, this can be related to writing data into The nonvolatile memory 126 of storage system 100 simultaneously reads data from the nonvolatile memory of the storage system.It can be by leading The file system for the exemplary types that machine 140 uses includes but is not limited to FAT32, exFAT, ext2/3, HFS+.Storage system 100 are usually designed to and work together with different types of host, and difference can be used in each of different types of host The file system of type.This may cause storage system 100 makes to write due to the excessive pre-filled and/or rear filling of small block data It is poor to enter performance.

Storage system 100 includes that (it can also with the storage control 122 that tube core 108 communicates is stored via communication interface 118 With referred to as controller 122).Communication interface 118 can be any suitable interface, such as open nand flash memory (ONFI) interface. Controller 122 has processor 122c and volatile memory 122b.Volatile memory 122b can be used for store command queue 32, the command queue is for storing the order from host 10.These orders may include memory access command, such as read It takes, be written or wipe.In some embodiments, what controller 122 can select the order in queue 32 executes sequence.It is volatile Property memory 122b a part can be used for data buffer 34, which can be used for storing from host 140 Data these data to be programmed into memory 126.Data buffer 34 can be also used for storage and read from memory 126 Data these data are transferred to host 140.

A part of volatile memory 122b can be used for storing logic, and to the caches of physical mappings, (L2P high speed is slow Deposit 36) and physics to logical mappings cache (P2L cache 38).Logic can be used to physics in controller 122 Map the storage list logical block address in the memory access command from host 140 being mapped in storage organization 126 The physical address of member.For example, logical block address (LBA) may map to physical block address (PBA).It is such mapping can be used for by LBA, which maps directly to PBA or LBA, may map to the centre for being mapped to PBA or virtual block address.

Storing tube core 108 has storage organization 126.Storage organization 126 is for storing host data 50.Storage organization 126 It is also used to storage management table 60.Management table may include L2P table 66 and P2L table 68.It may be noted that LTP cache 36 is L2P table 66 cache, and P2L cache 38 is the cache of P2L table 68.

Storing tube core 108 has one group of sensing data register 40, can be used for storing the data sensed from storage unit. Sensing data register 40 can also be used in the data that storage will be programmed into storage unit.In one embodiment, number is sensed It is data latches according to register 40.Storing tube core 108 has one group of I/O register 42, can be used for storing from storage control The data of device 122 processed are with by these data write storage units.I/O register 42 can be also used for storage and read from storage unit Data these data are transferred to data buffer 34.In one embodiment, I/O register 42 is that data latch Device.

When storage organization 126 is written, data can be transferred to data buffer 34 from mainframe memory 20.Storage control Data can be transferred to I/O data register 42 from data buffer 34 by device 122.Then I/O data register will can be come from The data of device 42 are transferred to sensing data register 40.Then can future self-inductance measurement data register 40 data be programmed into and deposit In storage unit in storage structure 126.It may be noted that the details that parity check bit is such as added to host data is not described, To simplify explanation.

When reading storage organization 126, the data of the storage unit in storage organization 126 can be sensed and put Enter to sense in data register 40.Then can future self-inductance measurement data register 40 data be transferred to I/O data register 42.Then the data in I/O data register 42 can be transferred to data buffer 34.It then can be by data buffer 34 In data be transferred to mainframe memory 20.It may be noted that not describing such as to entangle the data execution read from storage organization 126 Wrong details, to simplify explanation.

In some embodiments disclosed herein, storage control 122 checks that command queue 32 is autonomous with the presence or absence of coming The unjustified write-in of machine 140.Unjustified write-in includes at least one data sector from host, but not completely filled data are slow Rush the segment in device 34.Storage control 122 to storage tube core send order with provide the pre-filled of unjustified write-in and/or after It fills data and referred to herein as forms align data to form complete segment.In addition, storage system 100 merges sensing With transmission, wherein sensing for for the pre-filled of unjustified writing commands and/or after fill data, be transmitted as previous Another unjustified writing commands pre-filled of sensing and/or after fill data.For example, working as a unjustified writing commands Sensing data write-in sensing data register 40 in when, the filling data of the previous sensor of another unjustified writing commands from I/O data register 42 is transferred to data buffer.By merging sensing and transmission, in one group of processing, two or more are right The a large amount of time is saved when the data of neat writing commands.

In one embodiment, the segment of multiple unjustified writing commands is sent storage tube by storage control 122 Segment is stored in I/O data register 42 by core 108, the storage tube core first.Then these segments are transferred to sensing number According to register 40, wherein they can be used for being programmed the storage unit in storage organization 126.In one embodiment, Segment for multiple unjustified writing commands is typically programmed simultaneously.Some conventional solutions may need unjustified to write to each Enter order and executes programming operation.Therefore, a large amount of programming time is saved.Furthermore, it is possible to reduce write-in amplification.

Figure 1B to Fig. 4 describes an example of the storage system 100 that can be used for realizing technology proposed in this paper.Figure 1B is The perspective view for the nonvolatile semiconductor memory member that three-dimensional (3D) is stacked.Memory device 100 includes substrate 101.On substrate and substrate Top is the illustrated blocks BLK0 and BLK1 of storage unit (non-volatile memory device).There are also peripheral region on substrate 101 104, there are the support circuits used for block.Substrate 101 can also be held in block below along with one or more lower metal layers Circuit is carried, these metal layers are patterned to the signal of bearer circuit in conductive path.Block is formed in the centre of memory device In region 102.In the upper area 103 of memory device, one or more upper metallization layers are patterned in conductive path With the signal of bearer circuit.Each piece includes the stack region of storage unit, wherein the alternate level stacked indicates wordline.Although showing Two blocks are gone out as an example, the extra block extended along the direction x and/or y still can be used.

In an exemplary specific implementation, the length of plane in the x direction indicates the side that the signal path of wordline extends To (wordline or SGD line direction), and the direction (bit line that the signal path of the width means bit line of plane in y-direction extends Direction).The height of the direction z expression memory device.

Fig. 1 C is the functional block diagram of the 3D stacked non-volatile memory part 100 of exemplary storage device such as Figure 1B.Figure Component shown in 1C is circuit.Memory device 100 includes one or more storage tube cores 108.Each storage tube core 108 includes Three-dimensional storage organization 126 (for example, 3D array of storage unit), control circuit 110 and the read/write circuits of storage unit 128.In other embodiments, the two-dimensional array of storage unit can be used.Storage organization 126 can pass through row decoder 124 It is addressed by wordline, and is addressed by column decoder 132 by bit line.Read/write circuits 128 include multiple sensing blocks 150, the sense Survey block include SB1, SB2 ..., SBp (sensing circuit) and allow that one page storage unit is read or programmed parallel.One In a little systems, controller 122 is included in identical with one or more storage tube cores 108 memory device 100 (for example, moving Storage card) in.However, controller can be separated with storage tube core 108 in other systems.In some embodiments, it controls Device 122 will be located on the tube core different from storage tube core 108.In some embodiments, a controller 122 will be deposited with multiple Tube core 108 is stored up to communicate.In other embodiments, each storage tube core 108 has the controller of their own.Order and data warp It is transmitted between host 140 and controller 122 by data/address bus 120, and via line 118 in controller 122 and one or more It is transmitted between a storage tube core 108.In one embodiment, storage tube core 108 includes one group of input for being connected to line 118 And/or output (I/O) pin.

Storage organization 126 may include one or more memory cell arrays, one or more of memory cell arrays Including 3D array.Storage organization may include whole three-dimensional storage organization, and plurality of storage level is formed in single substrate such as Above chip (rather than wherein), without intermediate substrate.Storage organization may include being integrally formed in memory cell array One or more physical levels in any kind of nonvolatile memory, the memory cell array have be arranged in silicon substrate The active region of top.Storage organization can be in nonvolatile semiconductor memory member, which has and storage The associated circuit of the operation of unit, no matter associated circuit is square on substrate or in substrate.In an embodiment party In case, storage organization 126 realizes three dimensional NAND flash memory.Other embodiments include two-dimentional nand flash memory, two-dimentional NOR flash memory, ReRAM cross point memory, magnetoresistive memory (for example, MRAM), phase transition storage (for example, PCRAM) etc..

Control circuit 110 and read/write circuits 128 cooperate with executed on storage organization 126 storage operation (for example, Erasing, programming, reading etc.), and including state machine 112, on-chip address decoder 114, power control module 116.State machine 112 provide the die-level control of storage operation.In one embodiment, state machine 112 can be by software programming.In other implementations In scheme, state machine 112 is without using software and completely with hardware (for example, circuit) realization.In one embodiment, it controls Circuit 110 includes register, ROM fuse and other memory devices, for storing the default of such as reference voltage and other parameters Value.

On-chip address decoder 114 provides the address that host 140 or controller 122 use and decoder 124 and 132 uses Hardware address between address interface.The control of power control module 116 is supplied to wordline and bit line during storing operation Power and voltage.It may include for the driver of word line layer (being discussed below) of 3D configuration, selection transistor (under for example, The SGS and SGD transistor of text description) and source electrode line.Power control module 116 may include the charge pump for generating voltage. Sensing block includes bit line driver.SGS transistor is the selection gate transistor of the source terminal of NAND string, and SGD transistor is The selection gate transistor of the drain electrode end of NAND string.

Control circuit 110, decoder 114/124/132, power control module 116, sensing block 150, is read state machine 112 Take/any one of write circuit 128, controller 122, processor 122c and/or interface 122d or any combination can regard as Execute one or more control circuits of function described herein.

(on and off the chip) controller 122 (it is circuit in one embodiment) may include one or more processing Device 122c, ROM 122a, RAM 122b, memory interface 122d, all these is all interconnection.Other embodiments can make With state machine or it is designed to carry out other custom circuits of one or more functions.Memory device (ROM 122a, RAM It 122b) include code such as one group of instruction, and processor 122c can be operated to execute group instruction to provide and be described herein At least some of function.Alternatively or in addition to this, processor 122c can be from the memory device in storage organization (such as It is connected to the reservation region of the storage unit of one or more wordline) fetcher code.With ROM122a, RAM 122b and processor The memory interface 122d of 122c communication is circuit (electrical interface), controller 122 and one or more storage tube cores 108 it Between electrical interface is provided.For example, memory interface 122d can change signal format or timing, provide buffer, isolation surge, Latch I/O etc..Processor 122c can via memory interface 122d to control circuit 110 (or storage tube core 108 it is any its His component) issue order.

Multiple memory elements in storage organization 126 are configured such that they are connected in series or make each element It is individually accessible.As non-limiting example, the flush memory device in NAND configuration (nand flash memory) generally comprises series connection Memory element.NAND string is the storage unit of one group of series connection and the example of selection gate transistor.

Nand flash memory array is configured such that array is made of multiple NAND strings, and wherein NAND string is by shared single Multiple storage units of bit line constitute and as a group access.Alternatively, memory element can be configured, so that each element can be single Solely access, such as NOR storage array.The configuration of NAND and NOR memory is exemplary, and storage unit can be with its other party Formula configuration.

Storage unit can be arranged in single memory device grade with oldered array, such as be arranged in multiple rows and/or column In.However, memory element can be arranged with irregular or nonopiate configuration, or not to be considered as the structural arrangement of array.

Three-dimensional memory array is arranged, so that storage unit occupies multiple planes or multiple memory device grades, to form three It ties up structure (that is, in the x, y and z directions, the direction z is substantially vertical, the direction x and y is basically parallel to the main surface of substrate).

As non-limiting example, three-dimensional storage organization can be arranged vertically as the stacking of multiple two-dimensional storage device grades. As another non-limiting example, three-dimensional memory array can be arranged to multiple vertical rows (for example, being substantially perpendicular to lining The column that the main surface (i.e. in y-direction) at bottom extends), wherein each column has multiple storage units.Vertical row can be matched with two dimension Arrangement is set, for example, in an x-y plane, to generate the three dimensional arrangement of storage unit, wherein storage unit is located at multiple vertical stacks On folded memory plane.The other configurations of three-dimensional memory element also may be constructed three-dimensional memory array.

As non-limiting example, in three dimensional NAND storage array, memory element can be coupled with formed across The vertical nand string of more multiple levels.It is contemplated that other three-dimensional configurations, some of NAND strings include in single storage level Memory element, and other string comprising across multiple storage levels memory elements.Three-dimensional memory array can also with NOR configure and ReRAM configures to design.

It will be appreciated by those of ordinary skill in the art that the techniques described herein are not limited to single particular memory structure, but The many correlations covered in the spirit and scope of technology as described herein and as one of ordinary skill in the understanding are deposited Storage structure.

Fig. 2 is the block diagram of exemplary memory system 100, shows the more details of an embodiment of controller 122. As it is used herein, flash controller be the data that are stored on flash memory of management and with host such as computer or electronic device The device of communication.Other than concrete function as described herein, flash controller can also have various functions.For example, flash memory Flash format can be ensured that memory operates normally, maps out bad flash cell by controller, and distribute slack storage Unit is to replace trouble unit in the future.The some parts of stand-by unit can be used for keeping firmware with operating flash memory controller and real Existing other function.In operation, when host needs to read data from flash memory or write data into flash memory, it will be with flash memory control Device communication processed.If host, which provides, wants the logical address of reading/writing data, flash controller can will be received from host Logical address is converted to the physical address (alternatively, host can provide physical address) in flash memory.Flash controller can also be held (distribution write-in should be repeated originally to avoid loss to be write for the various memory management functions of row, such as, but not limited to wear leveling The particular memory block entered) and garbage collection (after block has been expired, effective data page is only moved to new block, therefore can wipe And reuse whole blocks).

Interface between controller 122 and non-volatile memories tube core 108 can be any suitable flash interface, such as Switch mode 200,400 or 800.In one embodiment, storage system 100 can be the system based on card, such as safe Digital (SD) or microampere digital (micro- SD) card.In an alternate embodiment, storage system 100 can be Embedded Memory System A part.For example, flash memory can be embedded in host.In other examples, storage system 100 can be solid state drive (SSD) form.

In some embodiments, Nonvolatile memory system 100 includes controller 122 and non-volatile memories tube core Individual channel between 108, theme described herein are not limited to single memory channel.For example, in some storage systems In framework, controller ability is depended on, 2,4,8 or more channels may be present between controller and storage tube core.Herein It, can also be between controller and storage tube core even if individual channel is shown in the attached drawings in any embodiment of description In the presence of more than individual channel.

As shown in Fig. 2, controller 122 includes the front-end module 208 connecting with host, non-volatile deposits with one or more The rear module 210 that tube core 108 connects is stored up, and executes the various other modules for the function of will be described in now.

The component of controller 122 shown in Figure 2 can take the encapsulation for being designed to be used together with other component The form of functional hardware unit (for example, circuit), can be by for example usually executing (micro-) processor of the specific function of correlation function Or the program code (for example, software or firmware) that processing circuit or the separate hardware connecting with bigger system or software component execute A part.For example, each module may include specific integrated circuit (ASIC), field programmable gate array (FPGA), circuit, Digital Logical Circuits, analog circuit, discrete circuit, grid or any other type hardware combination or their combination.Separately Selection of land or in addition to this, each module may include the software being stored in processor readable devices (for example, memory), with right The processor of controller 122 is programmed, thereby executing functions described herein.Framework shown in Figure 2 is can (or can be with No) using an exemplary tool of the component (i.e. RAM, ROM, processor, interface) of controller 122 shown in Figure 1A or Fig. 1 C Body is implemented.

Referring again to the module of controller 122, buffer-manager/bus marco 214 manages random access memory (RAM) buffer in 216 and the internal bus arbitration of controller 122 is controlled.218 storage system of read-only memory (ROM) is drawn Lead code.Although be shown in Figure 2 for it is separated with controller 122, in other embodiments, RAM 216 and ROM One or both in 218 can be located in controller.In other embodiments, the part of RAM and ROM can both be located at control Device 122 is interior, can be located at outside the controller again.In addition, in some specific implementations, controller 122, RAM216 and ROM 218 can be located on individual semiconductor element.

Front-end module 208 includes providing the host interface 220 and object of the electrical interface with host or next stage storage control Manage layer interface (PHY) 222.The selection of 220 type of host interface may depend on the type of used memory.Host interface 220 example includes but is not limited to SATA, SATA Express, SAS, fiber channel, USB, PCIe and NVMe.Host interface 220 generally facilitate transmission data, control signal and timing signal.

Rear module 210 includes error correcting code (ECC) engine 224, and the error correcting code engine is to from the received data byte of host It is encoded, and the data byte read from nonvolatile memory is decoded and error correction.Order sequencer 226 generates life Sequence, such as programmed and erased command sequence are enabled, to be sent to non-volatile memories tube core 108.RAID (the redundancy of individual dice Array) module 228 manage RAID parity verification generation and fault data recovery.RAID parity verification may be used as to write-in The integrity protection of the additional level of the data of Nonvolatile memory system 100.In some cases, RAID module 228 can be with It is a part of ECC Engine 224.It may be noted that RAID parity verification can be used as additional one or more tube cores addition, such as altogether As being implied with title, but can also be added in existing tube core, for example, as additional plane, additional block or Additional WL in block.Command sequence is supplied to non-volatile memories tube core 108 by memory interface 230, and is deposited from non-volatile Store up 108 receiving status information of tube core.In one embodiment, memory interface 230 can be Double Data Rate (DDR) and connect Mouthful, such as switch mode 200,400 or 800 interfaces.The all operationss of the control rear module 210 of flash memory control layer 232.

The additional component of system 100 shown in Fig. 2 includes media management layer 238, executes non-volatile memories tube core The wear leveling of 108 storage unit.System 100 further includes other discrete parts 240, such as external electrical interface, external RAM, Resistor, capacitor or the other component that can be connect with controller 122.In an alternate embodiment, physical layer interface 222, One in RAID module 228, media management layer 238 and buffer-manager/bus control unit 214 or more persons are controllers Unnecessary optional component in 122.

Flash translation layer (FTL) (FTL) or media management layer (MML) 238, which can be integrated into, can handle flash memory mistake and and host A part of the flash memory management of connection.In particular, MML can be the module in flash memory management, and NAND pipe can be responsible for The inside of reason.In particular, MML 238 may include the algorithm in memory device firmware, which turns the write-in from host It is changed to the write-in to the flash memory 126 of tube core 108.MML 238 may be needed, because are as follows: 1) flash memory may have limited durability； 2) multiple ECC page faces can be only written in flash memory 126；And/or 3) otherwise may not be used unless flash memory 126 is wiped as block The flash memory is written.MML 238 understands these potential limitations of flash memory 126, these limitations may be invisible to host.Therefore, MML 238 attempt to be converted to the write-in from host in write-in flash memory 126.As described below, MML 238 can be used to identify and remember The unstable positioning of record.The record of shakiness positioning can be used for assessing the health status of block and/or wordline (storage unit in wordline).

Controller 122 can be connect with one or more storage tube core 108.In one embodiment, 122 He of controller Multiple storage tube cores (together including Nonvolatile memory system 100) realize solid state drive (SSD), which can be with Hard disk drive in simulation, replacement or substitution host, such as NAS device, laptop, tablet computer.In addition, SSD is not It needs to be used as hard disk drive.

Some embodiments of Nonvolatile memory system will include a storage tube core for being connected to a controller 122 108.However, other embodiments may include the multiple storage tube cores 108 communicated with one or more controllers 122.At one In example, as shown in Figure 3A, multiple storage tube cores can be grouped into storage stack encapsulation.Each memory package include with One or more storage tube cores that controller 122 communicates.Fig. 3 A is shown in controller and each memory package 0 to N Storage tube core between the N+1 memory package (encapsulation 0 to encapsulation N) that communicates and N+1 channel (channel 0 to channel N).? In one embodiment, memory package includes printed circuit board (or similar structures), with one mounted thereto or Multiple storage tube cores.In some embodiments, memory package may include molding material to wrap up the storage of memory package Tube core 108.In one embodiment, memory package can be single storage tube core 108.In some embodiments, it controls Device 122 processed is physically separated with any memory package.

Fig. 3 B is the block diagram for showing an embodiment of sensing block SB1 of Fig. 1 C.Sensing block, which is divided into, referred to as to be felt It surveys one or more cores of module (for example, SM0) or sensing amplifier and is referred to as management circuit (for example, MC0) altogether With part.In one embodiment, exist for each bit line individual sensing module and for one group of sensing module it is all Such as a shared management circuit of SM0, SM1, SM2 and SM3.Each of sensing module in group is via data/address bus 172 With associated management circuit communication.Accordingly, there exist the one or more management communicated with the sensing module of one group of storage unit Circuit.

Each sensing module SM0, SM1, SM2 and SM3 respectively include sensing circuit SC0, SC1, SC2 and SC3, the sensing Whether the conduction electric current in bit line BL0, BL1, BL2 and the BL3 of circuit by determining connection respectively is higher or lower than predetermined threshold Voltage (verifying voltage) executes sensing.Each sensing module SM0, SM1, SM2 and SM3 are respectively further comprised in the position of connection Bit line latch BLL0, BLL1, BLL2 and BLL3 of voltage conditions are set on line.For example, being latched in place during programming operation The bit line that predetermined state in line latch will lead to connection is pulled to lock state (for example, 1.5-3V), slow programming state (example Such as, 0.5-1V) or normal program state (for example, 0V).

Management circuit MC0 include 192, four groups of example data latch 194 (0) of processor, 194 (1), 194 (2) and 194 (3) and the I/O interface 198 being coupled between data latches group 194 and data/address bus 120.Bit line latch (BLL0 Combination to BLL3) and latch 194 is to sense an embodiment of data register 40.I/O interface 198 is I/O data One embodiment of register 42.

In this example, every group of latch is associated with one of bit line.For example, data latches 194 (0) and bit line BL0 Associated, data latches 194 (1) are associated with bit line BL1, and data latches 194 (2) are associated with bit line BL2, data lock Storage 194 (3) is associated with bit line BL3.In this embodiment, every group of data latches include by LDL 151, MDL 152 With the data latches of UDL153 mark.In the memory for storing three data in each storage unit, the storage of LDL 151 is used In the position of the nextpage (LP) of write-in data, MDL 152 stores the position for the intermediate page (MP) of data to be written, and UDL 153 Store the position for the upper page (UP) of data to be written.It may be noted that there may be one group of such latches associated with each bit line Device.Latch 194 can be also used for storing the data read from non-volatile memory cells.

Also every group of additional or less data latches can be used.For example, in the specific implementation of two every storage units In, do not need the MDL data latches of the intermediate page (MP) for data.The specific implementation of four every storage units can be used LDL, LMDL (in-nextpage), UMDL (upper-intermediate page) and UDL latch.Technology provided herein is intended to cover such modification. In another option, when the Vth of storage unit is in the specified nargin of the verifying voltage of its targeted data states, using another One latch comes whether recognition memory cell is in slow programming mode.

Processor 192 executes calculating during reading and programming.In order to read, processor, which determines, is stored in depositing of being sensed Data mode in storage unit simultaneously stores data in this group of data latches.For programming and refreshing programming completely, handle Device reads latch to determine the data mode for wanting write storage unit.

During reading, under the control of state machine 112, which controls the storage to addressing for the operation of system Unit provides different control grid voltages.When it has stepped through each of the various memory states supported corresponding to memory When the predefined control grid voltage of kind, sensing module can trip at one of these voltages place, and will pass through data/address bus 172 Corresponding output is provided from sensing module to processor 192.At this point, trip event of the processor 192 by consideration sensing module Memory state is determined with the information about the control grid voltage applied via input line 193 from state machine.Then, It calculates the binary coding of memory state, and by the storage of resulting data bit into data latches 194.For example, with position The memory state of the associated storage unit of line BL0 can store in latch 194 (0) etc..In the another of management circuit MC0 In one embodiment, bit line latch had been used as latch both with the output of latching sense module, also served as position as described above Line latch.

Some specific implementations may include multiple processors.In one embodiment, each processor will include output line (not shown) so that each of output line by wired OR together.In some embodiments, output line is connecting It is inverted before to wired OR line.The configuration makes it possible to quickly determine when complete programming process is during program verification process At because the state machine for receiving wired OR can decide when that all programmed positions have reached required level.For example, when each When position reaches its required level, the logical zero of this will be sent to wired OR line (or data 1 are inverted).It is exported when all When data 0 (or data 1 are inverted), state machine knows programming process to be terminated.Because of each processor and four sensing modules Communication, so state machine needs to read wired OR line four times, or is added to processor 192 for logic to accumulate associated position Line as a result, so that state machine only needs to read a wired OR line.Similarly, by correctly selecting logic level, entirely Office's state machine can detecte first its state of timing changing and correspondingly change algorithm.

During programming or verification operation, data to be programmed (write-in data) are stored in the number from data/address bus 120 According in latch 194 and in LP, MP and UP data latches.For example, will be in selected memory cell associated with bit line BL0 The data of middle programming can store in latch 194 (0), program in the associated selected memory cell of Yao Yu bit line BL1 Data can store it is medium in latch 194 (1).Under the control of state machine, programming operation includes being applied to be addressed A series of program voltage pulses of the control grid of storage unit.It is to read back (validation test) with determination after each program voltage Whether storage unit is programmed to be arrived required memory state.In some cases, processor monitoring is relative to required storage The memory state that reads back of device state.When two state consistencies, bit line latch is arranged so that bit line is pulled to finger in processor Determine the state (for example, 2-3V) of program-inhibit.Even if program voltage appears in it and controls on grid, this also forbids being couple to bit line Storage unit further program.In other embodiments, processor initially loads bit line latch, and sensing circuit exists Prohibition value is set to during verification process.

Every group of data latches 194 can be implemented as the stacking of the data latches of each sensing module.Some specific In implementation, data latches are implemented as shift register, so that the parallel data being stored therein is converted into data/address bus 120 serial data, vice versa.All data latches of read/write block corresponding to storage unit can connect Together to form block shift register, so as to pass through serial transmission input or output block.In particular, reading/writing Enter module group to be adjusted so that each of its data latches group by data in order into and out data/address bus, just As they are a part of the shift register of entire read/write block.

Fig. 4 A shows the exemplary structure of memory cell array 126.In one embodiment, memory cell array quilt It is divided into M memory cell block.The block is erasing unit.That is, each piece includes the storage for the minimum number wiped together Unit.Each piece is typically split into many pages.It may be noted that these pages herein are properly termed as " ECC page face ".ECC page Face is programming unit.One or more ECC data pages are generally stored inside in a line storage unit.ECC page face can store one A or multiple sectors.Sector includes user data and overhead data.Overhead data generally includes the user data according to sector The parity check bit of the error correcting code (ECC) of calculating.When data are programmed into array, it is odd that a part of controller calculates ECC Even parity check, and also it is checked when reading data from array.Alternatively, ECC and/or other overhead datas are stored in In the different ECC page face of the user data being associated with or even different blocks.

Fig. 4 A also shows the more details of an embodiment of the block i of storage array 126.Block i includes X+1 bit line With X+1 NAND string.There may be thousands of NAND strings in block.Block i further include 64 data wordline (WL0 to WL63), 2 it is illusory Wordline (WL_d0 and WL_d1), drain side selection line (SGD) and source side selection line (SGS).One terminal of each NAND string It is connected to corresponding bit line via drain electrode selection gate (being connected to selection line SGD), and another terminal is via drain selection Grid (being connected to selection line SGS) is connected to source electrode line.Because having 64 data wordline and 2 dummy word lines, each NAND string includes 64 data storage cells and 2 illusory storage units.In other embodiments, NAND string can have more In or less than 64 data storage cells and more or fewer illusory storage units.Data storage cell can store user Or system data.Illusory storage unit is generally not used for storage user or system data.Some embodiments do not include illusory deposit Storage unit.

In some embodiments, a word line program is once executed.That is, primary only to being connected to a wordline Storage unit be programmed.In addition, in order to improve efficiency, when being programmed to wordline, all in wordline can be deposited Storage unit is programmed.In general, multiple ECC page faces are programmed into storage unit associated with a wordline.ECC page face Quantity can depend on each storage unit programs how many position.For example, if each storage unit programs a position, each word Line can program the ECC page face of four, eight, 16 or some other quantity.

Storage unit can be programmed to store two charge levels (or some other physical parameters, such as resistance), So that storing individual data position in each cell.This is commonly known as binary system or single stage unit (SLC) memory.SLC is deposited Reservoir can store two states.Alternatively, it is (or some to store more than two detectable charge levels to operate storage unit Other physical parameters, such as resistance), to be more than one data in each middle storage.Latter configuration is known as multi-level unit (MLC) memory.For example, MLC memory can store four kinds of states and can retain two data bit.For another example, MLC is stored Device can store eight states and can retain three data bit.Two kinds of storage unit can be used in memory, example If binary system SLC Flash can be used for cached data, MLC memory can be used for storing for a long time.In some embodiments In, storage system has the block pond for SLC programming and the block pond for MLC programming.These are referred to as SLC block and MLC block. In one embodiment, host data is initially stored in SLC block by storage control 122, then executes folding operation, Middle data are transferred to MLC block from one or more SLC blocks.

In order to realize better concurrency, storage tube core (or other logic units) can be divided into multiple planes.It is flat Face can be defined as reporting the mode of operation of their own and can execute life independently of other planes in storage tube core Enable the unit executed.For example, each plane can have the data register of their own, data buffer etc., to realize independence Command operation.Fig. 4 B shows tool, and there are two plane (planes 0,402a；Plane Isosorbide-5-Nitrae 02b) one of storage tube core 108 show Example.In this example, plane 0 has block 0,1,4,5,8,9,12,13 ... n, n+1.Plane 1 have block 2,3,6,7,10,11, 14,15……n+2,n+3.How this only stores an example of 108 addressed block of tube core for biplane.

It may be noted that sensing data register 40a can store the memory cell group from one of block in 0 402a of plane The data of sensing.Equally, sensing data register 40b can store the memory cell group from one of block in 1 402b of plane The data of sensing.Therefore, the storage unit in a block in plane 0 can be with the storage unit in a block in plane 1 It senses simultaneously.

In addition, the data in sensing data register 40a can be used for storing one of the block that be programmed into 0 402a of plane In memory cell group in data.Equally, the data in sensing data register 40b, which can be used for storing, will be programmed into plane 1 The data in memory cell group in one of block in 402b.Therefore, the storage unit in a block in plane 0 can with it is flat The storage unit in a block in face 1 programs simultaneously.Additionally, there are associated with each plane 402a, 402b individual One group of I/O data register 42a, 42b.

In one embodiment, in one of block that one or more ECC page faces are programmed into plane 0 by storage tube core In memory cell group, while in the memory cell group in one of block that also one or more ECC page faces are programmed into plane 1. In some embodiments, a wordline in plane is once only programmed.Therefore, in one embodiment, storage tube core will Multiple ECC page faces are programmed into the storage unit in a wordline in plane 0, while being also programmed into multiple ECC page faces flat In the storage unit in a wordline in face 1.Herein, term " maximum programming unit " refers to can be programmed into storage simultaneously The maximum amount of data in storage unit on tube core 108.The maximum unit of programming depends on the digit of each storage unit programming. For example, storing tube core can while be programmed into 8 ECC page faces in plane 0 if each storage unit programs single position In block, and other 8 ECC page faces are programmed into the block in plane 1.Therefore, the maximum programming unit in the SLC example is 16 ECC page faces.It may be noted that in one embodiment, the maximum quantity of the storage unit that can be programmed simultaneously independent of The digit of each unit.

As described above, segment is defined herein as the smallest addressable storage unit in memory device.In a reality It applies in scheme, segment includes the memory cell group in memory cell group and block plane 1 in the block in plane 0.For example, at one In embodiment, a segment is programmed, an ECC page face is programmed in the storage unit in the block in plane 0, and in block Another ECC page face is programmed in memory cell group in plane 1.It is further noted that in some embodiments, maximum programming unit It is multiple segments.

Fig. 5 illustrate how to carry out the data of the unjustified writing commands in data buffer 34 it is pre-filled and/or after Filling is to form complete segment.Four segments are shown in data buffer 34.It may be noted that data buffer 34 refers to physics A part of memory (for example, RAM 122b) is used to temporarily deposit when transmitting data between host 140 and memory 126 Store up data.The corresponding unjustified writing commands of each segment.In this example, the sector data of each unjustified writing commands Less than clip size.

For segment 1, there are both pre-filled with data and rear filling data.Sector data is the data from host, should Data will be written by unjustified writing commands.In one embodiment, by read associated with segment storage unit come Obtain pre-filled with data and rear filling data.For example, before writing, segment may be mapped to some on storage tube core Physical location.

For segment 2, there is also both pre-filled with data and rear filling data.For segment 3, data are filled after existing, But since sector data is located at the beginning of segment, pre-filled with data is not needed.For segment 4, there are pre-filled with data, But since sector data is located at the end of segment, data are filled after not needing.Moreover, there are two fans in segment 4 Area data sector.It note that unjustified data are not filled with segment as defined herein.Therefore, for unjustified sector number According to, be constantly present pre-filled with data and/or after fill data.

Fig. 6 is the flow chart for handling the process 600 of unjustified writing commands.Unjustified writing commands can be random not right Neat writing commands.In one embodiment, random unjustified writing commands are be not filled up completely at least one segment not right Neat writing commands.Process 600 is realized in storage system 100, in such as, but not limited to Figure 1A, Figure 1B, Fig. 1 C, Fig. 2 or Fig. 3 A Storage system.In the process 600 of discussion, by the various elements in reference Figure 1A, Fig. 4 B and Fig. 5.It is near in host 140 Few two unjustified writing commands are sent to after storage system 100, start-up course 600.In one embodiment, order is deposited Storage is in command queue 32.It may be noted that for ease of description, describing these steps in process 600 with particular order.It can be with It is executed in different order these steps.In addition, certain steps can execute repeatedly.

Step 602 includes the unjustified writing commands in recognition command queue 32.In one embodiment, storage control Device 122 identifies unjustified writing commands as follows.Any writing commands with the starting LBA for not being the multiple of sector number in segment It is identified as unjustified writing commands.In addition, any size of data is all unjustified write not equal to the writing commands of clip size Enter order.It may be noted that unless otherwise the process is without arriving step 604 there are at least two unjustified writing commands.At one In embodiment, step 602 includes identification random writing order.

Step 604 includes that the unjustified data of unjustified writing commands are received in data buffer 34.Implement at one In scheme, the starting of storage control 122 is transmitted from mainframe memory 20 to the data of data buffer 34.With reference to Fig. 5, sector number According to the appropriate location for receiving and being placed in data buffer 34 from host 140.This includes that sector data is put into segment, It is put at the offset in segment.It may be noted that for convenience, describing step 604 with regard to this point in process 600.In step It can receive part or all of sector data after 606.

Step 606 includes merging sensing and transmission, wherein sensing is for one 's in unjustified writing commands Store tube core on storage unit filling data, transmission be for previous sensor data from storage tube core on storage unit Another the data buffer being transferred in unjustified writing commands." the filling data " of given segment include that " pre-fill is made up the number According to " and/or " filling data afterwards ".For example, the filling data of the storage unit sensing segment 2 on storage tube core, pass simultaneously The filling data of the segment 1 of defeated previous sensor.In one embodiment, sensing data register 40 is initially used for storage from depositing The filling data for the segment 1 that storage unit on storage tube core 108 senses.Then the filling data of segment 1 are transferred to I/O number According to register 42.Then, sensing data register 40 is used to store the segment 2 sensed from the storage unit on storage tube core 108 Filling data, while the filling data of segment 1 are transferred to data buffer 24 from I/O register 42.This sensed in parallel It can be applied to other segments pair with transmission.It unjustified is write due to each segment in this example there are one in addition, note that Enter order, therefore this can be referred to as the sensed in parallel and transmission to the filling data of unjustified writing commands pair.In addition, needing to infuse Meaning, before or after adding padding data to data buffer 34, the sector data of unjustified writing commands can be passed It is defeated to arrive data buffer 34.

After step 606 and 608, align data is created for unjustified writing commands.With reference to Fig. 5, each Section is respectively completed." complete segment " means that institute is in need pre-filled and/or rear filling data are together with host sector data quilt It is added to segment.Therefore, it can be said that each of four segments in data buffer 34 are all the complete slices of align data Section.

Step 608 is that the align data of each of unjustified writing commands is transferred to storage from data buffer 34 Tube core 108.In other words, step 608 includes delaying the partial data segment of each of unjustified writing commands from data It rushes device 34 and is transferred to storage tube core 108.It may be noted that controller 122 can execute data before being transferred to storage tube core 108 Some other processing.For example, controller 122 can be by the data that are added to parity check bit in data buffer 34 come shape At one or more ECC page faces.In one embodiment, storage control 122 collects enough data for maximum programming Unit, so that the quantity for the complete segment transmitted in step 608 is equal to maximum programming unit.

Step 610 is including will be transmitted in the memory cell group that the align data of storage tube core is programmed into storage tube core. In other words, the memory cell group that step 610 is programmed on memory including will be transmitted to the partial data segment of storage tube core In.It may be noted that storage unit can be in two or more planes.In one embodiment, storage tube core is simultaneously by institute There is align data to be programmed into the memory cell group on storage tube core.It may be noted that the memory cell group can be located at storage tube core One or more planes on.Therefore, in a programming operation on a storage tube core and on another storage tube core Another programming operation may be performed simultaneously.Therefore, step 610 may include each plane single programming operation in will not All align datas of alignment writing commands are programmed into the memory cell group on storage tube core.Storage unit can be programmed to often Unit one, every unit two, every unit three etc..Therefore, multiple unjustified writing commands can be programmed simultaneously.This section It has saved the time and has reduced write-in amplification.Which also saves electric power.

Fig. 7 is the flow chart of an embodiment of the process 700 for the align data to form unjustified writing commands.Process 700 can be used for being formed the complete segment of a unjustified writing commands in data buffer 34.For example, process 700 can be used In added to data buffer 34 the pre-filled of sector data and segment and/or after fill data.Process 700 is in storage system It is realized in 100, the storage system in such as, but not limited to Figure 1A, Figure 1B, Fig. 1 C, Fig. 2 or Fig. 3 A.It, will in the process 700 of discussion With reference to the various elements in Figure 1A, Fig. 4 B and Fig. 5.It may be noted that for ease of description, process 700 describes unjustified to one The data processing of writing commands.However, as will be described below, when for one of unjustified writing commands implementation procedure 700 When the stage, another stage of the process can be executed for another unjustified writing commands.

Step 702 includes that storage control 122 identifies unjustified writing commands.This is the mistake for a unjustified order One embodiment of the step 602 of journey 600.

Step 704 and 706 can execute parallel.However, not requiring parallel execution of steps 704 and 706.Step 704 includes Logical address in unjustified writing commands is converted to the physical address in storage system 100 by storage control 122.It needs to infuse Meaning, in one embodiment, one in physical address mark storage tube core 108.In one embodiment, physical address It is smallest addressable unit.As described above, term " segment " in this article refers to the storage list of the smallest addressable in memory device Member.In the step 704 of an embodiment, storage control 122 uses logic to physical translation table.It may be noted that some In embodiment, only the L2P cache 36 of logic to physical translation table 66 is maintained in RAM 122b.Therefore, if necessary Entry is not in L2P cache 36, then the L2P table 66 in the accessible storage organization 126 of storage control 122.

Step 706 includes that unjustified sector data is transferred to data buffer 34 from host 140.Step 706 is to be used for One embodiment of the step 604 of the process 600 of one unjustified order.

Step 708 includes that storage control 122 is ordered to the storage transmission of tube core 108 to read and be used for unjustified writing commands Filling data.The order can identify the memory cell group bigger according to memory cell group actually required than filler.For example, The order can indicate that storage tube core reads the storage unit in entire wordline in some block, even if filling data are merely stored in In the subset of storage unit.This is because in some embodiments, the usually sensing storage in read operation of storage tube core 108 One wordline of unit.It is further noted that the order can request storage tube core to sense storage unit in more than one plane.Example Such as, with reference to Fig. 4 B, which can indicate that storage tube core is read on the block 10 in wordline and plane 1 in the block 8 in plane 0 Wordline.It is further noted that in some cases, more than one storage tube core can be sensed to obtain filling data.Therefore, some In the case of, storage control 122 can send reading order to more than one storage tube core.It may be noted that the wordline to be read Referred to as selected word line, the block with selected word line are referred to as selected block.In one embodiment, reading order is ONFI life It enables.

It may be noted that storage control 122 can start for another unjustified writing commands after step 708 Process 700.Therefore, in one embodiment, after step 708, controller 122, which executes, is used for another unjustified write-in The step 702 of order.Alternatively, another unjustified writing commands may have been identified, in such a case, it is possible to execute Step 704 and/or 706 for next unjustified writing commands.The further details of such processing are discussed below.

Step 710 includes storing the sensing of tube core 108 filling data and storing filling data to sensing data register 40 In.In one embodiment, step 710 includes sensing data in the storage unit at least one wordline.With reference to above About the example of Fig. 4 B, the storage unit in a wordline of 108 sensing block 8 of tube core is stored, and stores data in sensing number According in register 40a.In addition, the storage unit in a wordline of storage 108 sensing block 10 of tube core, and store data in sense In measured data register 40b.It may be noted that step 710 may include only feeling in a plane, two planes, four planes etc. Survey the storage tube core 108 of storage unit.It is further noted that in some cases, step 710 can be related to sensing storage unit to obtain Multiple storage tube cores of data must be filled.

Step 710 may include the sensing stage, wherein one or more read reference voltage and are applied in selected block Selected word line.Data can be stored in a storage unit with every unit one, every unit two, every unit three etc..In a reality It applies in scheme, the quantity for reading reference voltage depends on the digit of every unit.Such as begging in the exemplary sensing amplifier of Fig. 3 B Pointed by, data can be initially stored in bit line latch (for example, BLL0 is then store in latch into BLL3) In one or more of 194.Typically for SLC data, using the only one in LDL 151, MDL 152 and UDL 153, Two are used when each two positions of unit senses, and three are used when each three positions of unit senses.

Step 712 includes the storage tube that will be sensed data and be transferred to I/O data register 42 from sensing data register 40 Core 108.With reference to Fig. 4 B, senses the data in data register 40a and be transferred to I/O data register 42a, sense data register Data in device 40b are transferred to I/O data register 42b.With reference to Fig. 3 B, data are transferred to I/O interface from latch 194 198。

Step 714 includes that data are transferred to data buffer 34 from I/O register 42.With reference to Figure 1A, data are from I/O number Data buffer 34 is transferred to according to register 42.With reference to Fig. 5, complete segment is formed in data buffer 34 now.Also It is to say, any filling data that segment needs are transferred data buffer 34.In addition, data buffer 34 is received To the sector data of segment.

Fig. 8 is the figure of the timing in the embodiment shown for the programming data of multiple unjustified writing commands. Timing diagram has the axis labeled as " time ", and shows the sequence of operations executed by storage system 100.Timing diagram point For several stages: 1) firmware postpones；2) sector data is transmitted；3) L2P resolves；4) data sensing is filled；5) transmission filling data； 6) segment is transmitted；With 7) programming.In this example, eight unjustified writing commands have been handled.In this example, all eight not The align data of alignment writing commands is typically programmed simultaneously.In other words, in this example, every in eight unjustified writing commands One complete segment is typically programmed simultaneously.

Initially, there are the delays of some firmwares, as shown in firmware operation 802.The firmware operation 802 includes recognition command queue The storage control 122 of unjustified writing commands in 32.One embodiment of the firmware operation 802 expression step 602.It should Firmware delay 802 indicates an embodiment of step 702.

Next, first transmission sector data stage and L2P the resolution stage being directed in unjustified writing commands open Begin.This is indicated by transmission sector data 804 (1) and 806 (1) of L2P resolution.It may be noted that transmission sector data 804 (1) corresponds to The step 706 of process 700, and 806 (1) of L2P resolution correspond to the step 704 of process 700.

Next, the filling data sensing stage for first unjustified writing commands starts.This is by filling data sense Surveying 808 (1) indicates.Fill step 708,710 and 712 that data sensing corresponds to process 700.

It may be noted that the transmission sector data stage of the second unjustified writing commands and L2P resolution stage can be first not Start during the filling data sensing stage for being aligned writing commands.For example, storage control 122 process 700 step 708 It is middle send storage tube core for reading order after, storage control 122 can execute step for the second unjustified writing commands Rapid 704 and 706.It is indicated in this timing diagram 800 in fig. 8 by 806 (2) of resolving transmission sector data 804 (2) and L2P.

After the filling data sensing stage for the first unjustified writing commands terminates, it can start for second not It is aligned the filling data sensing stage of writing commands.This is indicated by the filling data sensing 808 (2) in timing diagram 800.In addition, It can be with the filler for the second unjustified writing commands for the transmission filling data phase of the first unjustified writing commands Merge according to the sensing stage.This is in timing diagram by filling out with the simultaneous transmission of at least part of filling data sensing 808 (2) Making up the number indicates according to 810 (1).In this example, transmission filling data phase is shorter than the filling data sensing stage.

Therefore, it may be noted that timing diagram 800 shows merging for sensing and transmission, wherein sensing is for from unjustified The filling data of the storage unit on one storage tube core in writing commands (for example, unjustified writing commands), transmission are Another the data in unjustified writing commands are transferred to from the storage unit on storage tube core for the data of previous sensor Buffer.It can be to other unjustified writing commands to the execution merging.For example, merge filling data sensing stage 808 (3) with Transmission filling data phase 810 (2) etc..

Timing diagram 800 also shows transmission sector data stage, L2P resolution stage, filling data sensing stage and transmission How filling data phase continues on for other unjustified writing commands pair in a similar way.Finally, data buffer 34 will Complete segment comprising all eight unjustified orders.In other words, data buffer 34 will include all eight unjustified lives The align data of order.In other words, by operating 810 (1) to 810 (8) for any desired of all eight unjustified orders Filling data (pre-filled and/or rear filling) is transferred to data buffer.In addition, will own by operating 804 (1) to 804 (8) The sector data of eight unjustified orders is transferred to data buffer.It may be noted that in this example, being transferred to data will be filled When data buffer 34, the transmission of sector data to data buffer 34 does not occur.

In one embodiment, storage control 122 handles sufficient amount of unjustified writing commands, so that piece The quantity of section corresponds to maximum programming unit.For example, programming single position if it is each storage unit, maximum unit of program can To be eight ECC page faces in the block in plane 0 and other eight ECC page faces in the block in plane 1.Therefore, the SLC Maximum programming unit in example is 16 ECC page faces.In order to further expand this example, segment may be two ECC page faces. Therefore, in this example, maximum unit of program is eight segments.There may be more or less than eight in maximum programming unit Segment.

After all data that data buffer 34 has had been filled with all eight unjustified writing commands, segment is transmitted Stage starts.This is indicated by the way that eight segments 812 (1) to 812 (8) are transferred to storage tube core.Eight segments 812 (1) are extremely The transmission of 812 (8) corresponds to an embodiment of the step 608 of process 600.With reference to Figure 1A, eight segments 812 (1) to 812 (8) I/O data register 42 is transferred to from data buffer 34.

Next, being programmed during the program phase 814 to eight segments 812 (1) to 812 (8).This corresponds to process One embodiment of 600 step 610.Data can be programmed to every storage unit one, every storage unit two, often deposit Storage unit three etc..Segment can be programmed into the storage unit in one or more planes.For example, being posted with reference to Fig. 4 B, I/O Data in storage 42a are transferred to sensing data register 40a, and the data in I/O register 42b are transferred to sensing Data register 40b.It may be noted that in this context, sensing data register 40b may include LDL shown in Fig. 3 B 151, one or more of 153 latch 194 of MDL 152 and UDL.For example, can will sense in data register 40a Data are programmed into the storage unit on the selected word line in the block 8 of plane 0.For example, can will sense in data register 40b Data be programmed into the storage unit on the selected word line in the block 10 of plane 1.It may be noted that programming can be maximum programming list Position.As described above, term " maximum programming unit " refers to the maximum in the storage unit that can be programmed into simultaneously on storage tube core Data volume (this depends on the digit of each storage unit programming).

How the sequence shown in timing diagram 800 is saved a large amount of time by following example.Be made that it is assumed hereinafter that.Individually The time of the transmission sector data 804 of order is 50 microseconds (this is also the L2P resolution 806 under worst condition), fills data sense Surveying the time is 80 microseconds, and it is 30 microseconds that each filling data, which are transferred to the time of data buffer, by each segment from data The time of Buffer transfer to storage tube core is 30 microseconds, and programming time is 300 microseconds.

Total time in Fig. 8 is sector data 804 (1) transmission, eight sensing operations 808 (1) to 808 (8), one It fills data and transmits 810 (8), eight fragments for transport 812 (1) to 812 (8) and a programming operation 814.The total time is 30+ 8* (80+30)+30+300=1240 microsecond (does not calculate original firmware delay 802).

It may be noted that the timing 800 in Fig. 8 conceals another unjustified writing commands filling data 810 (1) to 810 (7) Transmission in the sensing operation of filling data, this saves the times.It may be noted that merging in this way, " n " is a unjustified to be write Enter " n-1 " in order to unjustified writing commands.In addition, it may be noted that timing 800 in Fig. 8 is a to all " n " unjustified writes The segment for entering order is carried out while being programmed.It may be noted that segment is the maximum unit of program in an embodiment.Therefore, it saves Plenty of time.

In contrast, the more original technology that each unjustified writing commands are executed with read-write modification is needed to spend more Time.Such technology can be used eight sector datas transmit 804, eight sensing operations, 808, eight filling data transmit 810, Eight fragments for transport 812 and eight programming operations 814.The total time is that 8* (50+80+30+30+300)=3920 microsecond (is disregarded Calculate original firmware delay 802).

In one embodiment, unjustified write-in is executed during the folding from SLC storage unit to MLC memory cell The processing of order.Fig. 9 is the mistake that unjustified writing commands are handled during the folding from SLC storage unit to MLC memory cell The flow chart of one embodiment of journey 900.Process 900 can execute in storage system 100, such as Figure 1A, Figure 1B, figure Storage system in 1C, Fig. 2 or Fig. 3 A.During process 900, the sensing amplification of sensing amplifier such as Fig. 3 B can be used Device.In process 900, MLC cell is programmed to every unit three；However, it is possible to modify process 900 to program MLC cell For every unit two, every unit four etc..

Step 902 includes starting folding sequence.The step can be started by storage control 122.

Step 904 includes the storage control 122 that the unjustified writing commands of folding sequence are selected from command queue 32.Such as Fruit MLC wordline will store three bits per memory cell, then storage control 122 can choose sufficient amount of three SLC wordline Writing commands.It may be noted that this refers to three SLC in plane 0 in the embodiment that plane 0 and plane 1 have parallel processing Three SLC wordline in wordline and plane 1.Equally, there may be MLC wordline in plane 0, and there may be another in plane 1 A MLC wordline.It may be noted that step 904 may include unjustified writing commands are divided into it is every in multiple SLC memory cell groups One one group of unjustified writing commands.SLC memory cell group can be the storage in each of one or more planes The wordline of unit.Step 904 is an embodiment of the step 602 of process 600.For ease of description, storage control selects Select 24 unjustified writing commands.This is consistent with the example of Fig. 8, wherein there are eight segments in maximum writing unit.

Step 906 is step 604,606,608 and 610 for the first SLC group implementation procedure 600.First SLC group can be with Including storing the storage unit in the wordline in each of one or more planes on tube core.It is primary to execute step 906 Sequence of operations as shown in Figure 8 may be implemented.Therefore, in this example, step is executed to eight in unjustified writing commands Rapid 906.In one embodiment, programming phases 814 are typically programmed simultaneously all data of eight unjustified writing commands. It may be noted that this may include being programmed in one or more planes to storage unit.For example, the wordline in the block 8 of plane 0 12 are programmed to every storage unit one, and the wordline 12 in the block 10 of plane 1 is programmed to every storage unit one.

Step 908 is step 604,606,608 and 610 for the 2nd SLC group implementation procedure 600.2nd SLC group can be with Including storing the storage unit in the wordline in each of one or more planes on tube core.It is primary to execute step 908 Sequence of operations as shown in Figure 8 may be implemented.Therefore, in this example, step is executed to eight in unjustified writing commands Rapid 908.In one embodiment, programming phases 814 are typically programmed simultaneously all data of eight unjustified writing commands. It may be noted that this may include being programmed in one or more planes to storage unit.For example, the wordline in the block 8 of plane 0 13 are programmed to every storage unit one, and the wordline 13 in the block 10 of plane 1 is programmed to every storage unit one.

Step 910 is step 604,606,608 and 610 for the 3rd SLC group implementation procedure 600.3rd SLC group can be with Including storing the storage unit in the wordline in each of one or more planes on tube core.It is primary to execute step 910 Sequence of operations as shown in Figure 8 may be implemented.Therefore, in this example, step is executed to eight in unjustified writing commands Rapid 910.In one embodiment, programming phases 814 are typically programmed simultaneously all data of eight unjustified writing commands. It may be noted that this may include being programmed in one or more planes to storage unit.For example, the wordline in the block 8 of plane 0 14 are programmed to every storage unit one, and the wordline 4 in the block 10 of plane 1 is programmed to every storage unit one.

Step 912 includes that the data just programmed are executed with the on piece data transmission of three SLC groups to a MLC group.MLC group It may include the storage unit in the wordline in each of one or more planes on storage tube core.In this example, The data of wordline 12,13 and 14 in block 8 from plane 0 can be programmed to every storage unit in the block 1012 of plane 0 Three, and the data for the wordline 12,13 and 14 being simultaneously from the block 10 of plane 1 can be programmed to the block 1014 in plane 1 In each storage unit three.The transmission of on piece data may include such as feeling the data sensing from SLC wordline to register In measured data register 40, it is then programmed into MLC wordline without transmitting data from storage tube core 108.

First embodiment disclosed herein is a kind of equipment, comprising: the storage tube core with storage unit；Data buffering Device；With one or more control circuits.One or more control circuits are configured as: by unjustified data receiver to data buffering In device.Unjustified data are used for multiple unjustified writing commands.One or more control circuits are configured as being sensed simultaneously With transmission, wherein sensing is the filler of the storage unit on storage tube core for one in unjustified writing commands It is to be transferred in unjustified writing commands for the filling data of previous sensor from the storage unit stored on tube core according to, transmission Another data buffer.One or more control circuits are configured as the alignment of each of unjustified writing commands Data are transferred to storage tube core from data buffer.One or more control circuits are configured as align data being programmed into storage In memory cell group on tube core.

In this second embodiment, and promote first embodiment, one or more control circuits are further configured All align datas to be programmed into simultaneously in the memory cell group on storage tube core.

In the third embodiment, and promote first embodiment or the second embodiment, one or more control electricity Road is configured as being sensed and being transmitted simultaneously, wherein sensing is for one storage tube in unjustified writing commands The filling data of storage unit on core, transmission be for previous sensor filling data from storage tube core on storage unit biography Another data buffer in the defeated unjustified writing commands to " n-1 " unjustified writing commands a to " n ".

In the 4th embodiment, and first embodiment is promoted to appoint whichever, storage tube into third embodiment Core includes first group of data register and second group of data register.In order to be sensed and be transmitted simultaneously, wherein sensing is needle To the filling data of the storage unit on the storage tube core of one in unjustified writing commands, transmission is for previously sense The filling data of survey are transferred to another the data buffer in unjustified writing commands from the storage unit on storage tube core, One or more control circuits are further configured to: first group of storage unit on sensing storage tube core, so as to will be unjustified First filling data in writing commands are stored into first group of data register；By first unjustified writing commands It fills data and is transferred to second group of data register from first group of data register；And at the same time sensed and transmitted, wherein Sensing is for the second memory cell group on storage tube core so as to by second filling data in unjustified writing commands It stores into first group of data register, transmission is the filling data for first unjustified writing commands from second group of data Register transfer is to data buffer.

In the 5th embodiment, and promote any 4th embodiment, one or more control circuits are further It is configured to simultaneously program all align datas of each of unjustified writing commands from first group of data register Into memory cell group.

In a sixth embodiment, and first embodiment is promoted to appoint whichever into the 5th embodiment, storage is single Tuple is a complete maximum programming unit.

In the 7th embodiment, and promote first embodiment into the 6th embodiment appoint whichever, one or Multiple control circuits are further configured to identify sufficient amount of unjustified writing commands in command queue, so that right Neat data are a largest units of programming.

In the 8th embodiment, and first embodiment is promoted to appoint whichever into the 7th embodiment, storage is single Tuple is located in multiple planes in storage tube core.

In the 9th embodiment, and first embodiment is promoted to appoint whichever into the 8th embodiment, wherein one A or multiple control circuits are further configured to: enough to the selection of multi-level unit (MLC) folding operation for single stage unit (SLC) The unjustified writing commands of quantity；Unjustified writing commands are divided into the group of each of multiple SLC groups of storage unit；It is right In each of unjustified writing commands group: i) by unjustified data receiver to data buffer, ii) simultaneously carry out sensing with Transmission, wherein sensing is filling out for the storage unit on one storage tube core in the unjustified writing commands in group It makes up the number evidence, transmission is that be transferred in group from the storage unit stored on tube core for the filling data of previous sensor unjustified is write Enter the data buffer of another in order；Iii) by the align data of each of unjustified writing commands in group from Data buffer is transferred to storage tube core；And SLC storage unit iv) being programmed into the align data of the group on storage tube core In group；And the data from multiple SLC memory cell groups are transferred to the MLC memory cell group on storage tube core.

One embodiment includes the method for operating storage system.This method includes in the command queue of storage control Identify multiple unjustified writing commands；The unjustified data of multiple unjustified writing commands are transferred to the data of storage control Buffer；Merge sensing and transmission, wherein sensing is on one storage tube core in unjustified writing commands The filling data of storage unit, transmission be for previous sensor filling data from store tube core on storage unit be transferred to not Another the data buffer being aligned in writing commands.Unjustified data and transmission are transmitted for each unjustified writing commands The filling data of previous sensor form complete segment in data buffer.This method further includes will be in unjustified writing commands The partial data segment of each is transferred to storage tube core from data buffer；And it will be transmitted to the partial data of storage tube core Segment is programmed into the memory cell group on storage tube core.

One embodiment includes Nonvolatile memory system, which includes: storage tube core, with storage unit； Data buffer；Unjustified writing commands identification device, it is multiple not right in the command queue of storage control for identification Neat writing commands；First data transmission device is used to the unjustified data of multiple unjustified writing commands being transferred to storage The data buffer of controller；Merge device, be used to merge sensing and transmission, wherein sensing is for from unjustified write-in The filling data of storage unit on one in order storage tube core, transmission are the filling data for previous sensor from depositing Storage unit on storage tube core is transferred to another the data buffer in unjustified writing commands；Second data transmission dress It sets, is used to the partial data segment of each of unjustified writing commands being transferred to storage tube core from data buffer； And programmer, the partial data segment for being used to will be transmitted to storage tube core are programmed into the memory cell group stored on tube core In.

In one embodiment, first data transmission device include following items in one or more persons: processor 122c, controller 122, RAM 122b, front-end module 208, host interface 220, PHY222, specific integrated circuit (ASIC), show Field programmable gate array (FPGA), circuit, Digital Logical Circuits, analog circuit, discrete circuit, grid or any other type The combination or their combination of hardware.Alternatively or in addition to this, first data transmission device may include being stored in processor Software in readable devices (for example, memory), to be programmed to processor 122c, thereby executing identification storage control Multiple unjustified writing commands in 122 command queue 32.

In one embodiment, merge device include following items in one or more persons: processor 122c, controller 122, RAM 122b, sensing data register 40, I/O data register 42, sensing block SB, read/write circuits 128, state Machine 112, on-chip address decoder 114, power control 116, decoder 124/132, interface 122d, latch 164, processor 192, I/O interface 198, bit line latch BLL0 to BLL3, sensing circuit SC0 to SC3, specific integrated circuit (ASIC), scene Programmable gate array (FPGA), circuit, Digital Logical Circuits, analog circuit, discrete circuit, grid or any other type it is hard The combination or their combination of part.Alternatively or in addition to this, merging device may include being stored in processor readable devices (example Such as, memory) in software, to be programmed to processor 122, thereby executing sensing and transmitting at least part merged, Wherein sensing is the filling data of the storage unit on the storage tube core for one in unjustified writing commands, transmission It is to be transferred to another in unjustified writing commands from the storage unit stored on tube core for the filling data of previous sensor Data buffer.

In one embodiment, the second data transmission device include following items in one or more persons: processor 122c, controller 122, RAM 122b, I/O register 42, main interface 122d, memory interface 230, specific integrated circuit (ASIC), field programmable gate array (FPGA), circuit, Digital Logical Circuits, analog circuit, discrete circuit, grid or any The combination or their combination of other kinds of hardware.Alternatively or in addition to this, the second data transmission device may include depositing Software in processor readable devices (for example, memory) is stored up, to be programmed to processor 122c, thereby executing will be not right The partial data segment of each of neat writing commands is transferred to storage tube core 108 from data buffer 34.

In one embodiment, programmer include following items in one or more persons: processor 122c, controller 122, RAM 122b, sensing data register 40, sensing block SB, read/write circuits 128, state machine 112, on-chip address solution Code device 114, power control 116, decoder 124/132, latch 164, processor 192, I/O interface 198, bit line latch BLL0 to BLL3, sensing circuit SC0 to SC3, specific integrated circuit (ASIC), field programmable gate array (FPGA), circuit, number Word logic circuit, analog circuit, discrete circuit, grid or any other type hardware combination or their combination.Optionally Ground or in addition to this, programmer may include the software being stored in processor readable devices (for example, memory), to place Reason device is programmed, thereby executing at least part of programming, wherein programming is the partial data piece that will be transmitted to storage tube core Section is programmed into the memory cell group on storage tube core.

For purpose of this document, term " write-in " and " storage " are usually used interchangeably, term " write-in " and " storage " it is also such.

For purpose of this document, numerical terms first (that is, 1st) and second (that is, 2nd) can be used for substantially specifying storage When controller receives the sequence of order (for example, writing commands) from host, and substantially specifies data (for example, the 1st number According to the 2nd data) storage sequence in the nonvolatile memory.It should, however, be mentioned that term first (i.e. the 1st) is no It should be construed as to imply that before it without any other sequence.For example, may be before receiving the 1st writing commands Receive previous writing commands.However, it can imply that in later point rather than when receiving 1 writing commands Receive the 2nd writing commands, term as used herein.Similarly, it, which can imply that, is receiving being followed by for the 2nd writing commands Receive the 3rd writing commands.

For purpose of this document, in specification to " embodiment ", " embodiment ", " some embodiments " or The reference of " another embodiment " can be used for describing different embodiment or identical embodiment.

For purpose of this document, connection can be it is connected directly or indirectly (for example, via it is one or more other Component).In some cases, when an element, which is referred to as, is connected or coupled to another element, which can directly connect It is connected to another element or is connected indirectly to another element via intermediary element.When an element is said to be directly connected to separately When one element, there is no intermediary element between the element and another element.If two device direct or indirect connections, it " communication ", allow them to transmit electronic signal between them.

For purpose of this document, term "based" and " depending on " can be read as " being based at least partially on ".

Although the various embodiments of this technology are hereinbefore described, but it is to be understood that they be as example and It is unrestricted to present.It is evident that for those skilled in the relevant art, in the essence for not departing from this technology Under the premise of range, various modifications in form and details can be carried out to the disclosure.For example, although above-detailed Some variations, but other modifications or addition form are also possible.In particular, in addition to those described herein Except form, other features and/or variations can also be provided.For example, above-mentioned specific implementation can be directed to disclosed spy The various combinations of sign and the combination and sub-portfolio of sub-portfolio and/or other several features disclosed above.In addition, showing in the accompanying drawings Out and/or logic flow as described herein do not need shown in particular order or sequential order realize desired result.Other Embodiment can be in the range of following claims.

The embodiment of this technology is described by means of function building block above, the function building block shows regulation Function and its relationship execution.For ease of description, the boundary of these function building blocks is generally defined herein.As long as regulation Function and its relationship be duly executed, so that it may define the boundary of substitution.Therefore, the boundary of any such substitution is being authorized In the scope and spirit of the technology of sharp claim protection.It would be recognized by those skilled in the art that these function building blocks can be by Discrete assembly, specific integrated circuit, the processor etc. or any combination thereof for executing appropriate software are realized.

The range and range of this technology should not be limited by any of above exemplary implementation scheme, and should be according only to Following claims and its equivalent are defined.

Although theme is described with the language specific to structure feature and/or method behavior, it is to be understood that, institute The theme limited in attached claims is not necessarily limited to special characteristic or behavior described above.On the contrary, described above Special characteristic or behavior are disclosed as the exemplary forms for realizing claim.

It is had been presented for for the purpose of illustration and description to detailed description above.The explanation is not intended to be detailed Or be limited to precise forms disclosed in this invention.According to above teaching content, many modifications and variations are all It is possible.Selecting described embodiment is the principle and its practical application in order to most preferably illustrate proposed technology, with Just so that others skilled in the art in various embodiments and can be suitable for expected special-purpose The technology is most preferably utilized in various modifications form.The scope of the present invention is intended to be defined by the following claims.

Claims (10)

1. a kind of equipment, comprising:

It stores tube core (108), the storage tube core has storage unit (126)；

Data buffer (34)；With

One or more control circuits (110,112,114,116,122,124,132,128,150), one or more of controls Circuit processed is configured as:

By unjustified data receiver into the data buffer, the unjustified data are used for multiple unjustified writing commands；

It is sensed and is transmitted simultaneously, wherein the sensing is for described in one in the unjustified writing commands The filling data of the storage unit on tube core are stored, the transmission is the filling data for previous sensor from the storage tube core On storage unit be transferred to another the data buffer in the unjustified writing commands；

The align data for being used for each of described unjustified writing commands is transferred to described deposit from the data buffer Store up tube core；And

The align data is programmed into the memory cell group on the storage tube core.

2. equipment according to claim 1, wherein one or more of control circuits are further configured to:

All align datas are programmed into the memory cell group on the storage tube core simultaneously.

3. equipment according to claim 1 or 2, wherein one or more of control circuits are further configured to:

It is sensed and is transmitted simultaneously, wherein the sensing is for described in one in the unjustified writing commands The filling data of the storage unit on tube core are stored, the transmission is the filling data for previous sensor from the storage tube core On storage unit " n-1 " couple that is transferred to " n " a unjustified writing commands the unjustified writing commands in another The data buffer.

4. equipment according to claim 1 or 2, wherein the storage tube core includes first group of data register and second group Data register, wherein in order to be sensed and be transmitted simultaneously, wherein the sensing is for from the unjustified write-in life The filling data of the storage unit on one storage tube core in order, the transmission are the fillers for previous sensor Another the data buffering in the unjustified writing commands is transferred to according to from the storage unit on the storage tube core Device, one or more of control circuits are further configured to:

First group of storage unit on the storage tube core is sensed, so as to first for being used in the unjustified writing commands The filling data of writing commands are stored into first group of data register；

The filling data for being used for first unjustified writing commands are transferred to from first group of data register Second group of data register；And

Simultaneously sensed and transmitted, wherein it is described sensing be for it is described storage tube core on the second memory cell group so as to will The filling data of second unjustified writing commands are stored into first group of data register, and the transmission is to be directed to The filling data of first unjustified writing commands are transferred to the data from second group of data register and delay Rush device.

5. equipment according to claim 4, wherein one or more of control circuits are further configured to:

It will be used for all align datas of each of described unjustified writing commands simultaneously from first group of data Register is programmed into the memory cell group.

6. equipment according to claim 1,2 or 4, wherein one or more of control circuits are further configured to:

In the single programming operation of each plane, all align datas of the multiple unjustified writing commands will be used for It is programmed into the memory cell group on the storage tube core.

7. equipment according to claim 1,2 or 4, wherein one or more of control circuits are further configured to:

Sufficient amount of unjustified writing commands are identified in command queue, so that the align data is one of programming Largest unit.

8. equipment according to claim 7, wherein the memory cell group is located at multiple planes in the storage tube core On.

9. equipment according to claim 1,2 or 4, wherein one or more of control circuits are further configured to:

Sufficient amount of unjustified writing commands are selected for single stage unit (SLC) to multi-level unit (MLC) folding operation；

The unjustified writing commands are divided into each of the multiple SLC groups for organizing unit for storage；

For each of described unjustified writing commands group: i) by the unjustified data receiver to the data buffering Device, ii) it is sensed and is transmitted simultaneously, wherein the sensing is in the unjustified writing commands in described group One storage tube core on storage unit the filling data, the transmission is the filler for previous sensor Another the institute in the unjustified writing commands in described group is transferred to according to from the storage unit on the storage tube core State data buffer；Iii) by the align data of each of the unjustified writing commands being used in described group from described Data buffer is transferred to the storage tube core；And iv) align data for being used for described group is programmed into the storage In SLC memory cell group on tube core；And

The data from the multiple SLC memory cell group are transferred to the MLC memory cell group on the storage tube core In.

10. a kind of method for operating storage system, which comprises

The multiple unjustified writing commands of identification in the command queue (32) of storage control (122)；

The data that the unjustified data for being used for the multiple unjustified writing commands are transferred to the storage control (122) are slow Rush device (34)；

Merge sensing and transmission, wherein the sensing is for one storage tube core in the unjustified writing commands (108) the filling data of the storage unit (126) on, the transmission are the filling data for previous sensor from the storage tube Storage unit on core is transferred to another the data buffer in the unjustified writing commands, wherein for each Unjustified writing commands transmit the unjustified data and transmit the filling data of previous sensor in the data buffer It is middle to form complete segment；

The partial data segment for being used for each of described unjustified writing commands is transferred to institute from the data buffer State storage tube core；And

The partial data segment that will be transmitted to the storage tube core is programmed into the memory cell group on the storage tube core.