CN109840163B - Nand-Flash error data redundancy replacement method - Google Patents
Nand-Flash error data redundancy replacement method Download PDFInfo
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- CN109840163B CN109840163B CN201811614888.2A CN201811614888A CN109840163B CN 109840163 B CN109840163 B CN 109840163B CN 201811614888 A CN201811614888 A CN 201811614888A CN 109840163 B CN109840163 B CN 109840163B
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Abstract
In order to solve the technical problem that the conventional Nand-Flash write operation redundancy replacement method consumes a long time, the invention provides a Nand-Flash error data redundancy replacement method. The FIFO is divided into two parts, one part is used for storing the position of the byte to be replaced in the page buffer, the other part is used for storing the read data containing the replaced byte, all the bytes to be replaced are selected by hardware during output and are written into the redundant area at one time, and the time consumption of the whole redundant replacement process is short.
Description
Technical Field
The invention relates to a Nand-Flash error data redundancy replacement method.
Background
As shown in fig. 1, in the conventional Nand-Flash write operation, the error data redundancy replacement method is to move the data corresponding to the error unit to a good redundancy unit through a firmware program after the data is written into the Page-buffer, so as to complete the replacement, and the specific steps are as follows:
1) reading a page buffer address corresponding to an array damaged unit, wherein 2 clock cycles are needed;
2) reading word 0 according to the address in the step 1), wherein 1 clock cycle is needed;
3) adjusting the replacement unit position requires 3 clock cycles;
4) moving the data to a redundant area and shielding other three bytes, wherein 1 clock cycle is needed;
……
11) reading word3 according to the address of step 1), which requires 1 clock cycle;
12) adjusting the replacement unit position requires 3 clock cycles;
13) moving the data to the redundant area and masking the other three bytes requires 1 clock cycle.
Taking a 32-bit internal data bus as an example, using the above method, the replacement of 4 bytes using the firmware program takes approximately 22 clock cycles. If the internal clock period is 50ns, about 64/4 x 22 x 50 x 17.6us is required to complete the 64 byte replacement, which affects the performance of the Nand-Flash write operation.
Disclosure of Invention
In order to solve the technical problem that the conventional Nand-Flash write operation redundancy replacement method consumes a long time, the invention provides a Nand-Flash error data redundancy replacement method.
The technical scheme of the invention is as follows:
a Nand-Flash error data redundancy replacement method is characterized by comprising the following steps:
1) for internal data buses with different bit numbers, FIFOs with corresponding depths are adopted and are defined: defining one part of FIFO as an index area and the other part as a data area;
2) reading page buffer addresses corresponding to array damage units into the index area;
3) reading data containing the replacing bytes from the page buffer according to the page buffer address in the step 2) and storing the data into the data area;
4) taking out a byte to be replaced from all the data read in the step 3);
5) writing the bytes to be replaced, which are taken out in the step 4), into a redundant area of the page buffer.
Further, the step 1) is specifically as follows: number of bits 2 according to internal data busNWith a depth of at least 2+2N -3Defining at least 2 lower depths of the FIFO as an index area, defining the rest depths as a data area, wherein the depth of the data area is more than or equal to the number of data containing the replacing bytes to be read; wherein N is an integer of 4 or more.
Further, N is 4, 5, 6 or 7.
Further, each depth of the index area is divided into 2 on averageN-4And each part stores the address of one bad byte respectively.
Further, the step 3) is specifically as follows: reading 2 containing the replacing bytes from the page buffer according to the address in the step 2)N-32 eachNBit data and storing the bit data into the data area; each 2NThe bit data contains a byte to be replaced.
The invention also provides another Nand-Flash error data redundancy replacement method, which is characterized by comprising the following steps:
1) setting a storage FIFO and an index FIFO; wherein: for internal data buses with different bit numbers, a storage FIFO with corresponding depth is adopted;
2) reading a page buffer address corresponding to the array damage unit, and storing the lower N-3 bits of the read address as a byte index address into the index FIFO; wherein: n number of bits 2 of the internal data busNDetermining, wherein N is an integer greater than or equal to 4;
3) reading 2 from the page buffer according to the address read in the step 2)N-32 eachNData of the bits into the storage FIFO;
4) according to the byte index address stored in the index FIFO, 2 is taken out from the storage FIFON-3A byte to be replaced;
5) taking out 2) in the step 4)N-3The byte to be replaced is written in the redundant area of the page buffer.
Compared with the prior art, the invention has the beneficial effects that:
1. the FIFO is divided into two parts, one part is used for storing the position of the byte to be replaced in the page buffer, the other part is used for storing the read data containing the replaced byte, all the bytes to be replaced are selected by hardware during output and are written into the redundant area at one time, and the time consumption of the whole redundant replacement process is short.
2. The invention can be suitable for bus systems with different bit widths by adjusting the FIFO depth and the broadband.
Drawings
FIG. 1 is a schematic diagram illustrating a redundancy replacement method for error data in a conventional Nand-Flash write operation;
FIG. 2 is a schematic diagram illustrating a principle of an embodiment of a Nand-Flash error data redundancy replacement method according to the present invention;
FIG. 3 is an embodied example of a first method of the present invention;
FIG. 4 is a schematic diagram of a principle of a Nand-Flash error data redundancy replacement method according to a second embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The method for redundantly replacing the Nand-Flash error data comprises the following steps:
step 1) for internal data buses with different bit numbers, adopting FIFO with corresponding depth, and defining the FIFO: defining one part of the FIFO as an index area and the other part as a data area; specifically, the method comprises the following steps:
for a 16-bit internal data bus, adopting an FIFO with the depth of at least 4, defining at least 2 lower depths of the FIFO as an index area, defining the rest depths as data areas, and enabling the depth of the data areas to be more than or equal to the number of data containing replacement bytes read in the subsequent step 3); each depth of the index area is averagely divided into 2 parts, and each part is respectively used for storing an address of a bad byte;
for a 32-bit internal data bus, adopting an FIFO with the depth of at least 6, defining at least 2 lower depths of the FIFO as an index area, defining the rest depths as data areas, and enabling the depth of the data areas to be more than or equal to the number of data containing replacement bytes read in the subsequent step 3); each depth of the index area is averagely divided into 2 parts, and each part is respectively used for storing an address of a bad byte;
for a 64-bit internal data bus, adopting an FIFO with the depth of at least 10, defining at least 2 lower depths of the FIFO as an index area, defining the rest depths as data areas, and enabling the depth of the data areas to be more than or equal to the number of data containing replacement bytes read in the subsequent step 3); each depth of the index area is averagely divided into 4 parts, and each part is respectively used for storing an address of a bad byte;
for a 128-bit internal data bus, adopting a FIFO with the depth of at least 18, defining the lower at least 2 depths of the FIFO as an index area, defining the rest depths as data areas, and the depth of the data areas is more than or equal to the number of data containing the replaced bytes read in the step 3); equally dividing each depth of the index area into 8 parts, wherein each part is used for storing an address of a bad byte;
and so on;
for 2NBit internal data bus, using depth of at least 2+2N-3Defining at least 2 lower depths of the FIFO as index zones, the remaining depthsDefining the data area as the data area, wherein the depth of the data area is more than or equal to the number of the data containing the replacement bytes read in the step 3); divide each depth of the index zone into 2N-4Each part is used for storing the address of a bad byte; n is an integer of 4 or more.
Step 2) reading a page buffer address corresponding to the array damage unit into the index area;
step 3) reading data containing the replacement bytes from the page buffer according to the address in the step 2) and storing the data in the data area;
specifically, the method comprises the following steps:
for a 16-bit internal data bus, reading 2 16-bit data containing replacing bytes from the page buffer according to the address in the step 2), and storing the data in the data area; each 16-bit data contains a byte to be replaced;
for a 32-bit internal data bus, reading 4 32-bit data containing replacement bytes from a page buffer according to the address in the step 2), and storing the data in the data area; each 32-bit data contains a byte to be replaced;
for a 64-bit internal data bus, reading 8 64-bit data containing replacing bytes from a page buffer according to the address in the step 2), and storing the data into the data area; each 64-bit data contains a byte to be replaced;
for a 128-bit internal data bus, reading 16 128 bits of data containing replacing bytes from the page buffer according to the address in the step 2), and storing the data into the data area; each 128-bit datum contains a byte to be replaced;
and so on;
for 2NA bit internal data bus for reading 2 containing the replacing byte from the page buffer according to the address in the step 2)N-32 eachNBit data and storing the bit data into the data area; each 2NThe bit data contains a byte to be replaced; n is an integer of 4 or more.
Step 4) taking out one byte to be replaced from the data read in step 3), and taking out 2 in totalN-3A byte;
step 5) taking out 2 in the step 4)N-3Bytes are written into the redundant area of the page buffer. And step 5) when writing bytes, writing the bytes into word and writing the word into a redundant area of the page buffer, wherein 1 word is formed by 4 bytes: for a 16-bit internal data bus, half word is formed by splicing; for a 32-bit internal data bus, 1 word is formed in a splicing mode; for a 64-bit internal data bus, 2 words are formed in a whole; for a 128-bit internal data bus, a total of 4 words are tiled.
Based on the same inventive concept, the invention also provides another Nand-Flash error data redundancy replacement method, which comprises the following steps:
1) setting a storage FIFO and an index FIFO; wherein: for internal data buses with different bit numbers, a storage FIFO with corresponding depth is adopted;
2) for 2NReading a page buffer address corresponding to the array damage unit by using an internal data bus with bits (N is an integer greater than or equal to 4), and storing the lower N-3 bits of the read address into the index FIFO as a byte index address;
3) reading 2 from the page buffer according to the address read in the step 2)N-32 eachNData of the bits into the storage FIFO;
4) according to the byte index address stored in the index FIFO, 2 is taken out from the storage FIFON-3A byte to be replaced;
5) 2 to be taken outN-3The byte to be replaced is written in the redundant area of the page buffer.
Embodiment one (corresponding to the first redundancy replacement method described above):
as shown in fig. 2 and 3, taking a 32-bit internal data bus as an example, a FIFO with a depth of 6 is used, and each of the lower two depths of the FIFO is divided into two parts to store location information (address index) of a bad byte in a page buffer, and the upper four depths are used to store 4 bytes of data containing a byte to be replaced, which are read from the page buffer according to the location information in the lower two depths. When the FIFO outputs, 4 bytes (B0-B3) to be replaced are selected from byte data stored four times deep according to corresponding position information (address index), and then written into a redundant area of the page buffer. After the method is adopted, for a 32-bit internal bus, the whole redundancy replacement process needs 7 clock cycles, wherein 2 cycles read in addresses, 4 cycles read in data and 1 cycle write out data; if the internal clock period is 50ns, only about 64/4 × 7 × 50 × 5.6us is needed to complete the 64-byte replacement, which is a significant time-consuming reduction compared to the prior art.
Example two (corresponding to the second redundancy replacement method described above):
as shown in fig. 4, taking a 32-bit internal data bus as an example, firstly, according to a page buffer address corresponding to an array damaged unit, reading four 32-bit data from the page buffer into a storage FIFO, and storing the lower two bits of the page buffer address corresponding to the array damaged unit into an additionally introduced index FIFO; then, taking out four bytes to be replaced from the four data respectively according to the address stored in the index FIFO to splice into a word; and finally, writing the spliced word into a redundant area of the page buffer. The advantage of introducing the index FIFO is that the four data of the page buffer can be read in any order.
Claims (7)
1. A Nand-Flash error data redundancy replacement method is characterized by comprising the following steps:
1) for internal data buses with different bit numbers, FIFOs with corresponding depths are adopted and defined: defining one part of the FIFO as an index area and the other part as a data area; wherein the respective depth is at least 2+2N-3；
2) Reading a page buffer address corresponding to the array damage unit into the index area;
3) reading data containing the replacement bytes from the page buffer according to the page buffer address in the step 2), and storing the data into the data area;
4) taking out a byte to be replaced from all the data read in the step 3);
5) writing the bytes to be replaced, which are taken out in the step 4), into a redundant area of the page buffer.
2. The Nand of claim 1-a Flash error data redundancy replacement method, characterized in that said step 1) is specifically: number of bits 2 according to internal data busNWith a depth of at least 2+2N-3Defining at least 2 lower depths of the FIFO as an index area, defining the rest depths as a data area, wherein the depth of the data area is more than or equal to the number of data containing the replacing bytes to be read; wherein N is an integer of 4 or more.
3. The Nand-Flash error data redundancy replacement method of claim 2, wherein N is 4, 5, 6 or 7.
4. The Nand-Flash error data redundancy replacement method of claim 2 or 3, wherein each depth of the index area is divided equally into 2N-4And each part stores the address of one bad byte respectively.
5. The Nand-Flash error data redundancy replacement method according to claim 4, wherein the step 3) is specifically as follows:
reading 2 containing the replacing bytes from the page buffer according to the address in the step 2)N-32 eachNBit data and storing the bit data into the data area; each 2NThe bit data contains a byte to be replaced.
6. The Nand-Flash error data redundancy replacement method according to claim 2 or 3, wherein the step 3) is specifically:
reading 2 containing the replacing bytes from the page buffer according to the address in the step 2)N-32 eachNBit data and storing the bit data into the data area; each 2NThe bit data contains a byte to be replaced.
7. A Nand-Flash error data redundancy replacement method is characterized by comprising the following steps:
1) setting a storage FIFO and an index FIFO; wherein: for internal numbers of different digitsAccording to the bus, a storage FIFO with a corresponding depth is adopted; wherein the respective depth is at least 2+2N-3；
2) Reading a page buffer address corresponding to the array damage unit, and storing the lower N-3 bits of the read address as a byte index address into the index FIFO; wherein: n number of bits 2 of the internal data busNDetermining, wherein N is an integer greater than or equal to 4;
3) reading 2 from the page buffer according to the address read in the step 2)N-32 eachNData of the bits into the storage FIFO;
4) according to the byte index address stored in the index FIFO, 2 is taken out from the storage FIFON-3A byte to be replaced;
5) taking out 2) in the step 4)N-3The byte to be replaced is written in the redundant area of the page buffer.
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| CN101308702A (en) * | 2007-05-18 | 2008-11-19 | 瑞昱半导体股份有限公司 | Data structure suitable for flash memory and data writing and reading method thereof |
| CN101425342A (en) * | 2008-10-29 | 2009-05-06 | 四川登巅微电子有限公司 | Access method for NAND Flash redundant code |
| CN102521162A (en) * | 2011-11-30 | 2012-06-27 | 华为技术有限公司 | Method and device for cache data processing |
| CN102981921A (en) * | 2012-12-17 | 2013-03-20 | 浙江宇视科技有限公司 | Restoring method and device for failure reading of IO (image orthicon) by Raid5 array |
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| KR102200489B1 (en) * | 2014-05-30 | 2021-01-11 | 삼성전자주식회사 | Nonvolatile memory device and storage device having the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308702A (en) * | 2007-05-18 | 2008-11-19 | 瑞昱半导体股份有限公司 | Data structure suitable for flash memory and data writing and reading method thereof |
| CN101425342A (en) * | 2008-10-29 | 2009-05-06 | 四川登巅微电子有限公司 | Access method for NAND Flash redundant code |
| CN102521162A (en) * | 2011-11-30 | 2012-06-27 | 华为技术有限公司 | Method and device for cache data processing |
| CN102981921A (en) * | 2012-12-17 | 2013-03-20 | 浙江宇视科技有限公司 | Restoring method and device for failure reading of IO (image orthicon) by Raid5 array |
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