CN109830464A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109830464A CN109830464A CN201910116405.4A CN201910116405A CN109830464A CN 109830464 A CN109830464 A CN 109830464A CN 201910116405 A CN201910116405 A CN 201910116405A CN 109830464 A CN109830464 A CN 109830464A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
A kind of semiconductor structure and forming method thereof, wherein semiconductor structure includes: the first substrate, first substrate includes several device regions and several sealing ring regions, and each device region is surrounded by the sealing ring region respectively, and first substrate includes opposite the first face and the second face；Positioned at the first device layer of several device regions of the first substrate and several sealing the first face of ring region surfaces, first device layer includes the first conductive layer positioned at first the first face of substrates seal ring region surface；The first plug in the first substrates seal ring region, first plug are electrically connected with the first conductive layer, and the second face of the first substrate exposes first plug；The second conductive layer positioned at the second face surface of the first substrates seal ring region, and second conductive layer is connect with first plug.The semiconductor structure has shielding, anti-static effect.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
In the manufacture of integrated circuit (IC, Integrated Circuit), production sealing ring (also referred to as protective ring,
Seal Ring) ring is important for semiconductor technology.
With the development of semiconductor technology, integrated circuit is made into the form of chip.On wafer between adjacent chip
There can be scribe line (scribe line), by scribe line cutting crystal wafer, wafer is divided into multiple chips.However, to wafer into
During row cutting, it is also easy to produce mechanical stress, the mechanical stress is easy to damage chip.Semiconductor core in order to prevent
Damage of the piece by cutting technique can form seal ring structure between chip (chip) and scribe line.
However, the function of existing seal ring structure is relatively simple, so that the chip performance for cutting formation is still poor.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, have semiconductor structure
Shielding, electrostatic protection performance.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of semiconductor structure, comprising: the first substrate, it is described
First substrate includes several device regions and several sealing ring regions, and each device region is surrounded by the sealing ring region respectively, described
First substrate includes opposite the first face and the second face；Positioned at several device regions of the first substrate and the first face of several sealing ring regions table
First device layer in face, first device layer include the first conductive layer positioned at first the first face of substrates seal ring region surface；
The first plug in the first substrates seal ring region, first plug are electrically connected with the first conductive layer, and the first substrate
Second face exposes first plug；The second conductive layer positioned at the second face surface of the first substrates seal ring region, and it is described
Second conductive layer is connect with first plug.
Optionally, further includes: the second substrate, second substrate include the 5th face；Positioned at the 5th of second substrate the
Second device layer on face surface；Second device layer is mutually bonded with first device layer.
Optionally, further includes: operation substrate；The operation substrate surface is mutually bonded with first device layer.
Optionally, first device layer includes: the first medium layer positioned at first the first face of substrate surface；Positioned at described
First conductive layer of first medium layer surface；The second plug between the first substrate and the first conductive layer.
Optionally, further includes: be located at the described first intrabasement isolation structure, the first face of first substrate exposes
The isolation structure.
Optionally, further includes: the articulamentum positioned at the isolation structure surface, the articulamentum include opposite third face
And fourth face, and the fourth face is contacted with isolation structure surface；First device layer is located at the connection layer surface.
Optionally, the material of the articulamentum includes: polysilicon, monocrystalline silicon, amorphous silicon or metal.
Optionally, also there is third plug, third plug one end is located at the articulamentum in first device layer
Third face surface, and the other end of the third plug is in contact with the first conductive layer bottom surface.
Optionally, first plug is contacted with the fourth face of the articulamentum.
Optionally, in first device layer further include: the third conductive layer of several layers overlapping；Positioned at adjacent two layers third
The 4th plug between conductive layer or between adjacent first conductive layer and third conductive layer.
Correspondingly, the present invention also provides the forming methods of semiconductor structure described in any of the above-described, comprising: provide the first base
Bottom, first substrate includes several device regions and several sealing ring regions, and each device region is respectively by the sealing ring region packet
It encloses, first substrate includes opposite the first face and the second face；In several device regions of first substrate and several sealing rings
Area the first face surface forms the first device layer, and first device layer includes being located at first the first face of substrates seal ring region surface
First conductive layer；The first plug is formed in the first substrates seal ring region, first plug is connect with the first conductive layer,
And first second face of substrate expose first plug；The is formed on the second face surface of the first substrates seal ring region
Two conductive layers, second conductive layer are connect with the first plug.
Optionally, further includes: provide the second substrate, second substrate includes the 5th face；The of second substrate
Five faces surface form the second device layer；After forming first device layer, before forming first plug, by first base
First device layer at bottom is bonded with the second device layer of the second substrate；First device layer and the second device layer are being subjected to key
After conjunction, carry out from the second of first substrate in face of the first substrate thinned.
Optionally, after forming first device layer, before forming first plug, further includes: to first substrate
The second face carry out it is thinned.
Optionally, carrying out thinned method to second face of the first substrate includes: to provide operation substrate；By the first device
Layer is bonded with the operation substrate；By the first device layer in operation substrate be bonded after, from first substrate
Second in face of substrate carry out it is thinned.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In the semiconductor structure that technical solution of the present invention provides, the first plug in the first substrates seal ring region, institute
It states the first plug to connect with the first conductive layer, and the second face of the first substrate exposes first plug；Positioned at the first substrate
Second conductive layer on the second face surface of ring region is sealed, second conductive layer is connect with the first plug.Wafer is cut
During, it is also easy to produce mechanical stress, the mechanical stress is easy to damage chip.The sealing ring region is used to form guarantor
Retaining ring structure, the device region are used to form chip, and the protection ring structure includes the first conductive layer and the second conductive layer, described
The semiconductor structure that protection ring structure can reduce device region is damaged by mechanical stress bring.First plug will be located at
First conductive layer on the first face surface of the first substrate and the second conductive layer positioned at first the second face of substrate surface connect
Come, makes to form electrical connection access between the first conductive layer and the second conductive layer.Second when second face of the first substrate is conductive
When layer ground connection, due to being electrically connected between the first conductive layer and the second conductive layer of the first device layer, sealing ring region can shield institute
State the external interference that semiconductor structure is subject to.Simultaneously as the first face of the first substrate has the first device layer, first device
Part layer can generate the aggregation of electrostatic charge, due to being electrically connected between the first conductive layer and the second conductive layer of the first device layer, lead to
The second conductive layer ground connection is crossed, it can be by the Electro-static Driven Comb in the first device layer.To sum up, the semiconductor structure has shielding, prevents
Electrostatic efficiency.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of semiconductor structure；
Fig. 2 to Figure 10 is the structural schematic diagram of each step of the method for forming semiconductor structure of one embodiment of the invention；
Figure 11 to Figure 15 is the structural schematic diagram of each step of the method for forming semiconductor structure of another embodiment of the present invention.
Specific embodiment
As described in background, the function of existing seal ring structure is relatively simple.
Fig. 1 is a kind of structural schematic diagram of semiconductor structure.
Referring to FIG. 1, substrate 100, the substrate 100 includes several device region A and several sealing ring region B, and each device
Part area A is surrounded by the sealing ring region B respectively, and the substrate 100 includes opposite the first face 101 and the second face 102；Positioned at institute
State the first device layer 110 of several device region A of substrate 100 and several sealing 101 surfaces of the first face ring region B, first device
Layer 110 includes the first conductive layer 111 that 101 surface of the first face ring region B is sealed positioned at substrate 100；Ring region is sealed positioned at substrate 100
Second conductive layer 120 on 102 surface of the second face of B.
In above-mentioned semiconductor structure, during cutting to wafer, it is also easy to produce mechanical stress, the mechanical stress is held
Easily device region A is caused to damage.The sealing ring region B of above-mentioned semiconductor structure surrounds device region A, can play to device region A
Protective effect, so that the mechanical stress for preventing cutting crystal wafer from generating has an impact device region A.However, above-mentioned semiconductor structure
Front metal ground connection when, i.e. the second conductive layer 120 be grounded when, shielding, antistatic can not be played to the device region A of insulation blocking
Effect.
In order to solve the technical problem, the present invention provides a kind of semiconductor structure, comprising: the first substrate, described first
Substrate includes several device regions and several sealing ring regions, and each device region is surrounded by the sealing ring region respectively, and described first
Substrate includes opposite the first face and the second face；Positioned at several device regions of the first substrate and several sealing the first face of ring region surfaces
First device layer, first device layer include the first conductive layer positioned at first the first face of substrates seal ring region surface；It is located at
The first plug in first substrates seal ring region, first plug is electrically connected with the first conductive layer, and the second of the first substrate
Face exposes first plug；The second conductive layer positioned at the second face surface of the first substrates seal ring region, and described second
Conductive layer is connect with first plug.The semiconductor structure has shielding, anti-static effect.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 2 to Figure 10 is the structural schematic diagram of each step of method for forming semiconductor structure in one embodiment of the invention.
Referring to FIG. 2, providing the first substrate 200, first substrate 200 includes several device region A and several sealing rings
Area B and each device region A are surrounded by the sealing ring region B respectively, and first substrate 200 includes opposite 201 He of the first face
Second face 202.
In the present embodiment, the material of first substrate 200 is monocrystalline silicon.
In other embodiments, the material of first substrate can also be polysilicon or amorphous silicon.First substrate
Material can also be the semiconductor materials such as germanium, SiGe or GaAs.First substrate can also be that semiconductor-on-insulator is led
Body structure, the semiconductor-on-insulator structure include insulator and the semiconductor material layer on insulator, described partly to lead
The material of body material layer includes the semiconductor materials such as silicon, germanium, SiGe, GaAs or indium gallium arsenic.
In the present embodiment, further includes: the isolation structure 210 in the first substrate 200, first substrate 200
First face 201 exposes the isolation structure 210.
The material of the isolation structure 210 includes: silica, silicon nitride, carbonitride of silicium, silicon carbide, aluminium oxide, oxidation
Hafnium, silicon oxynitride or silicon oxide carbide.
In the present embodiment, the material of the isolation structure 210 is silica.
In the present embodiment, further includes: the articulamentum positioned at 210 surface of isolation structure.Incorporated by reference to Fig. 3, to the connection
The forming process of layer is illustrated.
Referring to FIG. 3, forming articulamentum 220, the company on 210 surface of isolation structure of the first substrate 200 sealing ring region B
Connecing layer 220 includes opposite third face 221 and fourth face 222, and the fourth face 222 is in contact with 210 surface of isolation structure.
The articulamentum 220, on the other hand on the one hand can be used as the etching stop layer for being subsequently formed third opening is
It is subsequent that electrical connection access is formed between the first conductive layer and the second conductive layer.
The forming method of the articulamentum 220 includes: in 200 first face of the first substrate, 201 surface and isolation junction
210 surface of structure forms connecting material film (not shown)；The first mask layer is formed (in figure not in the connecting material film surface
Show), first mask layer exposes the surface of part connecting material film；Using first mask layer as described in mask etching
Connecting material film forms articulamentum 220 on 210 surface of isolation structure.
The formation process of the connecting material film includes: chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation.
The material of the connecting material film includes: polysilicon, monocrystalline silicon, amorphous silicon or metal.In the present embodiment, described
The material of connecting material film is polysilicon, correspondingly, the material of the articulamentum 220 formed is polysilicon.
After forming the articulamentum 220, in the first face several device region A of first substrate 200 and several sealing ring region B
201 surfaces form the first device layer, and first device layer includes being located at the first substrate 200 to seal 201 surface of the first face ring region B
The first conductive layer.
In the present embodiment, first device layer includes: the first medium layer positioned at 200 surface of the first substrate；It is located at
First conductive layer of the first medium layer surface；The second plug between the first substrate 200 and the first conductive layer.It please tie
Fig. 4 to fig. 6 is closed, the forming process of first device layer is illustrated.
Referring to FIG. 4, forming first medium layer 231 on 200 first face of the first substrate, 201 surface.
The material of the first medium layer 231 includes: silica, silicon nitride, carbonitride of silicium, silicon carbide, aluminium oxide, oxidation
Hafnium, silicon oxynitride or silicon oxide carbide.
In the present embodiment, the material of the first medium layer 231 is silica.
The formation process of the first medium layer 231 includes: chemical vapor deposition process, physical gas-phase deposition or heat
Oxidation technology.
Referring to FIG. 5, the second plug 232 is formed in the first medium layer 231 of the first substrate 200 sealing ring region B, it is described
Second plug 232 is located at 201 surface of the first face of the first substrate 200.
First device layer includes the first medium layer 231, the second plug 232 and the first conductive layer being subsequently formed.
The forming method of second plug 232 includes: in the first medium layer 231 of the first substrate 200 sealing ring region B
The second opening (not shown) is formed, until exposing 200 first face 201 of the first substrate；It is described second opening in and
231 surface of first medium layer forms the second plug film (not shown)；The second plug film is planarized, until exposing the
One dielectric layer, 231 surface forms the second plug 232 in the first medium layer 231.
The material of the second plug film includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.In the present embodiment, institute
The material for stating the second plug film is copper, correspondingly, the material of the second plug 232 formed is copper.
The technique for planarizing the second plug film includes: chemical mechanical milling tech.
In the present embodiment, also there is third plug 240, the third plug 240 is located in first device layer 230
220 third face of articulamentum, 221 surface.
The third plug 240 is in contact with the third face 221 of articulamentum 220, for for it is subsequent in the first conductive layer and
Electrical connection access is formed between second conductive layer.
The forming method of the third plug 240 includes: to form third in the first medium layer 231 of sealing ring region B to open
Mouth (not shown), until exposing 220 third face 221 of articulamentum；The third opening in and first medium layer
231 surfaces form third plug film (not shown), the full third opening of third plug film filling；Described in planarization
Third plug film forms third plug 240 until exposing 231 surface of first medium layer in the first medium layer 231.
In the present embodiment, the material of second plug 232 is identical with the material of third plug 240, is copper.
In the present embodiment, second plug 232 and third plug 240 are simultaneously formed, so as to simplify work
Skill saves preparation cost and preparation time.
In other embodiments, it is formed after second plug, forms the third plug；Or form the third
After plug, second plug is formed.
Referring to FIG. 6, forming the first conductive layer 250 on part 231 surface of first medium layer, and described first is conductive
Layer 250 covers the surface of the second plug 232 and third plug 240.
The material of first conductive layer 250 includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.In the present embodiment,
The material of first conductive layer 250 is tungsten.
The forming method of first conductive layer 250 include: 231 surface of first medium layer, third plug 240 with
And 232 surface of the second plug forms the second conductive film (not shown)；The second exposure mask is formed in the described second conductive film surface
Layer (not shown), second mask layer expose the surface of the second conductive film of part；It is to cover with second mask layer
Film etches second conductive film until exposing the surface of first medium layer 231, forms first conductive layer 250.
First device layer 230 includes: first medium layer 231, the second plug 232 and the first conductive layer 250.
In the present embodiment, first device layer 230 includes: first medium layer 231, the second plug 232, third plug
240 and first conductive layer 250.
In other embodiments, in first device layer further include: the third conductive layer of several layers overlapping；Positioned at adjacent
The 4th plug between two layers of third conductive layer or between adjacent first conductive layer and third conductive layer.
In the present embodiment, after forming first conductive layer 250, before being subsequently formed the first plug, further includes: to described
Second face 202 of the first substrate 200 carries out thinned.Incorporated by reference to Fig. 7 to Fig. 8, to the second face 202 of first substrate 200 into
The thinned process of row is illustrated.
Referring to FIG. 7, providing operation substrate 300,250 surface of the first conductive layer and the operation substrate 300 are subjected to key
It closes.
The operation substrate 300 can be common silicon substrate or other suitable substrates.
First conductive layer, 250 surface and operation substrate 300 are bonded together, the entirety for increasing semiconductor structure is conducive to
Thickness is conducive to the progress of subsequent technique.
In the present embodiment, the operation substrate 300 is common silicon substrate.The material and first of the operation substrate 300
The material of substrate 200 is identical, is silicon (Si).
In other embodiments, the handle substrate material includes germanium (Ge), SiGe (SiGe), silicon carbide, on insulator
Silicon, germanium on insulator or GaAs.
250 surface of the first conductive layer is mutually bonded with the side of operation substrate 300 by bonding technology.
In the present embodiment, the bonding technology is oxide fusion bonding technology.
Referring to FIG. 8, after 250 surface of the first conductive layer is bonded with the operation substrate 300, from described first
200 second face 202 of substrate carries out the first substrate 200 thinned.
First conductive layer 250 is bonded with operation 300 phase of substrate, and after bonding by first substrate 200
It is overturn together with operation substrate 300, so that the second face 202 of first substrate 200 is upwards.
Then, reduction processing is carried out to the first substrate 200 from the second face 202 of first substrate 200.
The method of the reduction processing includes: chemical mechanical milling tech.
Referring to FIG. 9, carrying out the reduction processing to the first substrate 200 from the second face 202 of first substrate 200
Afterwards, the first plug 260, first plug 260 and the first conductive layer 250 are formed in first substrate 200 sealing ring region B
Connection, and the second face 202 of the first substrate 200 exposes first plug 260.
In the present embodiment, first plug 260 is in contact with the fourth face 222 of articulamentum 220.
First plug 260 is not only connect with the first conductive layer 250, is also connected with the second conductive layer being subsequently formed
It connects, to form electrical connection access between the first conductive layer and the second conductive layer to be subsequent.
The forming method of first plug 260 includes: to form the in the first substrate 200 sealing the second face ring region B 202
One opening (not shown), until exposing the fourth face 222 of articulamentum 220；It is described first opening in and the first substrate
200 second face, 202 surface forms the first plug film (not shown), and the first plug film is full of first opening；It is flat
The smoothization first plug film, until 202 surface of the first 200 second face of substrate is exposed, in 200 sealing ring of the first substrate
The first plug 260 is formed in the second face area B 202.
The technique for planarizing the first plug film includes: chemical mechanical milling tech.
In the present embodiment, it after the opening of formation first, before filling full first plug film in first opening, also wraps
It includes: forming insulating layer (not shown) in first opening sidewalls.
The forming method of the insulating layer includes: in the side wall of first opening and bottom and the first substrate 200 the
Two faces, 202 surface forms insulating film；Remove the insulation of 200 second face of the first substrate, 202 surface and the first open bottom
Film forms insulating layer in the side wall of first opening.
The insulating layer is isolated for realizing the first plug 260 and the first substrate 200.
Referring to FIG. 10, after forming first plug 260, in the second face of first substrate 200 sealing ring region B
202 surfaces form the second conductive layer 270, and second conductive layer 270 is connect with the first plug 260.
The material of second conductive layer 270 includes: Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
In the present embodiment, the material of second conductive layer 270 is tungsten.
The formation process of second conductive layer 270 includes: chemical vapor deposition process, physical gas-phase deposition.
Positioned at the articulamentum 220 of sealing ring region B, in the first medium layer 231 of sealing ring region B with articulamentum 220 the
The third plug 240 and be located in the first substrate 200 sealing the second face ring region B 202 and articulamentum 220 that three faces 221 are in contact
First conductive layer 250 and the second conductive layer 270 are electrically connected by the first plug 260 that fourth face 222 is in contact jointly, make first to lead
Electrical connection access is formed between electric layer 250 and the second conductive layer 270.
The sealing ring region B is used to form protection ring structure, and the device region A is used to form chip, the protection ring knot
Structure includes the first conductive layer 250 and the second conductive layer 270, and the protection ring structure can reduce the semiconductor structure of device region A
It is damaged by mechanical stress bring.When second conductive layer 270 ground connection, since the first conductive layer 250 and second is conductive
It is electrically connected between layer 270, sealing ring region B can shield the external interference that the semiconductor structure is subject to.Simultaneously as the first base
First face, 201 surface at bottom 200 has the first device layer 230, and first device layer 230 can generate the aggregation of electrostatic charge,
Due to being electrically connected between the first conductive layer 250 and the second conductive layer 270 of the first device layer 230, connect by the second conductive layer 270
Ground, can be by the Electro-static Driven Comb in the first device layer 230.To sum up, the semiconductor structure that the method is formed is quiet with shielding, preventing
Electric effect.
Correspondingly, the present invention also provides the semiconductor structures that the above method is formed, referring to FIG. 10, including: the first substrate
200, first substrate 200 includes several device region A and several sealing ring region B, and each device region A is respectively by the sealing
Ring region B is surrounded, and first substrate 200 includes opposite the first face 201 and the second face 202；Positioned at several devices of the first substrate 200
The first device layer 230 of part area A and several sealing 201 surfaces of the first face ring region B, first device layer 230 include being located at the
First conductive layer 250 on one substrate 200 sealing, 201 surface of the first face ring region B；The in the first substrate 200 sealing ring region B
One plug 260, first plug 260 are electrically connected with the first conductive layer 250, and the second face 202 of the first substrate 200 exposes
First plug 260；The second conductive layer 270 positioned at 202 surface of the second face of the first substrate 200 sealing ring region B, and it is described
Second conductive layer 270 is connect with first plug 260.
The sealing ring region B is used to form protection ring structure, and the device region A is used to form chip, the protection ring knot
Structure includes the first conductive layer 250 and the second conductive layer 270, and the protection ring structure can reduce the semiconductor structure of device region A
It is damaged by mechanical stress bring.First plug 260 will be located at the first of 201 surface of the first face of the first substrate 200
Conductive layer 250 and the second conductive layer 270 positioned at 202 surface of the first 200 second face of substrate are electrically connected, and make first to lead
Electrical connection access is formed between electric layer 250 and the second conductive layer 270.When second conductive layer 270 ground connection, lead due to first
It is electrically connected between electric layer 250 and the second conductive layer 270, it is dry that sealing ring region B can shield the external world that the semiconductor structure is subject to
It disturbs.Simultaneously as 201 surface of the first face of the first substrate 200 has the first device layer 230, first device layer 230 can be produced
The aggregation of raw electrostatic charge is led to due to being electrically connected between the first conductive layer 250 and the second conductive layer 270 of the first device layer 230
The second conductive layer 270 ground connection is crossed, it can be by the Electro-static Driven Comb in the first device layer 230.To sum up, the semiconductor structure has screen
It covers, anti-static effect.
The semiconductor structure further include: operation substrate 300；The of operation 300 surface of substrate and the first substrate 200
First device layer, the 230 phase bonding on 201 surfaces on one side.
First device layer 230 includes: the first medium layer 231 positioned at 201 surface of the first 200 first face of substrate；Position
The first conductive layer 250 in 231 surface of first medium layer；Between the first substrate 200 and the first conductive layer 250
Two plugs 232.
The semiconductor structure further include: the isolation structure 210 in first substrate 200, first substrate
200 the first face 201 exposes the isolation structure 210.
The semiconductor structure further include: the articulamentum 220 positioned at 210 surface of isolation structure, the articulamentum 220
Including opposite third face 221 and fourth face 222, and the fourth face 222 is contacted with 210 surface of isolation structure；Described first
Device layer 230 is located at 220 surface of articulamentum.
The material of the articulamentum 220 includes: polysilicon, monocrystalline silicon, amorphous silicon or metal.
Also there is third plug 240, the third plug 240 is located at the articulamentum 220 in first device layer 230
221 surface of third face, and the other end of the third plug 240 is in contact with 250 bottom surface of the first conductive layer.
First plug 260 is contacted with the fourth face 222 of the articulamentum 220.
In other embodiments, in first device layer further include: the third conductive layer of several layers overlapping；Positioned at adjacent
The 4th plug between two layers of third conductive layer or between adjacent first conductive layer and third conductive layer.
Figure 11 to Figure 15 is the structural schematic diagram of each step of method for forming semiconductor structure in another embodiment of the present invention.
The present embodiment and above-described embodiment only difference is that, provide the second substrate, and the second substrate surface has second
Device layer；First device layer surface of first substrate is bonded with the second device layer surface of the second substrate；It is described
After first device layer surface is bonded with second device layer surface, carried out from the second of first substrate in face of the first substrate
It is thinned.
Figure 11 to Figure 15 is each step of Subsequent semiconductor Structure formation method on the basis of Fig. 6 in the aforementioned embodiment
Structural schematic diagram.
Figure 11 is please referred to, the second substrate 400 is provided, second substrate 400 includes the 5th face 41；In second substrate
400 41 surface of the 5th face forms the second device layer 410.
In the present embodiment, second device layer 410 includes: the grid positioned at 41 surface of the second the 5th face of substrate 400
Structure 401；It is located at the source and drain doping area 402 in 401 the second substrate of two sides 400 of gate structure；Positioned at the second substrate 400,
The second dielectric layer 403 on 402 surface of gate structure 401 and source and drain doping area, the second dielectric layer 403 is interior to have the first contact
Hole (not marking in figure) and the second contact hole (not marking in figure), the first contact hole bottom-exposed go out 401 table of gate structure
Face, the second contact hole bottom-exposed go out 402 surface of source and drain doping area；Connecing in the first contact hole and the second contact hole
Plug 404 is touched, the contact plunger 404 is full of the first contact hole and the second contact hole；In the second dielectric layer 403 and contact
404 surface of plug forms third dielectric layer 405, has interconnection structure 406, the interconnection structure in the third dielectric layer 405
406 contact with contact plunger 404；The 4th conductive layer 407 positioned at 405 surface of third dielectric layer, the 4th conductive layer 407 with
Interconnection structure 406 contacts.
In other embodiments, second device layer includes capacitor, inductance, bipolar junction transistor or PN structure.
Figure 12 is please referred to, by second device on 230 surface of the first device layer of first substrate 200 and the second substrate 400
410 surface of part layer is bonded.
230 surface of the first device layer and second base on 201 surface of the first 200 first face of substrate will be located at by bonding technology
Second device layer 410 on 41 surface of the 5th face at bottom 400 is bonded.
In the present embodiment, the bonding technology is oxide fusion bonding technology.
Figure 13 is please referred to, behind 230 surface of the first device layer and 410 surface bond of the second device layer, from described
Second face 202 of the first substrate 200 carries out the first substrate 200 thinned.
The reduction processing is identical to the reduction processing method of the first substrate 200 with above-described embodiment, no longer superfluous herein
It states.
Figure 14 is please referred to, after carrying out the reduction processing, first is formed in first substrate 200 sealing ring region B and inserts
Plug 280, and the second face 202 of the first substrate 200 exposes first plug 280.
The formation side of first plug 260 (shown in Fig. 9) in the forming method and above-described embodiment of first plug 280
Method is identical, and details are not described herein.
Figure 15 is please referred to, after forming first plug 280, in the second face of first substrate 200 sealing ring region B
202 surfaces form the second conductive layer 290, and second conductive layer 290 is connect with the first plug 280.
Second conductive layer 270 in the forming method and above-described embodiment of second conductive layer 290 (shown in Figure 10)
Forming method is identical, and details are not described herein.
Correspondingly, please referring to Figure 15 the present invention also provides a kind of semiconductor structure, comprising: the first substrate 200, described
One substrate 200 includes several device region A and several sealing ring region B, and each device region A is surrounded by the sealing ring region B respectively,
First substrate 200 includes opposite the first face 201 and the second face 202；If positioned at several device region A of the first substrate 200 and
First device layer 230 on 201 surface of the first face dry seal ring region B, first device layer 230 include being located at the first substrate 200
Seal first conductive layer 250 on 201 surface of the first face ring region B；The first plug in the first substrate 200 sealing ring region B
280, first plug 280 is electrically connected with the first conductive layer 250, and the second face 202 of the first substrate 200 exposes described
One plug 280；The second conductive layer 290 positioned at 202 surface of the second face of the first substrate 200 sealing ring region B, and described second leads
Electric layer 290 is connect with first plug 280.
The sealing ring region B is used to form protection ring structure, and the device region A is used to form chip, the protection ring knot
Structure includes the first conductive layer 250 and the second conductive layer 290, and the protection ring structure can reduce the semiconductor structure of device region A
It is damaged by mechanical stress bring.First plug 280 will be located at the first of 201 surface of the first face of the first substrate 200
Conductive layer 250 and the second conductive layer 290 positioned at 202 surface of the first 200 second face of substrate are electrically connected, and make first to lead
Electrical connection access is formed between electric layer 250 and the second conductive layer 290.When second conductive layer 290 ground connection, lead due to first
It is electrically connected between electric layer 250 and the second conductive layer 290, it is dry that sealing ring region B can shield the external world that the semiconductor structure is subject to
It disturbs.Simultaneously as 201 surface of the first face of the first substrate 200 has the first device layer 230, first device layer 230 can be produced
The aggregation of raw electrostatic charge is led to due to being electrically connected between the first conductive layer 250 and the second conductive layer 290 of the first device layer 230
The second conductive layer 290 ground connection is crossed, it can be by the Electro-static Driven Comb in the first device layer 230.To sum up, the semiconductor structure has screen
It covers, anti-static effect.
The semiconductor structure further include: the second substrate 400, second substrate 400 include the 5th face 41；Positioned at described
Second device layer 410 on 41 surface of the 5th face of the second substrate 400；The first of second device layer 410 and the first substrate 200
First device layer, 230 phase on 201 surface of face is bonded.
First device layer 230 includes: the first medium layer 231 positioned at 201 surface of the first 200 first face of substrate；Position
The first conductive layer 250 in 231 surface of first medium layer；Between the first substrate 200 and the first conductive layer 250
Two plugs 232.
The semiconductor structure further include: the isolation structure 210 in first substrate 200, first substrate
200 the first face 201 exposes the isolation structure 210.
The semiconductor structure further include: the articulamentum 220 positioned at 210 surface of isolation structure, the articulamentum 220
Including opposite third face 221 and fourth face 222, and the fourth face 222 is contacted with 210 surface of isolation structure；Described first
Device layer 230 is located at 220 surface of articulamentum.
The material of the articulamentum 220 includes: polysilicon, monocrystalline silicon, amorphous silicon or metal.
Also there is third plug 240, described 240 one end of third plug is located at the connection in first device layer 230
221 surface of third face of layer 220, and the other end of the third plug 240 connects with 250 bottom surface of the first conductive layer
Touching.
First plug 280 is contacted with the fourth face 222 of the articulamentum 220.
In other embodiments, in first device layer further include: the third conductive layer of several layers overlapping；Positioned at adjacent
The 4th plug between two layers of third conductive layer or between adjacent first conductive layer and third conductive layer.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of semiconductor structure characterized by comprising
First substrate, first substrate includes several device regions and several sealing ring regions, and each device region is respectively by described
It seals ring region to surround, first substrate includes opposite the first face and the second face；
Positioned at the first device layer of several device regions of the first substrate and several sealing the first face of ring region surfaces, first device layer
The first conductive layer including being located at first the first face of substrates seal ring region surface；
The first plug in the first substrates seal ring region, first plug is electrically connected with the first conductive layer, and the first base
Second face at bottom exposes first plug；
The second conductive layer positioned at the second face surface of the first substrates seal ring region, and second conductive layer is inserted with described first
Plug connection.
2. semiconductor structure as described in claim 1, which is characterized in that further include: the second substrate, second substrate include
5th face；The second device layer positioned at the 5th face surface of second substrate；Second device layer and first device
Layer is mutually bonded.
3. semiconductor structure as described in claim 1, which is characterized in that further include: operation substrate；The operation substrate surface
It is mutually bonded with first device layer.
4. semiconductor structure as described in claim 1, which is characterized in that first device layer includes: positioned at the first substrate
The first medium layer in the first face surface；Positioned at first conductive layer of the first medium layer surface；Positioned at the first substrate with
The second plug between first conductive layer.
5. semiconductor structure as described in claim 1, which is characterized in that further include: it is located at the described first intrabasement isolation
First face of structure, first substrate exposes the isolation structure.
6. semiconductor structure as claimed in claim 5, which is characterized in that further include: the company positioned at the isolation structure surface
Layer is connect, the articulamentum includes opposite third face and fourth face, and the fourth face is contacted with isolation structure surface；Described
One device layer is located at the connection layer surface.
7. semiconductor structure as claimed in claim 6, which is characterized in that the material of the articulamentum includes: polysilicon, monocrystalline
Silicon, amorphous silicon or metal.
8. semiconductor structure as claimed in claim 6, which is characterized in that also there is third plug in first device layer,
Third plug one end is located at the third face surface of the articulamentum, and the other end of the third plug is led with described first
Electric layer bottom surface is in contact.
9. semiconductor structure as claimed in claim 8, which is characterized in that the fourth face of first plug and the articulamentum
Contact.
10. semiconductor structure as described in claim 1, which is characterized in that in first device layer further include: several layers weight
Folded third conductive layer；Between adjacent two layers third conductive layer or between adjacent first conductive layer and third conductive layer
Four plugs.
11. the forming method of the semiconductor structure as described in claims 1 to 10 characterized by comprising
First substrate is provided, first substrate includes several device regions and several sealing ring regions, and each device region respectively by
The sealing ring region is surrounded, and first substrate includes opposite the first face and the second face；
The first device layer, first device are formed in several device regions of first substrate and several sealing ring regions the first face surface
Part layer includes the first conductive layer positioned at first the first face of substrates seal ring region surface；
The first plug is formed in the first substrates seal ring region, first plug is connect with the first conductive layer, and first
Second face of substrate exposes first plug；
The second conductive layer, second conductive layer and the first plug are formed on the second face surface of the first substrates seal ring region
Connection.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that further include: the second substrate is provided,
Second substrate includes the 5th face；The second device layer is formed on the 5th face surface of second substrate；Forming described the
After one device layer, before forming first plug, by the second device of the first device layer of first substrate and the second substrate
Layer is bonded；After being bonded the first device layer with the second device layer, first is faced from the second of first substrate
Substrate carries out thinned.
13. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that form first device layer
Afterwards, before forming first plug, further includes: carried out to the second face of first substrate thinned.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that second face of the first substrate
Carrying out thinned method includes: to provide operation substrate；First device layer is bonded with the operation substrate；By the first device
Part layer in operation substrate be bonded after, from first substrate second in face of substrate carry out it is thinned.
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