CN109828879A - Adjustment method, device, computer equipment and the storage medium of hardware device - Google Patents
Adjustment method, device, computer equipment and the storage medium of hardware device Download PDFInfo
- Publication number
- CN109828879A CN109828879A CN201910157173.7A CN201910157173A CN109828879A CN 109828879 A CN109828879 A CN 109828879A CN 201910157173 A CN201910157173 A CN 201910157173A CN 109828879 A CN109828879 A CN 109828879A
- Authority
- CN
- China
- Prior art keywords
- interface
- data
- test
- register
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Abstract
The invention discloses the adjustment method of hardware device, device, computer equipment and storage mediums, belong to Electronic Testing field.The present invention is tested by device under test data-interface, read the value of data-interface current state and register corresponding with data-interface, value by adjusting register makes the maximum valid window of data-interface, it realizes and shortens debug time, the purpose of Devices to test system stability is promoted, while reducing human cost.
Description
Technical field
The present invention relates to the adjustment method of Electronic Testing field more particularly to hardware device, device, computer equipment and deposit
Storage media.
Background technique
Existing hardware device interface debugging can only estimate SOC (System on Chip, system level chip) internal signal
Settling time and retention time, do not account for clock (CLK)/delay, shake etc. of data (DATA) signal inside SOC and ask
Topic cannot accurately reflect the real window of SOC internal signal sampling, and signal, which exists, samples unstable risk, and when test
Between long expend a large amount of manpower.
Summary of the invention
In view of the above-mentioned problems, now providing a kind of hardware for being intended to carry out interface debugging automatically and promoting hardware device stability
Adjustment method, device, computer equipment and the storage medium of equipment.
A kind of adjustment method of hardware device, comprising:
Device under test data-interface is tested；
The value of register corresponding with the data-interface in the Devices to test is obtained, the value for adjusting the register makes
The maximum valid window of the data-interface.
Preferably, the value for obtaining register corresponding with the data-interface in the Devices to test, adjusts the deposit
The value of device makes the maximum valid window of the data-interface, comprising:
The register is called by serial ports corresponding with the data-interface, reads the value of the register, the number
It include data-signal and clock signal according to the signal that interface exports；
Value by adjusting the register adjusts the clock signal delay of the corresponding data-interface, described in obtaining
The maximum valid window of data-interface.
Preferably, the data-interface includes: gigabit ethernet interface, 100 m ethernet interface, utilizing camera interface, storage
Interface and WIFI interface.
Preferably, device under test data-interface is tested, comprising:
The Devices to test is powered on and initialized；
Control that the Devices to test is in running order to test the data-interface.
The present invention also provides a kind of debugging apparatus of hardware device, comprising:
Communication unit is connect with Devices to test, for being communicated with the Devices to test；
Test cell connects the communication unit, is tested for device under test data-interface；
Debugging unit connects the communication unit and the test cell, for obtain in the Devices to test with it is described
The value of the corresponding register of data-interface, the value for adjusting the register make the maximum valid window of the data-interface.
Preferably, the debugging unit includes:
Module is obtained, for calling the register by serial ports corresponding with the data-interface, reads the deposit
The signal of the value of device, the data-interface output includes data-signal and clock signal；
Adjustment module, the clock signal for adjusting the corresponding data-interface for the value by adjusting the register are prolonged
When, to obtain the maximum valid window of the data-interface.
Preferably, the data-interface includes: gigabit ethernet interface, 100 m ethernet interface, utilizing camera interface, storage
Interface and WIFI interface.
Preferably, the test cell controls the Devices to test for being powered on and initialized to the Devices to test
It is in running order that the data-interface is tested.
The present invention also provides a kind of computer equipment, the computer equipment, including memory, processor and storage
On a memory and the computer program that can run on a processor, the processor are realized when executing the computer program
The step of stating method.
The present invention also provides a kind of computer readable storage mediums, are stored thereon with computer program, it is characterised in that:
The step of above method is realized when the computer program is executed by processor.
Above-mentioned technical proposal the utility model has the advantages that
In the technical program, tested by device under test data-interface, read the current state of data-interface with
And the value of register corresponding with data-interface, the value by adjusting register make the maximum valid window of data-interface, realize
Shorten debug time, promote the purpose of Devices to test system stability, while reducing human cost.
Detailed description of the invention
Fig. 1 is the flow chart of the adjustment method of hardware device of the present invention；
Fig. 2 is a kind of module map of embodiment of the debugging apparatus of hardware device of the present invention；
Fig. 3 is a kind of module map of embodiment of debugging unit of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
As shown in Figure 1, the present invention provides a kind of adjustment methods of hardware device, comprising:
S1. device under test data-interface is tested；
It should be understood that the data-interface can include: gigabit ethernet interface, 100 m ethernet interface, camera
Interface, memory interface and WIFI interface etc..Wherein, each middle interface can be used method of the invention and be debugged.
Further, the step S1 device under test data-interface is tested, comprising:
S11. the Devices to test is powered on and initialized, to ensure that Devices to test can work normally；
S12. control that the Devices to test is in running order to test the data-interface.
S2. the value for obtaining register corresponding with the data-interface in the Devices to test, adjusts the register
Value makes the maximum valid window (that is: valid window maximizes) of the data-interface.
When the window of data-interface effectively maximizes, the unstable situation hair such as signal transmission delay, shake can avoid
It is raw, it is ensured that the stability of signal transmission and the stability of Devices to test.
Further, the step S2 obtains the value of register corresponding with the data-interface in the Devices to test,
The value for adjusting the register makes the maximum valid window of the data-interface, comprising:
S21. the register is called by serial ports corresponding with the data-interface, reads the value of the register, institute
The signal for stating data-interface output includes data-signal and clock signal；
The corresponding corresponding serial ports of each data-interface, the corresponding corresponding register of the serial ports and each data-interface
A corresponding corresponding register, can by the value of the register
S22. the clock signal delay of the corresponding data-interface is adjusted, by adjusting the value of the register to obtain
The maximum valid window of the data-interface.
By the range of the clock signal delay acquisition window of data-interface, to obtain the effective window of maximum of data-interface
Mouthful.
In the present embodiment, tested by device under test data-interface, read the current state of data-interface with
And the value of register corresponding with data-interface, the value by adjusting register make the maximum valid window of data-interface, realize
Shorten debug time, promote the purpose of Devices to test system stability, while reducing human cost.
As shown in Fig. 2, a kind of debugging apparatus of hardware device, comprising: communication unit 1, test cell 2 and debugging unit 3,
Wherein:
Communication unit 1, connect with Devices to test, for being communicated with the Devices to test；
Test cell 2 connects the communication unit 1, is tested for device under test data-interface；
Debugging unit 3 connects the communication unit 1 and the test cell 2, for obtain in the Devices to test with institute
The value for stating the corresponding register of data-interface, the value for adjusting the register make the maximum valid window of the data-interface.
It should be understood that the data-interface can include: gigabit ethernet interface, 100 m ethernet interface, camera
Interface, memory interface and WIFI interface etc..Wherein, each middle interface can be used the debugging apparatus of hardware device of the invention into
Row debugging.
In the present embodiment, tested by device under test data-interface, read the current state of data-interface with
And the value of register corresponding with data-interface, the value by adjusting register make the maximum valid window of data-interface, realize
Shorten debug time, promotes the purpose of Devices to test system stability.Using hardware device debugging apparatus device under test into
The effect debugged automatically can be achieved in line interface debugging, without artificial debugging manually, reduces while improving debugging efficiency
Human cost.
As shown in figure 3, in a preferred embodiment, the debugging unit 3 can include: obtain module 31 and adjustment module
32, in which:
Module 31 is obtained, for calling the register by serial ports corresponding with the data-interface, is posted described in reading
The signal of the value of storage, the data-interface output includes data-signal and clock signal；
Adjustment module 32 adjusts the clock signal of the data-interface for the value adjustment by the register accordingly
Delay, to obtain the maximum valid window of the data-interface.
When the window of data-interface effectively maximizes, the unstable situation hair such as signal transmission delay, shake can avoid
It is raw, it is ensured that the stability of signal transmission and the stability of Devices to test.
In a preferred embodiment, the test cell 2 is for being powered on and initialized the Devices to test, to ensure
Devices to test can work normally, and control that the Devices to test is in running order to test the data-interface.
The present invention also provides a kind of computer equipment, the computer equipment, including memory, processor and storage
On a memory and the computer program that can run on a processor, the processor are realized when executing the computer program
The step of stating method.
The present invention also provides a kind of computer readable storage mediums, are stored thereon with computer program, it is characterised in that:
The step of above method is realized when the computer program is executed by processor.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of adjustment method of hardware device characterized by comprising
Device under test data-interface is tested；
The value for obtaining register corresponding with the data-interface in the Devices to test, adjust the register value make it is described
The maximum valid window of data-interface.
2. the adjustment method of hardware device according to claim 1, which is characterized in that obtain in the Devices to test with institute
The value for stating the corresponding register of data-interface, the value for adjusting the register make the maximum valid window of the data-interface, packet
It includes:
The register is called by serial ports corresponding with the data-interface, reads the value of the register, the data connect
The signal of mouth output includes data-signal and clock signal；
Value by adjusting the register adjusts the clock signal delay of the corresponding data-interface, to obtain the data
The maximum valid window of interface.
3. the adjustment method of hardware device according to claim 1, which is characterized in that the data-interface includes: gigabit
Ethernet interface, 100 m ethernet interface, utilizing camera interface, memory interface and WIFI interface.
4. the adjustment method of hardware device according to claim 1, which is characterized in that device under test data-interface carries out
Test, comprising:
The Devices to test is powered on and initialized；
Control that the Devices to test is in running order to test the data-interface.
5. a kind of debugging apparatus of hardware device characterized by comprising
Communication unit is connect with Devices to test, for being communicated with the Devices to test；
Test cell connects the communication unit, is tested for device under test data-interface；
Debugging unit connects the communication unit and the test cell, for obtain in the Devices to test with the data
The value of the corresponding register of interface, the value for adjusting the register make the maximum valid window of the data-interface.
6. the debugging apparatus of hardware device according to claim 5, which is characterized in that the debugging unit includes:
Module is obtained, for calling the register by serial ports corresponding with the data-interface, reads the register
The signal of value, the data-interface output includes data-signal and clock signal；
Adjustment module adjusts the clock signal delay of the corresponding data-interface for the value by adjusting the register,
To obtain the maximum valid window of the data-interface.
7. the debugging apparatus of hardware device according to claim 5, which is characterized in that the data-interface includes: gigabit
Ethernet interface, 100 m ethernet interface, utilizing camera interface, memory interface and WIFI interface.
8. the debugging apparatus of hardware device according to claim 5, which is characterized in that the test cell is used for described
Devices to test is powered on and initialized, and controls that the Devices to test is in running order to test the data-interface.
9. a kind of computer equipment, the computer equipment, including memory, processor and storage are on a memory and can be
The computer program run on processor, the processor realize any one of Claims 1-4 when executing the computer program
The step of the method.
10. a kind of computer readable storage medium, is stored thereon with computer program, it is characterised in that: the computer program
The step of any one of Claims 1-4 the method is realized when being executed by processor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910157173.7A CN109828879A (en) | 2019-03-01 | 2019-03-01 | Adjustment method, device, computer equipment and the storage medium of hardware device |
| PCT/CN2019/116840 WO2020177369A1 (en) | 2019-03-01 | 2019-11-08 | Hardware device debugging method and apparatus, computer device, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910157173.7A CN109828879A (en) | 2019-03-01 | 2019-03-01 | Adjustment method, device, computer equipment and the storage medium of hardware device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109828879A true CN109828879A (en) | 2019-05-31 |
Family
ID=66864959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910157173.7A Pending CN109828879A (en) | 2019-03-01 | 2019-03-01 | Adjustment method, device, computer equipment and the storage medium of hardware device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109828879A (en) |
| WO (1) | WO2020177369A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020177369A1 (en) * | 2019-03-01 | 2020-09-10 | 晶晨半导体(上海)股份有限公司 | Hardware device debugging method and apparatus, computer device, and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010014922A1 (en) * | 2000-02-14 | 2001-08-16 | Mitsubishi Denki Kabushiki Kaisha | Interface circuit device for performing data sampling at optimum strobe timing |
| CN104407956A (en) * | 2014-12-03 | 2015-03-11 | 天津大学 | IIC bus experimental facility debugged by serial port |
| CN104461796A (en) * | 2013-09-17 | 2015-03-25 | 上海华虹集成电路有限责任公司 | JTAG (joint test action group) debugging module and method for embedded 8051CPU (central processing unit) |
| CN109284238A (en) * | 2018-09-04 | 2019-01-29 | 晶晨半导体(上海)股份有限公司 | Enhance the method and system of eMMC interface stability |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7512854B2 (en) * | 2005-02-24 | 2009-03-31 | International Business Machines Corporation | Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path |
| CN102968376B (en) * | 2012-12-10 | 2015-01-21 | 北京神舟航天软件技术有限公司 | System window phase sliding test method based on overall execution path process |
| CN106445751A (en) * | 2016-08-30 | 2017-02-22 | 大唐微电子技术有限公司 | Debugging board, debugging system and debugging method |
| CN109828879A (en) * | 2019-03-01 | 2019-05-31 | 晶晨半导体(上海)股份有限公司 | Adjustment method, device, computer equipment and the storage medium of hardware device |
-
2019
- 2019-03-01 CN CN201910157173.7A patent/CN109828879A/en active Pending
- 2019-11-08 WO PCT/CN2019/116840 patent/WO2020177369A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010014922A1 (en) * | 2000-02-14 | 2001-08-16 | Mitsubishi Denki Kabushiki Kaisha | Interface circuit device for performing data sampling at optimum strobe timing |
| CN104461796A (en) * | 2013-09-17 | 2015-03-25 | 上海华虹集成电路有限责任公司 | JTAG (joint test action group) debugging module and method for embedded 8051CPU (central processing unit) |
| CN104407956A (en) * | 2014-12-03 | 2015-03-11 | 天津大学 | IIC bus experimental facility debugged by serial port |
| CN109284238A (en) * | 2018-09-04 | 2019-01-29 | 晶晨半导体(上海)股份有限公司 | Enhance the method and system of eMMC interface stability |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020177369A1 (en) * | 2019-03-01 | 2020-09-10 | 晶晨半导体(上海)股份有限公司 | Hardware device debugging method and apparatus, computer device, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020177369A1 (en) | 2020-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207780960U (en) | A kind of wireless data acquisition system | |
| CN102438010B (en) | For the method and apparatus of streaming data profiling | |
| CN206541145U (en) | A kind of multi channel signals synchronous | |
| CN102692616A (en) | Automatic test and collection device and method of smart meter | |
| CN105718339A (en) | FPGA/CPLD remote debugging system and method | |
| CN105335316A (en) | Motor assembling line serial port server based on cloud computation | |
| CN109828879A (en) | Adjustment method, device, computer equipment and the storage medium of hardware device | |
| CN103592480B (en) | A kind of microwave power probe temperature compensation system based on USB interface | |
| CN104009878A (en) | Method and apparatus for measuring network transmission delay | |
| CN103092119A (en) | Bus state monitoring system and method based on field programmable gate array (FPGA) | |
| CN103559111B (en) | IO channel adaptation method and system between fpga chip | |
| CN206133249U (en) | Coil control system a little based on DSP and FPGA | |
| CN104808551A (en) | Intelligent monitoring system and method for aquaculture | |
| CN102779104B (en) | Fault injection method and device for serial port data | |
| CN201322778Y (en) | Measuring device for load characteristic of power system | |
| CN203534633U (en) | Farmland canopy humiture information automatic acquisition system | |
| CN103401734B (en) | The method and apparatus of the signal quality debugging of high speed data bus | |
| CN107256033B (en) | Unmanned aerial vehicle remote control signal conversion equipment | |
| CN109359010B (en) | Method and system for obtaining internal transmission delay of storage module | |
| CN106383793B (en) | External device access method and system on chip | |
| CN204886928U (en) | Small time interval data acquisition device based on PCIE bus | |
| CN206848989U (en) | A kind of automatic data collection timing encapsulation uploading device | |
| CN105871655A (en) | Baudrate evaluation IP core system applied to serial bus analyzer | |
| CN202111730U (en) | Embedded gateway | |
| CN202102428U (en) | Ethernet interface reader-writer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190531 |
|
| RJ01 | Rejection of invention patent application after publication |