CN109817699A - A kind of transistor and imaging sensor - Google Patents
A kind of transistor and imaging sensor Download PDFInfo
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- CN109817699A CN109817699A CN201811634346.1A CN201811634346A CN109817699A CN 109817699 A CN109817699 A CN 109817699A CN 201811634346 A CN201811634346 A CN 201811634346A CN 109817699 A CN109817699 A CN 109817699A
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Abstract
It includes: active layer that the present invention, which discloses a kind of transistor and imaging sensor, the transistor, including the both sides of the edge extended in a first direction；Grid is set on the active layer, and the projection of the grid on the active layer and the both sides of the edge of the active layer form overlay region, and the overlay region includes: two first side edges, is overlapped with the both sides of the edge of the active layer；And two second side edges, it is separately connected two first side edges；Wherein, the overlay region includes two first areas of the both sides of the edge of the adjacent active layer, in the first area, the second side edge gradually direction extension to the separate overlay region along the direction of the one side edge of the close active layer adjacent with the first area respectively.The transistor can improve dark current of the cmos image sensor in low temperature.
Description
Technical field
The present invention relates to semiconductor field, in particular to a kind of transistor and the imaging sensor with the transistor.
Background technique
Basic unit in imaging sensor is pixel, includes photodiode and MOS transistor, photoelectricity in each pixel
Diode is used for transmission and reads photodiode conversion for converting optical signals to corresponding current signal, MOS transistor
Current signal.Wherein the source electrode of transfering transistor is connected with photodiode, is silicon oxide layer, PN light above photodiode
Electric diode sequentially forms N-doped zone and P-doped zone in the direction far from substrate.PN photodiode is straight due to its surface
It connects and is contacted with silicon/oxidative silicon section, have the shortcomings that dark current is big, therefore, in traditional imaging sensor, in image sensing
Surface clamping structure is introduced in device, to reduce dark current.
In the image sensor, inter-band tunneling caused by forceful electric power field-effect, the electrons diffusion that hot carrier's effect generates
In photodiode after to the only resetting of a shallow trench isolation, the dark current of part photodiode is contributed.Temperature is lower,
The contribution of the dark current of this part is bigger, and when being lower than a certain temperature, this portion of electrical current can dominate the dark current of photodiode.
In cmos image sensor, usually source follower transistor, reset transistor and row selecting transistor
Source region and photodiode source region are arranged as distance and only have a shallow trench isolation, therefore, source follower transistor, resetting crystal
Inter-band tunneling caused by the high electric field effect of pipe and row selecting transistor, the electrons that hot carrier's effect generates are diffused into only
In photodiode after having the resetting of a shallow trench isolation, dark current is generated.
In silicon materials, N-type impurity is more than 2 magnitudes that the segregation coefficient of silicon/silicon dioxide interface is p type impurity.
Please also refer to Fig. 6 and Fig. 7, which respectively show bowing after a kind of top view of transistor of the prior art and removal grid
View.As shown in fig. 6, when the polysilicon gate 20 of strip is used as masking layer (barrier layer) to source follower transistor, resetting
When the active layer 10 of transistor and row selecting transistor carries out source and drain injection, due to N-type impurity and p type impurity segregation coefficient
Difference, N-type impurity can form wedge angle outstanding (B location in such as Fig. 7) at silicon/silicon dioxide interface.Through studying, the sharp corner
Electric field be 4 times of plane electric fields.In turn, the electrons spread that strong electrical field generates increases dark current to photodiode, influences
The performance of imaging sensor.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of transistor and with the figure of the transistor
As sensor, which can improve dark current of the cmos image sensor in low temperature.
A kind of transistor is provided according to an aspect of the present invention, and the transistor includes: active layer, including along first party
To the both sides of the edge of extension；Grid is set on the active layer, and the projection of the grid on the active layer has with described
The both sides of the edge of active layer form overlay region, and the overlay region includes: two first side edges, the both sides of the edge with the active layer
It is overlapped；And two second side edges, it is separately connected two first side edges；Wherein, the overlay region includes adjacent institute
Two first areas for stating the both sides of the edge of active layer, in the first area, the second side edge respectively along it is close with
Gradually extend to the direction far from the overlay region on the direction of the one side edge of the adjacent active layer in the first area.
Optionally, the second side edge in the first area is straight line.
Optionally, the first angle that the edge of the second side edge and the active layer is formed outside the overlay region is
Obtuse angle.
Optionally, first angle is between 105 degree to 165 degree.
Optionally, the second side edge in the first area is arc, and recessed to the direction close to the overlay region.
Optionally, the width of the first area is less than 0.05 micron.
Optionally, the active layer forms channel doping layer after source and drain is injected, in the overlay region and is located at institute
State the source electrode and drain electrode at channel doping layer both ends.
Optionally, the channel doping layer is p-type doping, and the source electrode and the drain electrode are n-type doping.
According to another aspect of the present invention, a kind of imaging sensor is also provided, described image sensor includes: photoelectricity two
Pole pipe groove is set to the side of the photodiode；And above-mentioned transistor, the transistor are set to the groove
In, as the source follower transistor of described image sensor, reset transistor and/or row selecting transistor.
Optionally, described image sensor further include: substrate；Epitaxial layer is set on the substrate；Two pole of photoelectricity
Pipe and the transistor are all set on the epitaxial layer.
Compared with the prior art, transistor provided in an embodiment of the present invention and the imaging sensor using the transistor
In, since the overlay region that the both sides of the edge of projection and active layer of the grid on active layer of transistor are formed includes two first
Region, and in first area, connection two is overlapped the second side edge difference of first side edge with the both sides of the edge of active layer
Gradually to the separate overlay region along the direction of the one side edge of the close active layer adjacent with the first area
Direction extends, and then the interface edge of p-type and N-type impurity can be kept more straight after active layer carries out source and drain injection diffusion,
Reduce or avoids the impurity of two kinds of conduction types because of caused by the difference of the segregation coefficient of p-type and N-type impurity in silicon/dioxy
The wedge angle that SiClx interface is formed, in turn, the channel doping layer of formation is more straight in the interface edge of p-type and N-type impurity, can
To effectively reduce electric field enhancement effect, reduce or avoid the electrons spread of strong electrical field generation to the photoelectricity two of imaging sensor
Pole pipe promotes the performance of imaging sensor so that dark current caused by inter-band tunneling or hot carrier's effect be inhibited to increase.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the top view of the transistor of one embodiment of the present of invention；
Fig. 2 is that the top view after grid is removed in the transistor of one embodiment of the present of invention；
Fig. 3 is the top view of the transistor of another embodiment of the invention；
Fig. 4 is the floor map of the imaging sensor of another embodiment of the invention；
Fig. 5 is the cross section structure schematic diagram of the imaging sensor of another embodiment of the invention；
Fig. 6 is a kind of top view of transistor of the prior art；And
Fig. 7 is that a kind of transistor of the prior art removes the top view after grid.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.It is identical attached in figure
Icon note indicates same or similar structure, thus will omit repetition thereof.
Described feature, structure or characteristic can be incorporated in one or more embodiments in any suitable manner
In.In the following description, many details are provided to provide and fully understand to embodiments of the present invention.However,
One of ordinary skill in the art would recognize that without one or more in specific detail, or using other methods, constituent element, material
Material etc., can also practice technical solution of the present invention.In some cases, be not shown in detail or describe known features, material or
Person operates to avoid the fuzzy present invention.
Purport according to the present invention design, transistor of the invention includes: active layer, including extend in a first direction two
Side edge；Grid is set on the active layer, the two sides projected with the active layer of the grid on the active layer
Edge forms overlay region, and the overlay region includes: two first side edges, is overlapped with the both sides of the edge of the active layer；And
Two second side edges are separately connected two first side edges；Wherein, the overlay region includes the adjacent active layer
Two first areas of both sides of the edge, the second side edge in the first area, along close to the active layer two sides
Gradually extend to the direction far from the overlay region on the direction at edge.
Technology contents of the invention are described further with reference to the accompanying drawings and examples.
Referring to Figure 1, it illustrates the top views of the transistor of one embodiment of the present of invention.As shown in Figure 1, in this hair
In bright embodiment, the transistor includes at least active layer 1 and grid 2.
Specifically, active layer 1 includes the both sides of the edge extended in a first direction.As shown in connection with fig. 1, active layer 1 includes
Edge 11 and 12, edge 11 and 12 are respectively the both sides of the edge up and down of active layer 1.In the embodiment shown in fig. 1, first direction
Refer to the transverse direction (left and right directions) in Fig. 1, i.e. edge 11 and edge 12 is extend transversely longitudinal direction (up and down direction) arrangement two
Item defines the edge of active layer 1.In other words, active layer 1 is whole extends in a first direction.
Grid 2 is set on active layer 1, wherein grid 2 can be polysilicon gate.Specifically, as shown in Figure 1, grid
The both sides of the edge 11 and 12 of active layer 1 are crossed in pole 2 along longitudinal direction, in turn, projection of the grid 2 on active layer 1 and the two of active layer 1
Side edge 11 and 12 forms overlay region 3 (as shown in figure 1 shown in shadow region).
Overlay region 3 includes two first side edges 311,312 and two second side edges 321,322.Wherein, two article
One side edge 311,312 is overlapped with the both sides of the edge 11,12 of active layer.Specifically in conjunction with Fig. 1, since overlay region 3 is by grid
What the both sides of the edge 11 and 12 of projection active layer 1 of the pole 2 on active layer 1 were formed, therefore, the edge of overlay region 3 is by active
What the projection of layer 1 and grid 2 was defined.On this basis, above and below the overlay region two sides 311 He of first side edge
312 be actually to be overlapped with the edge 11 and 12 of active layer 1.As shown in Figure 1, being located at the first side edge 311 and edge of upside
11 on the same line；First side edge 312 and edge 12 positioned at downside is on the same line.Two second side edges 321,
322 are separately connected two first side edges 311,312.As shown in Figure 1, when the plane where 2 place plane of grid and active layer 1
In the case where being parallel to each other, two second side edges 321,322 are actually overlapped with the left and right sides edge of grid 2.
Further, in order to when reducing source and drain injection, make the impurity of two kinds of conduction types exist because of the difference of segregation coefficient
The wedge angle formed at silicon/silicon dioxide interface.In an embodiment of the present invention, overlay region 3 includes the two sides of adjacent active layer 1
Two first areas 301,302 of edge 11,12.And in first area 301 or 302, the edge respectively of second side edge 321,322
Gradually to far from overlay region 3 on the direction of the one side edge 11 or 12 of the close active layer 1 adjacent with first area 301 or 302
Direction extend.Specifically, in the embodiment shown in fig. 1, first area 301 is located at the top of overlay region 3, with first
Side edge 311 is adjacent, i.e., the top edge of first area 301 is overlapped with first side edge 311；Similarly, first area 302 is located at
The lower part of overlay region 3, adjacent with first side edge 312, i.e., the lower edge of first area 302 is overlapped with first side edge 312.
By taking the second side edge 321,322 being located in first area 301 as an example, due to being with what first area 301 abutted
Edge 11, therefore, second side edge 321 and 322 are gradually prolonged to the direction far from overlay region 3 along on the direction of proximal edge 11
It stretches.In turn, in the embodiment shown in fig. 1, the second side edge 321 positioned at 3 left side of overlay region is along by proximal edge 11
Gradually extend to the left on direction (upwardly direction in Fig. 1)；And the second side edge 322 for being located at 3 right side of overlay region is that edge is leaned on
Gradually extend to the right on the direction (upwardly direction in Fig. 1) of proximal edge 11.(left and right directions is for entire 301 length of first area
Length) it is gradually increased along on the direction (upwardly direction in Fig. 1) of proximal edge 11.The width of first area 301 is preferably small
In 0.05 micron.
Further, in preferred embodiment shown in Fig. 1, in order to keep the processing procedure of grid 1 more convenient, therefore, first
Second side edge 321 and 322 in region 301 and 302 is straight line.Further, in order to more effectively reduce above-mentioned two
The wedge angle that the impurity of kind conduction type is formed at silicon/silicon dioxide interface, the side of second side edge 321 and 322 and active layer
The first included angle A that edge 11 or 12 is formed outside overlay region 3 is obtuse angle.As shown in connection with fig. 1, second side is referred to the first included angle A in Fig. 1
Edge 321 and its edge 11 with intersection are for the angle in overlay region 3 outer (i.e. left side in Fig. 1).It should be noted that first
Included angle A may also mean that second side edge 322 and its edge 11 with intersection overlay region 3 outer (i.e. right side in Fig. 1) angle,
The angle and second side edge of second side edge 321 and the edge 12 intersected with it outside overlay region 3 (i.e. on the left of in Fig. 1)
322 and the edge 12 that intersects with it overlay region 3 outer (i.e. right side in Fig. 1) angle.Preferably, the first included angle A is arrived at 105 degree
Between 165 degree.
Fig. 2 is referred to, it illustrates the top views after removal grid in the transistor of one embodiment of the present of invention.Such as figure
Shown in 2, in an embodiment of the present invention, active layer 1 is formed under the blocking of grid 2, after source and drain is injected, in overlay region 3
Channel doping layer 35 and positioned at channel doping layer both ends source electrode 34 and drain electrode 36.In an embodiment of the present invention, above-mentioned knot
After structure is mainly for the source and drain injection of n-type doping, in silicon/silicon dioxide interface, p-type trap is convex to the wedge angle of N-type source and drain, therefore,
In this embodiment, channel doping layer 35 is p-type doping, and source electrode 34 and drain electrode 36 are n-type doping.As shown in Fig. 2, due to grid
The overlay region 3 formed between pole 2 and active layer 1 has above-mentioned structure, therefore, forms the channel doping layer 35 after source and drain is injected
It is more straight in the interface edge 351 and 352 of p-type and N-type impurity, reduce or avoids because of caused by the difference of segregation coefficient
The wedge angle that the impurity of two kinds of conduction types is formed at silicon/silicon dioxide interface.
Fig. 3 is another embodiment of transistor of the invention, refers to Fig. 3, and it illustrates of the invention another
The top view of the transistor of a embodiment.Unlike above-mentioned embodiment shown in FIG. 1, in this embodiment, first area
Second side edge 321 and 322 in 301 and 302 is arc, and recessed to the direction close to overlay region 3.Wherein, first area
The arc of second side edge 321 and 322 in 301 and 302 preferably, can be according to the miscellaneous of two kinds of conduction types in the prior art
The arc of the wedge angle that matter is formed at silicon/silicon dioxide interface is arranged, such as symmetrical etc. with the arc of the wedge angle, in turn, the knot
The channel doping layer that structure is formed after source and drain can be made to inject is more straight in the interface edge of p-type and N-type impurity.
Further, the present invention also provides a kind of with above-mentioned Fig. 1 to the imaging sensor of transistor shown in Fig. 3.Please
Together referring to fig. 4 and Fig. 5, which respectively show the floor map of the imaging sensor of another embodiment of the invention and
Cross section structure schematic diagram.Specifically, described image sensor includes: photodiode 5, groove 6 and above-mentioned Fig. 1 to Fig. 3
Shown in transistor.
Specifically, groove 6 is set to the side of photodiode 5.As shown in figure 4, groove 6 is set to photodiode
5 right side.Further, described image sensor further includes source follower transistor 71, reset transistor 72 and row choosing
Select transistor 73.Source follower transistor 71, reset transistor 72 and row selecting transistor 73 are set in groove 6.It needs
It is noted that it is brilliant to only schematically show source follower transistor 71, reset transistor 72 and row selection in Fig. 3
The position of body pipe 73, is not limited thereto, source follower transistor 71, reset transistor 72 and row selecting transistor 73
Position can be replaced or adjust according to the actual needs.Further, in the embodiment of invention, source follower crystal
At least one in pipe 71, reset transistor 72 and row selecting transistor 73 is above-mentioned Fig. 1 to transistor shown in Fig. 3, with this
Improve dark current of the imaging sensor in low temperature.
More specifically, in the embodiment shown in fig. 5, described image sensor further includes substrate 81, epitaxial layer 82, photoelectricity
Diode and transistor.Wherein, photodiode and transistor are all set on epitaxial layer 82, and photodiode and transistor
It is connected.Transistor in Fig. 5 can be in source follower transistor 71, reset transistor 72 and row selecting transistor 73
Either one or two of.
More specifically, in the embodiment shown in fig. 5, substrate 81 can be p-type heavily doped silicon substrate.Epitaxial layer 82 is set
It is placed in and is set on substrate 81, epitaxial layer 82 can be p-type lightly doped epitaxial layer.Photodiode includes n-type doping layer 83, P
The clamped implanted layer 84 of type heavy doping, p-type doping separation layer 851, p-type adulterate separation layer 852, p-type heavy doping trench isolation layer 86.
Wherein, n-type doping layer 83 is formed on epitaxial layer 82, and the clamped implanted layer 84 of p-type heavy doping is formed in n-type doping layer 83.P-type
Doping separation layer 851 is formed in the side (left side in Fig. 5) of epitaxial layer 82, and longitudinal (being upward in Fig. 5) by epitaxial layer 82
It extends past after n-type doping layer 83 until the clamped implanted layer 84 of p-type heavy doping；P-type adulterates separation layer 852 similarly by epitaxial layer
82 longitudinal (they being upward in Fig. 5) extend to n-type doping layer 83, are located at the other side (right side in Fig. 5) of n-type doping layer 83, and
Its top is connected to p-type heavy doping trench isolation layer 86.P-type heavy doping trench isolation layer 86 is used in n-type doping layer 83, p-type
It is formed and is isolated between the clamped implanted layer 84 of heavy doping and groove 6.
Further, as shown in figure 5, transistor includes p-well 87, p-well 87 is set on epitaxial layer 82, is located at p-type and is adulterated
The other side (adulterating the right side of separation layer 852 in Fig. 5 for p-type) of the separate n-type doping layer 83 of separation layer 852, source electrode or drain electrode
It is formed in the top of p-well 87 (in Fig. 5 by taking drain electrode 36 as an example).P-well 87 and active layer 1 be respectively arranged on the left side and the right side groove 6 with
And p-type heavy doping trench isolation layer 86.Further, transistor is including further including dielectric layer 88 and being formed on dielectric layer 88
Contact hole 89.Wherein, dielectric layer 88 covers photodiode and transistor, contact hole 89 are corresponding with active layer 1.Dielectric layer
88 can be silica dioxide medium layer, and contact hole 89 is metal contact hole.
In conclusion in the imaging sensor of transistor provided in an embodiment of the present invention and the use transistor, due to
The overlay region that the both sides of the edge of projection and active layer of the grid of transistor on active layer are formed includes two first areas, and
In first area, the second side edge that connection two is overlapped first side edge with the both sides of the edge of active layer respectively along it is close with
Gradually extend to the direction far from the overlay region on the direction of the one side edge of the adjacent active layer in the first area,
And then can when active layer carry out source and drain injection diffusion after, keep the interface edge of p-type and N-type impurity more straight, reduction or
Avoid the impurity of two kinds of conduction types because of caused by the difference of the segregation coefficient of p-type and N-type impurity in silicon/silicon dioxide interface
Locate the wedge angle formed, in turn, the channel doping layer of formation is more straight in the interface edge of p-type and N-type impurity, can be effectively
Reduce electric field enhancement effect, the photodiode of the electrons spread for reducing or avoiding strong electrical field to generate to imaging sensor, from
And dark current caused by inter-band tunneling or hot carrier's effect is inhibited to increase, promote the performance of imaging sensor.
Although the present invention is disclosed as above with alternative embodiment, it is not intended to limit the invention.Belonging to the present invention
Those skilled in the art, without departing from the spirit and scope of the present invention, when various change and modification can be made.Therefore,
Protection scope of the present invention is subject to the range defined depending on claims.
Claims (10)
1. a kind of transistor, which is characterized in that the transistor includes:
Active layer, including the both sides of the edge extended in a first direction；
Grid is set on the active layer, the two sides projected with the active layer of the grid on the active layer
Edge forms overlay region, and the overlay region includes:
Two first side edges, are overlapped with the both sides of the edge of the active layer；And
Two second side edges are separately connected two first side edges；
Wherein, the overlay region includes two first areas of the both sides of the edge of the adjacent active layer, in the first area
Interior, the described second side edge respectively along the direction of the one side edge of the active layer adjacent with the first area along close by
Gradually extend to the direction far from the overlay region.
2. transistor as described in claim 1, which is characterized in that the second side edge in the first area is straight line.
3. transistor as claimed in claim 2, which is characterized in that the edge of the second side edge and the active layer is in institute
Stating the first angle formed outside overlay region is obtuse angle.
4. transistor as claimed in claim 3, which is characterized in that first angle is between 105 degree to 165 degree.
5. transistor as described in claim 1, which is characterized in that the second side edge in the first area is arc, and
It is recessed to the direction close to the overlay region.
6. the transistor as described in any one of claims 1 to 5, which is characterized in that the width of the first area is less than 0.05
Micron.
7. the transistor as described in any one of claims 1 to 5, which is characterized in that the active layer is after source and drain is injected, in institute
It states and forms channel doping layer and the source electrode and drain electrode positioned at the channel doping layer both ends in overlay region.
8. transistor as claimed in claim 7, which is characterized in that the channel doping layer is p-type doping, the source electrode and described
Drain electrode is n-type doping.
9. a kind of imaging sensor, which is characterized in that described image sensor includes:
Photodiode
Groove is set to the side of the photodiode；And
Such as transistor described in any item of the claim 1 to 8, the transistor is set in the groove, as the figure
As the source follower transistor of sensor, reset transistor and/or row selecting transistor.
10. imaging sensor as claimed in claim 9, which is characterized in that described image sensor further include:
Substrate；
Epitaxial layer is set on the substrate；
The photodiode and the transistor are all set on the epitaxial layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811634346.1A CN109817699B (en) | 2018-12-29 | 2018-12-29 | Transistor and image sensor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811634346.1A CN109817699B (en) | 2018-12-29 | 2018-12-29 | Transistor and image sensor |
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| Publication Number | Publication Date |
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| CN109817699A true CN109817699A (en) | 2019-05-28 |
| CN109817699B CN109817699B (en) | 2022-06-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100187543A1 (en) * | 2008-12-01 | 2010-07-29 | Fuji Electric Systems Co., Ltd. | Method for manufacturing silicon carbide semiconductor device and the silicon carbide semiconductor device |
| CN102124548A (en) * | 2008-08-19 | 2011-07-13 | 飞思卡尔半导体公司 | Transistor with gain variation compensation |
| CN104380472A (en) * | 2012-07-25 | 2015-02-25 | 住友电气工业株式会社 | Silicon carbide semiconductor device |
-
2018
- 2018-12-29 CN CN201811634346.1A patent/CN109817699B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102124548A (en) * | 2008-08-19 | 2011-07-13 | 飞思卡尔半导体公司 | Transistor with gain variation compensation |
| US20100187543A1 (en) * | 2008-12-01 | 2010-07-29 | Fuji Electric Systems Co., Ltd. | Method for manufacturing silicon carbide semiconductor device and the silicon carbide semiconductor device |
| CN104380472A (en) * | 2012-07-25 | 2015-02-25 | 住友电气工业株式会社 | Silicon carbide semiconductor device |
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