CN109802710A

CN109802710A - A kind of method and device realizing code book and generating

Info

Publication number: CN109802710A
Application number: CN201711137730.6A
Authority: CN
Inventors: 卞青
Original assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd; Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2019-05-24
Anticipated expiration: 2037-11-16
Also published as: CN109802710B

Abstract

A kind of realization method for generating codebooks and device, comprising: default discrete Fourier transform (DFT) base infrastructure elements that storage generates offline；The addressable address of DFT base infrastructure elements is determined according to code book related information, and DFT base infrastructure elements are carried out to make operable enabled information；Addressable address is exported according to preset address enable signal；DFT base infrastructure elements are taken out according to the addressable address of output, carry out enabled operation according to DFT base infrastructure elements of the enabled information of output to taking-up, and the data after enabled operation are stored to preset DFT basic sequence storage region；Twiddle factor is decomposed, and according to the data for obtaining each layer main beam and auxiliary wave beam；It is added with the main beam of acquisition and the data of auxiliary wave beam, and the data obtained after being added with are stored as code book.The embodiment of the present invention simplifies DFT base index and complex operation, reduces the complexity of code book generation, reduces memory space expense.

Description

A kind of method and device realizing code book and generating

Technical field

Present document relates to but be not limited to link adaptation techniques, it is espespecially a kind of realize code book generate method and device.

Background technique

Long Term Evolution upgrade version (LTE-A) system has used large-scale antenna array and beam shaping technology To improve system performance.Beam shaping technical requirements based on large-scale antenna array can accurately obtain channel in transmitting terminal Status information (CSI, channel state information), and select optimal wave beam to carry out data transmitting according to CSI. CSI needs to feed back by the user equipment (UE, User Equipment) of receiving end to transmitting terminal.UE is obtained using channel estimation Channel coefficient matrix H and noise coefficient No, according to the optiaml ciriterion of setting select with present channel CSI the most matched, finally By CSI reporting base station.

Before LTE-A issues (release) 14, the calculating and selection of CSI is all that UE assumes that its current transmission mode is In single user multiple-input and multiple-output (SU-MIMO, single user multiple input multiple output) mould Formula；If base station needs to carry out multi-user's multiple-input and multiple-output (MU-MIMO, multiple user according to the feedback of current UE Multiple input multiple output) transmission, then base station needs oneself to judge channel status and the progress of each UE Combination, then recalculate order instruction (RI, rank indicator), pre-coding matrix instruction that MU-MIMO uses (PMI, Precoding matrix index) and channel quality instruction (CQI, channel quality indicator), so often Cause the decline of MU-MIMO performance.In view of the above-mentioned problems, LTE-A release 14 is proposed for large-scale antenna array The enhanced code book of MU-MIMO, mainly uses 2 wave beam linear combining code books, UE according to the code book Combination selection go out RI and PMI further calculates corresponding CQI, and feeds back to base station.The enabling of the code book can effectively promote MU-MIMO biography Defeated performance, but code book enormous amount in enhanced linear combining codebook set only just have under a kind of configuration of 32 antenna ports 458752 one layer of code books and 29360128 two layers of code books.So complicated code book causes the generation of the precoding of the side UE It is difficult.

Aiming at the problem that precoding generates, the relevant technologies give some solutions；Wherein, first way be according to The requirement real-time online of agreement generates the pre-coding matrix needed, and this method is easily achieved but the generation of pre-coding matrix every time It requires to carry out multiple discrete Fourier transform (DFT, Discrete Fourier Transform) base generation (index fortune Calculate), complex matrix it is multiply-add it is equal calculate, then to comprehensively consider code book quantity its computation complexity very high；Another way is to use The mode of whole offline storage code books, this method do not need to carry out additional calculating, it is only necessary to corresponding code is read from memory This, but the memory space needed in this way will be very huge (being greater than 1 gigabit (GBytes)).

Summary of the invention

It is the general introduction to the theme being described in detail herein below.This general introduction is not the protection model in order to limit claim It encloses.

The embodiment of the present invention provides a kind of method and device realizing code book and generating, and can simplify DFT base index and plural number Operation reduces the complexity that code book generates, and reduces memory space expense.

The embodiment of the invention provides a kind of methods realizing code book and generating, comprising:

Store the default discrete Fourier transform DFT base infrastructure elements generated offline；

The addressable address of DFT base infrastructure elements is determined according to code book related information, and DFT base infrastructure elements are enabled The enabled information of operation；

Addressable address is exported according to preset address enable signal；Wherein, the addressable address of output is for taking out for giving birth to At the DFT base infrastructure elements of code book；

DFT base infrastructure elements are taken out according to the addressable address of output, according to the enabled information of output to the DFT base base of taking-up Plinth element carries out enabled operation, and the data after enabled operation are stored to preset DFT basic sequence storage region；

Twiddle factor is decomposed, and phase rotation is carried out to the data after enabled operation according to the twiddle factor obtained is decomposed, Obtain the data of each layer main beam and auxiliary wave beam；

It is added with the main beam of acquisition and the data of auxiliary wave beam, and the data obtained after being added with are stored as code book；

Wherein, the addressable address of the DFT base infrastructure elements includes: the addressable address of the DFT base infrastructure elements of main beam With the addressable address of the DFT base infrastructure elements of auxiliary wave beam；

The enabled operation includes: real empty exchange and/or negates.

Optionally, the default DFT base infrastructure elements include:

The DFT base of 1680 first quartiles；With the DFT of first quartile multiplied byValue；

Wherein, each DFT base infrastructure elements are stored by a corresponding address；Each address includes to be used for storage element real part 1 byte and storage element imaginary part 1 byte.

Optionally, the default DFT base infrastructure elements are stored according to following address:

The DFT base of first quartile is stored in the address determined according to following sequences:

The DFT of first quartile multiplied byValue be stored according to following sequences determine address:

Optionally, the code book related information includes following part or all of information:

Horizontal direction oversample factor O1, vertical direction oversample factor O2, the horizontal port number N1 of antenna, antennas orthogonal end Mouth number N2,1 first PMI1 of first order code book index, 2 first PMI2 of first order code book index, first order code book index 3 First PMI3, power factor configuration information p.

Optionally, described to include: according to preset address enable signal output addressable address

One or more accumulators are controlled according to the preset address enable signal, to export the addressing ground Location；

Wherein, the Sequential output that the addressable address intersects one by one according to main beam and auxiliary wave beam.

Optionally, the decomposition twiddle factor includes:

It is decomposed according to the second level code book index second PMI for inputting each layer and obtains the twiddle factor；

Wherein, the twiddle factor includes: the phase rotation coefficient for the upper and bottom section that main beam includes, He Fubo The phase rotation coefficient for the upper and bottom section that beam includes.

On the other hand, a kind of device realizing code book and generating of the embodiment of the present invention, comprising: first unit, second unit, the Unit three, Unit the 4th, Unit the 5th and Unit the 6th；Wherein,

First unit is used for: the default DFT base infrastructure elements that storage generates offline；

Second unit is used for: the addressable address of DFT base infrastructure elements is determined according to code book related information, and to DFT base base Plinth element carries out making operable enabled information；

Third unit is used for: exporting addressable address according to preset address enable signal；Wherein, the addressable address of output is used In taking out the DFT base infrastructure elements for generating code book；

Unit the 4th is used for: DFT base infrastructure elements is taken out according to the addressable address of output, according to the enabled information pair of output The DFT base infrastructure elements of taking-up carry out enabled operation, and the data storage after enabled operation is stored to preset DFT basic sequence Region；

Unit the 5th is used for: decomposing twiddle factor, and the twiddle factor obtained according to decomposition is to the data after enabled operation Phase rotation is carried out, the data of each layer main beam and auxiliary wave beam are obtained；

Unit the 6th is used for: be added with the main beam of acquisition and the data of auxiliary wave beam, and the data obtained after being added with as Code book storage；

The enabled operation includes: real empty exchange and/or negates.

Optionally, the default DFT base infrastructure elements include:

Optionally, the third unit is specifically used for:

Optionally, Unit the 5th includes: for decomposing twiddle factor

In another aspect, the embodiment of the present invention also provides a kind of computer storage medium, deposited in the computer storage medium Computer executable instructions are contained, the computer executable instructions are for executing above-mentioned method.

Also on the one hand, the embodiment of the present invention also provides a kind of terminal, comprising: memory and processor；Wherein,

Processor is configured as executing the program instruction in memory；

Program instruction reads in processor and executes following operation:

Store the default DFT base infrastructure elements generated offline；

The enabled operation includes: real empty exchange and/or negates.

Compared with the relevant technologies, technical scheme includes: the default discrete Fourier transform that storage generates offline (DFT) base infrastructure elements；The addressable address of DFT base infrastructure elements is determined according to code book related information, and to DFT base infrastructure elements It carries out making operable enabled information；Addressable address is exported according to preset address enable signal；According to the addressable address of output DFT base infrastructure elements are taken out, carry out enabled operation according to DFT base infrastructure elements of the enabled information of output to taking-up, and will make Data after capable of operating are stored to preset DFT basic sequence storage region；Twiddle factor is decomposed, and according to each layer main beam of acquisition With the data of auxiliary wave beam；It is added with the main beam of acquisition and the data of auxiliary wave beam, and the data obtained after being added with are deposited as code book Storage.The embodiment of the present invention simplifies DFT base index and complex operation, reduces the complexity of code book generation, and it is empty to reduce storage Between expense.

Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right Specifically noted structure is achieved and obtained in claim and attached drawing.

Detailed description of the invention

Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.

Fig. 1 is the flow chart for the method that the embodiment of the present invention realizes that code book generates；

Fig. 2 is the structural block diagram for the device that the embodiment of the present invention realizes that code book generates；

Fig. 3 is the composed structure schematic diagram that the present invention applies the optional circuit of example；

Fig. 4 is the time diagram that the present invention applies sample address enable signal；

Fig. 5 is the structural block diagram that the present invention applies another optional circuit of example；

Fig. 6 is composition block diagram of the present invention using the another optional circuit of example.

Specific embodiment

To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application Feature can mutual any combination.

Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable Sequence executes shown or described step.

Fig. 1 is the flow chart for the method that the embodiment of the present invention realizes that code book generates, as shown in Figure 1, comprising:

The default discrete Fourier transform DFT base infrastructure elements that step 100, storage generate offline；

Optionally, the default DFT base infrastructure elements of the embodiment of the present invention include:

Optionally, the default DFT base infrastructure elements of the embodiment of the present invention are stored according to following address:

Step 101, the addressable address that DFT base infrastructure elements are determined according to code book related information, and to DFT base infrastructure elements It carries out making operable enabled information；

The enabled operation includes: real empty exchange and/or negates.

Optionally, code book of embodiment of the present invention related information includes following part or all of information:

Step 102 exports addressable address according to preset address enable signal；Wherein, the addressable address of output is for taking Out for generating the DFT base infrastructure elements of code book；

Optionally, the embodiment of the present invention includes: according to preset address enable signal output addressable address

Addressable address of the embodiment of the present invention includes: according to main wave according to the Sequential output that main beam and auxiliary wave beam intersect one by one Second first element address of beam, first element address of auxiliary wave beam, second element address of main beam, auxiliary wave beam element The Sequential output addressable address of location ..., auxiliary wave beam last element address.

Step 103 takes out DFT base infrastructure elements according to the addressable address of output, according to the enabled information of output to taking-up DFT base infrastructure elements carry out enabled operation, and by the data storage after enabled operation to preset DFT basic sequence memory block Domain；

Step 104 decomposes twiddle factor, and carries out phase to the data after enabled operation according to the twiddle factor obtained is decomposed Position rotation, obtains the data of each layer main beam and auxiliary wave beam；

Optionally, decomposition of embodiment of the present invention twiddle factor includes:

It should be noted that the decomposition method of twiddle factor of the embodiment of the present invention includes: according to LTE protocol second PMI Design principle obtains；Take 2 bit of highest of second PMI respectively, intermediate 2 bits, minimum 2 bit as three rotations because Son.

The data of step 105, the main beam for being added with acquisition and auxiliary wave beam, and the data obtained after being added with are deposited as code book Storage.

The embodiment of the present invention simplifies DFT base index and complex operation, only with a small amount of addition and multiplying Corresponding code book is generated, the complexity of code book generation is reduced, reduces memory space expense.

Fig. 2 is the structural block diagram for the device that the embodiment of the present invention realizes that code book generates, as shown in Figure 2, comprising: first is single Member, second unit, third unit, Unit the 4th, Unit the 5th and Unit the 6th；Wherein,

Optionally, third unit of the embodiment of the present invention is specifically used for:

Optionally, Unit the 5th of the embodiment of the present invention includes: for decomposing twiddle factor

The enabled operation includes: real empty exchange and/or negates.

In another aspect, the embodiment of the present invention also provides a kind of computer storage medium, deposited in the computer storage medium Contain computer executable instructions, the side that the computer executable instructions require above-mentioned realization code book to generate for perform claim Method.

Processor is configured as executing the program instruction in memory；

Program instruction reads in processor and executes following operation:

Store the default DFT base infrastructure elements generated offline；

The enabled operation includes: real empty exchange and/or negates.

Present invention method is carried out to understand detailed description below by way of using example, is only used for using example old The present invention is stated, is not intended to limit the scope of protection of the present invention.Using example one

This application example precoding coefficients include: the horizontal port number N1=4 of two-dimensional antenna configuration antenna, antennas orthogonal port 32 of the number code book over-sampling parameter level direction oversample factor O1=4 of N2=4, vertical direction oversample factor O2=4 Transmission antenna port, 1 (first PMI1i of first layer first order code book index₁₁=10, first layer second level code book index 2 (first PMI2)i₁₂=12, first layer third level code book index 3first PMI 3i₁₃=1, p=1,2 layers of first layer second Grade code book index second PMI i_2,1=27,2 layers of second layer second level code book index second PMI i_2,2=37.

This application example stores the default DFT base infrastructure elements generated offline first, comprising: 1680 first quartiles DFT base；With the DFT base infrastructure elements of first quartile multiplied byValue；Each DFT base infrastructure elements is by a corresponding ground Location storage；Each address includes 1 of 1 byte (byte) and storage infrastructure elements imaginary part for storing infrastructure elements real part Byte.

This application example is used to store the addressable address range of DFT base infrastructure elements required for generation code book [0~3359], addressable address can be designed by those skilled in the art and be determined；Addressable address can determine in the following manner, It include: to obtain N1 and N2 least common multiple according to all possible values [1,2,3,4,5,6,7,8,10,12,14,16] of N1/N2 It is 1680, in all possible values [4] for obtaining O1/O2, obtains 6720 multiplied by least common multiple, that is to say, that need 6720 Plural number could save all possible values of the DFT base needed under all N1/N2/O1/O2 combinations, according to the quadrant symmetrical of plural number Characteristic takes 1/4 infrastructure elements of first quartile to save here, i.e. preservation 6720*1/4=1680, while in order to avoid power Because of the complex multiplication being likely to occur when subindex p=2, here in advance by first quartile DFT base infrastructure elements multiplied by the function of p=2 The rate factorAnd store, that is, increase by 1680 storages；

This application example can realize that Fig. 3 is by following optional circuit to second unit in embodiment and third unit The composed structure schematic diagram of the optional circuit of present invention application example, as shown in Figure 3, comprising:

First module 301: for N1=4, N2=4 and first PMI3i according to input₁₃=1 from corresponding N1/N2 Step-length memory obtains d1/d2 value and output step value S cumulative every time in d1/d2 memory_N1、S_N2；Wherein, output step Long value S_N1、S_N2Totalizing step is obtained after being multiplied with first PMI 1 or first PMI 2；N1 or N2 step-length of the embodiment of the present invention N1 or N2 input value and corresponding memory output valve are as shown in table 1 in memory, and table of the embodiment of the present invention 1 is based on following principle Design: the least common multiple of N1 and N2 are obtained according to all possible values [1,2,3,4,5,6,7,8,10,12,14,16] of N1/N2 Number is 1680, that is, corresponds to the different configurations of N1/N2, first PMI1 i₁₁Every increase N1 is equivalent to read address I₁₁Increase 1680, first PMI2 i₁₂Every increase N2 is equivalent to read address i₁₂Increase by 1680, so difference N1 value is corresponding defeated Step-length is exactly 1680/N1 out, and the corresponding output step-length of different N2 values is exactly 1680/N2；

Table 1

The content of this application example d1/d2 memory storage can be content as defined in LTE protocol, as shown in table 2, with N1、N2、i₁₃It is respectively as follows: as input value and corresponding memory output valve d1, d2

Table 2

Second module 302 is used for: after obtaining output step-length by the first module 301, the output step-length and d1/d2 that will obtain It is handled by multiplier, obtains main beam totalizing step and auxiliary wave beam compensates step-length:

S_{N1_add}=i₁₁*S_N1, S_{N2_add}=i₁₂*S_N2；Off_N1=d1*4*S_N1, Off_N2=d2*4*S_N2。

Wherein, main beam totalizing step=1 i of output step-length * first PMI₁₁Or main beam totalizing step=output step Long * first PMI2 i₁₂, what it is such as d10 output step-length characterization is that first PMI 1 or first PMI 2 increases by 1 corresponding selection Addressable address need increased value, and main beam totalizing step is exactly at determining first PMI 1 or first PMI 2 The two is multiplied, the storage address difference in Representation Level or vertical direction between main beam each element.Similarly auxiliary wave beam compensation step Length=output step-length * 4*d1 (d2)；Wherein, 4 indicate that horizontal over-sampling multiple, d1/d2 indicate auxiliary wave beam and main wave The alternate position spike of beam in horizontal/vertical directions, auxiliary wave beam compensation step-length characterize auxiliary wave beam and main beam in horizontal/vertical directions Storage address difference between same sequence number element.

Third module 303 is used for: output address enable signal；Wherein, address enable of embodiment of the present invention signal can wrap Include following three kinds: first enable signals, the second enable signal and major-minor enable signal；Wherein, the first enable signal controls S_{N1_add} With Off_N1It is cumulative, it is enabled every time to accumulate once；Second enable signal controls S_{N2_add}With Off_N2It is cumulative, it is enabled cumulative every time Once；Every N2 times enabled second enable signal, enables first enable signal；The embodiment of the present invention can be by major-minor Enable signal controls the output of addressable address, and addressable address includes main beam addressable address or auxiliary wave beam addressable address；For example, Major-minor to enable to indicate output main beam addressable address for 0, auxiliary wave beam offset is 0 at this time, major-minor to enable to indicate for 1 to export auxiliary wave Beam addressable address, auxiliary wave beam offset is Off at this time_N1+Off_N2。

Fig. 4 is the time diagram that the present invention applies sample address enable signal, as shown in figure 4, can pass through counter Separated in time output address enable signal as requested.First element of main beam is being generated by major-minor enable signal Behind address, the address of auxiliary first element of wave beam is generated, the second enable signal is then enabled, carries out a S_{N2_add}With Off_N2's It is cumulative；Generate second element of major-minor wave beam again, and so on until generating major-minor the 4th element of wave beam, then enable second Enable signal and the first enable signal, carry out a S_{N2_add}With Off_N2Cumulative and S_{N1_add}With Off_N1It is cumulative, generate master Auxiliary the 5th element of wave beam (main beam and auxiliary wave beam), it is complete according to the method described above until generating major-minor the 16th element of wave beam It is generated at the infrastructure elements of DFT base.

4th module 304 is used for: by the addressable address obtained according to address enable signal addressing by remainder module, being obtained Actual sequence addressable address；Remainder of the embodiment of the present invention is to guarantee model that the value of addressable address can be indicated in DFT base In enclosing [0~6719], remainder operation can be realized based on existing principle.

5th module 305 is used for: the actual sequence addressable address input comparator that will be obtained, to generate to DFT base basis Element carries out making operable enabled information；This application example by the actual sequence addressable address of output pass through respectively comparator with 1680/3360/5040 is compared, and obtains each enable signal by combinational logic using the output of comparator, i.e., to DFT base base Plinth element carries out making operable enabled information；Specific corresponding relationship can be as shown in table 3, and the embodiment of the present invention is turned using quadrant The principle changed obtains enable signal.If actual sequence address < 1680, indicate the corresponding value in current address in first quartile Interior, the storage of DFT memory is also the value of first quartile so without swapping and inversion operation.If in 1680 and 3360 Between, the corresponding value of current addressable address is indicated in the second quadrant, and first can just be transformed to by needing to subtract pi/2 in phase The corresponding value of quadrant, this is equivalent to negates the real empty exchange of the value of first quartile to real part again, so needing enabled real empty exchange Negated with real part it is enabled, similarly between 3360 and 5040 and be greater than 5040, be equivalent to third and fourth quadrant, need first Quadrant respective value carry out real part negate/imaginary part negates and actual situation exchange/imaginary part negates operation converted.

Table 3

6th module 306 is used for: the DFT base basis exported by quadrant address correction and power factor address correction The reading address of element (for taking out the addressable address of the DFT base infrastructure elements for generating code book).Quadrant address correction value It indicates to obtain by quadrant, actual sequence address is added to obtain first quartile address with address correction value, quadrant is indicated and repaired Corresponding relationship can be as shown in table 4 between positive value:

Quadrant instruction	Address correction value
		0	0
1	-1680
		2	-3360
3	-5040

Table 4

First quartile address obtains final output address after being added with power factor correction value, power factor correction value only exists Major-minor is 1680 when enabling as 1 (auxiliary wave beam output) and P=2, remaining condition is 0.

This application example is from default DFT base infrastructure elements of storage, according to the addressing of the DFT base infrastructure elements of output Take out DFT base infrastructure elements in address；Enabled behaviour is carried out to input data according to the first enabled information of output and the DFT base of taking-up Make, and the input data after enabled operation is stored according to addressable address；Wherein, enabled operation includes: real empty exchange and/or takes Instead.Unit the 4th of the embodiment of the present invention realizes that Fig. 5 is the present invention using another optional circuit of example by following optional circuit Structural block diagram, as shown in Figure 5, comprising:

7th module 501 is used for: the DFT base infrastructure elements of input being divided into real part imaginary part and are stored respectively；

8th module 502 is used for: the data exchange operation of DFT base infrastructure elements is carried out according to enabled information, such as fruit void Exchange enables to be 1, and two data select it to select data 1 at this time, and completion imaginary part is exchanged with real part；As the exchange of fruit void is enabled It is 0, two data select it to select data 0 at this time, and real part is not exchanged with imaginary part.Inversion operation is carried out according to enabled information, such as Fruit, which negates, to be enabled to be 1, and the data for negating device to input at this time carry out taking negative processing.

9th module 503 is used for: according to the corresponding addressable address of the enabled output of read-write；When writing enabled, output addressing ground Location is by the output of counter, and counter is according to major-minor enable signal failing edge flip-flop number, i.e. one main beam number of every processing According to after an auxiliary beam data, write address adds 1；

If major-minor beam memories work stores data into master if major-minor enable signal is 0 in WriteMode at this time Beam memories corresponding address；If major-minor enable to be 1, at this time according to the value of power factor p, auxiliary beam memories are exported Data successively carry out shifting/reset or be moved to right if p=1 without processing if p=2/3 is not necessarily to extra process 1 processing (being equivalent to except 2) is zeroed out processing if p=0, and by treated, auxiliary beam data storage is deposited to auxiliary wave beam Reservoir corresponding address.

This application example, the every processing for completing a data of counter module adds 1, if counter output is less than N1*N2, Counter output is that major-minor wave beam (main beam and auxiliary wave beam) memory reads address；If counter output is more than or equal to N1*N2 needs to subtract counter output N1*N2 and obtains major-minor beam memories reading address；Here, using N1*N2 as pair Than parameter, mainly according to the requirement of LTE protocol code book, every layer of code book is divided into two polarization directions, contains in each polarization direction There is N1*N2 codebook element, it is 2*N1*N2 that the number that address counter is read is read when generating every layer of code book, that is, Say that needs read primary/secondary beam memories twice, to generate the code book in polarization direction 0 and polarization direction 1 respectively, so reading Address counter technology is directly output as the reading address of major-minor beam memories when being less than N1*N2, when being more than or equal to N1*N2 The major-minor beam memories of second of reading are equivalent to, since major-minor beam memories address range is [0, N1N2-1], so this When need to subtract N1*N2 output address again.

Unit the 5th of the embodiment of the present invention is used for: being decomposed twiddle factor, is negated and hand over accordingly according to twiddle factor generation It changes enabled；It enables to carry out phase rotation respectively to the input data after enabled operation according to negating and exchanging, obtains the main wave of each layer The data of beam and auxiliary wave beam；Specifically, according to certain layer of input second PMI i₂This layer of twiddle factor q of needs is decomposited, According to q generate accordingly negate with exchange enable, according to enable major-minor wave beam input data is respectively processed；Unit the 6th For: it will obtain being added the two to obtain final code-book data after corresponding to major-minor beam data, Unit the 5th and Unit the 6th can To be realized by optional circuit, Fig. 6 is composition block diagram of the present invention using the another optional circuit of example, as shown in Figure 6, comprising:

Tenth module 601 is used for: being decomposed and is obtained twiddle factor；This application example twiddle factor q need for main beam and Auxiliary wave beam is chosen respectively, is designed based on existing LTE protocol codebook design principle, the method for selection are as follows: when counter output is small When N1*N2 (code book top half), comparator output is 0, and data selector selects data 0, at this time main beam twiddle factor q It is selected as 0, auxiliary wave beam twiddle factor q is selected as second PMI i₂Minimum 2bit；When counter output is more than or equal to N1*N2 When (code book lower half portion), comparator output is 1, and data selector selects data 1, and main beam twiddle factor q is selected as second PMI i₂2 bit of highest (bit), auxiliary wave beam twiddle factor q are selected as second PMI i₂Minimum 2bit and centre The minimum 2bit of 2bit summed result.Then it is respective major-minor wave beam to be generated by combinational logic according to major-minor wave beam twiddle factor It is as shown in table 5 to generate corresponding relationship for enable signal:

Twiddle factor (2bit)	Real part negates enabled	Imaginary part negates enabled	Real empty exchange is enabled
				00	0	0	0
01	0	1	1
				10	1	1	0
11	1	0	1

Table 5

11st module 602 is used for: according to what twiddle factor generated enabling that main beam data are swapped and negated with behaviour Make, obtains the data of main beam and auxiliary wave beam, be added with the main beam of acquisition and the data of auxiliary wave beam, and the number obtained after being added with It is stored according to as code book；May include: main beam data real part imaginary part is stored separately, if real part/imaginary part negate enable be 1, inversion operation is being carried out to real part/imaginary part respectively；Enable to be 0 if real part/imaginary part negates, without to real part/imaginary part into Row processing, directly output initial value.Next, then data selector selection data 1 output (is completed as the exchange of fruit void enables to be 1 Real part imaginary part exchange)；If the exchange of fruit void enables to be 0, then data selector selection data 0 export (real part imaginary part does not exchange). Results added is exported by the main beam real part data selector after enabled operation is carried out according to twiddle factor, and stores and is posted to result Imaginary data selector is exported results added, and stores and arrive result register imaginary part by storage real part.The register of storage is real Portion and register imaginary part are completed code book and are generated as code book.

Using example two

According to the value of all N1, N2, all value arrays { 2,3,6,8,10,12,14,16 } of N1*N2 are formed, are obtained The least common multiple 1680 of each element into the array obtains corresponding DFT base infrastructure elements multiplied by over-sampling multiple 4 Number is 6720；Quadrant compression and storage method is used again, is only stored the value of first quartile in all DFT bases, is needed to store so altogether 1680 DFT bases, while in view of avoiding the power factor from beingWhen multiplying, then store 1680 DFT bases multiplied by Afterwards as a result, storing the address of each DFT base infrastructure elements can be obtained by following formula:

DFT base infrastructure elements are stored in sequence；Wherein, the real and imaginary parts of each DFT base respectively account for 1 byte (Byte), as soon as using a storage address, address is 0~3359 in this example.

Step 2: according to the first PMI1 i of input₁₁、first PMI2 i₁₂、first PMI3 i₁₃, it is sequentially generated The addressable address and real part of the major-minor each DFT base infrastructure elements of wave beam/imaginary part exchange enable signal, real part/imaginary part negate enabled Signal, primary/secondary enable signal；According to the addressable address of generation take out DFT base infrastructure elements after, respectively according to enabled information into Row is exchanged and inversion operation, obtains the major-minor carrier wave DFT base of final output.Due to N1=4, N2=4, major-minor wave beam is every at this time A DFT base contains N1*N2=16 plural elements, be sequentially generated at this time this 32 element (main beam 16, auxiliary wave beam 16 It is a)；It is specific:

The embodiment of the present invention realizes the following contents by accumulator, obtains output step value according to the value of N1, N2 first S_N1、S_N2；S in this example_N1=420, S_N2=420；According to 1 i of first PMI of input₁₁、first PMI 2 i₁₂It obtains major-minor Wave beam totalizing step S_{N1_add}=i₁₁*S_N1=4200, S_{N2_add}=i₁₂*S_N2=840, according to first PMI3 i₁₃Obtain auxiliary wave The d of beam₁=2, d₂=0；And obtain auxiliary beam deviation step-length Off_N1=2*4*420=3360, Off_N2=0*4*420=0 is generated The corresponding addressable address sequence of 16 elements of main beam:

{0,S_{N2_add},2S_{N2_add},...(N2-1)S_{N2_add},0+S_{N1_add},S_{N2_add}+S_{N1_add},...

(N2-1)S_{N2_add}+S_{N1_add},0+(N1-1)S_{N1_add},S_{N2_add}+(N1-1)S_{N1_add},

2*S_{N2_add}+(N1-1)S_{N1_add},...(N2-1)S_{N2_add}+(N1-1)S_{N1_add}}；

And the addressable address sequence of auxiliary wave beam:

{0,S_{N2_add}+Off_N2,2(S_{N2_add}+Off_N2),...(N2-1)(S_{N2_add}+Off_N2),0+S_{N1_add}+Off_N1,

2*(S_{N2_add}+Off_N2)+S_{N1_add}+Off_N1,...(N2-1)(S_{N2_add}+Off_N2)+S_{N1_add}+Off_N1,

0+(N1-1)(S_{N1_add}+Off_N1),S_{N2_add}+Off_N2+(N1-1)(S_{N1_add}+Off_N1),

2*(S_{N2_add}+Off_N2)+(N1-1)(S_{N1_add}+Off_N1),...

(N2-1)(S_{N2_add}+Off_N2)+(N1-1)(S_{N1_add}+Off_N1)}；

It is total according to DFT base infrastructure elements to each address in major-minor wave beam address sequence after generating addressable address sequence Number 6720 carries out the addressable address that remainder obtains its DFT base infrastructure elements；Wherein, main beam be 0,840,1680,2520, 4200,5040,5880,0,1680,2520,3360,4200,5880,0,840,1680 }, auxiliary wave beam be 0,840,1680, 2520,840,1680,2520,3360,1680,2520,3360,4200,2520,3360,4200,5040 }；Finally according to above-mentioned Address sequence generates major-minor wave beam first quartile address and enable signal, and production method is for the ground in [0,1679] range Location, first quartile address are raw address, and real part, which negates, to be enabled to be 0, and imaginary part, which negates, to be enabled to be 0, and the exchange of real part imaginary part is enabled It is 0, for the address in [1680,3359] range, first quartile address is that raw address subtracts 1680, and real part negates enabled It is 0, imaginary part, which negates, to be enabled to be 1, and the exchange of real part imaginary part enables to be 1, for the address in [3360,5039] range, first Quadrant address is that raw address subtracts 3360, and real part, which negates, to be enabled to be 1, and imaginary part, which negates, to be enabled to be 1, and the exchange of real part imaginary part enables to be 0, For the address in [5040,6719] range, first quartile address is that raw address subtracts 5040, and real part, which negates, to be enabled to be 0, Imaginary part, which negates, to be enabled to be 1, and the exchange of real part imaginary part enables to be 1, the final first quartile address of this example and it is enabled as shown in table 6 and table 7:

Table 6

Table 7

The embodiment of the present invention, by power factor modified address, which only carries out address correction to auxiliary wave beam, together When be only 1680 in P=2, remaining p value is 0, and due to p=1, the power factor modified address in this example is 0, therefore is directly pressed DFT base infrastructure elements data are successively taken out according to first quartile address, real part/imaginary part is carried out according still further to enable signal and negates and exchange Processing, finally obtains the corresponding DFT basic sequence of major-minor wave beam；Wherein, main beam are as follows:

Due to power factor P=1, move to right for auxiliary wave beam one processing at this time, use power adjustment Auxiliary wave beam DFT basic sequence after obtaining power adjustment multiplied by auxiliary wave beam DFT basic sequence:

According to 1/2 layer of respective second PMI i_2,1, i_2,2Value obtains 1/2 layer of respective three twiddle factor.Its Middle i_2,1,i_2,2Value range be [0,63], indicated using 6bits unsigned number, 1 layer of three twiddle factor q_1,1,q_2,1,q_3,1Point I is not taken_2,1, highest 2bits, centre 2bits and minimum 2bits, 2 layers of three twiddle factor q_1,2, q_2,2,q_3,2I is taken respectively_2,2 Highest 2bits, centre 2bits and minimum 2bits.Q in this example_1,1=0, q_2,1=1, q_3,1=3, q_1,2=2, q_2,2=1, q_3,2 =1.

According to the major-minor wave beam DFT basic sequence and 1/2 layer of twiddle factor of acquisition, respectively to major-minor wave beam DFT basic sequence Phase rotation is carried out according to upper and lower two parts, code book sequence after 1/2 layer of respective major-minor wave beam rotation is obtained, wherein two up and down Every partial sequence length is DFT basic sequence length in point.Method of adjustment are as follows: for twiddle factor=0, adjusted value is exactly former member Element；For twiddle factor=1, newtonium imaginary part is exactly negated again the exchange of real part imaginary part by adjusted value；For twiddle factor=2, Adjusted value exactly negates newtonium real part imaginary part；For twiddle factor=3, adjusted value exactly negates newtonium real part again real The exchange of portion's imaginary part.

Specifically, 1 layer of code book top half of main beam is exactly main beam DFT basic sequence, without being adjusted, main beam 1 layer of code book top half are as follows:

1 layer of code book top half of auxiliary wave beam is according to q_3,1=3 carry out phase rotation, 1 layer of code book top half of auxiliary wave beam are as follows:

1 layer of code book lower half portion of main beam is according to q_1,1=0 carries out phase rotation, 1 layer of code book lower half portion of main beam are as follows:

1 layer of code book lower half portion of auxiliary wave beam is according to q_2,1+q_1,1=1 is rotated, 1 layer of code book lower half of auxiliary wave beam:

2 layers of code book top half of main beam are exactly main beam DFT basic sequence, without being adjusted, on 2 layers of code book of main beam Half part are as follows:

2 layers of code book top half of auxiliary wave beam are according to q_3,2=1 carries out phase rotation, 2 layers of code book top half of auxiliary wave beam:

2 layers of code book lower half portion of main beam are according to q_1,2=2 carry out phase rotation, 2 layers of code book lower half portion of main beam are as follows:

2 layers of code book lower half portion of auxiliary wave beam are according to q_2,2+q_1,2=3 are rotated, 1 layer of code book lower half sequence of auxiliary wave beam Are as follows:

Final goes out the respective code book sequence of 1/2 layer of major-minor wave beam, wherein every layer of each wave beam includes N1*N2*2=32 Element.

To above-mentioned every layer of code book sequence of generation, successively by the element in the major-minor wave beam code book sequence of same position into Row is added, and is obtained 2 layers of final code book and is stored.

Specifically, for 1 layer of code book, by the totally 32 elements successively phase of top and the bottom in 1 layer of code book sequence of major-minor wave beam Add, obtain 1 layer of final code book sequence are as follows:

For 2 layers of code book, by top and the bottom in 2 layers of code book sequence of major-minor wave beam, totally 32 elements are successively added, and are obtained most 2 layers of whole code book sequence are as follows:

Finally 1/2 layer of code book sequence is successively stored and is generated in code book memory.

From above step as can be seen that generating for the present embodiment present invention by simple address, memory is read, it is real Portion's imaginary part is exchanged/is negated, the multiply-add precoding codebook matrix that can generate needs of real number of displacement and finite number of time.It compares Compared with existing offline storage technology, present invention only requires storage very small part DFT base element value, the memory space needed is only About 7kB, and existing offline storage needs at least 1GB memory space, ten a ten thousandths of the storage about prior art needed for the present invention, Simultaneously also without promoting excessive complexity in terms of addressing；Compare and existing online generation technique, the present invention by part from Line, which stores, the operation such as exchanges/negates with real part imaginary part, it is entirely avoided the complicated calculations such as exponent arithmetic and complex multiplication drop significantly The low implementation complexity of online generation.

Code book production method of the present invention is every when searching for the major-minor optimal PMI of wave beam (i.e. the search of first PMI and p) Secondary code book generates the description of implementation procedure such as one step 1~bis- of embodiment, by result in the main beam memory in module 203 The step of directly exporting, merging without progress phase rotation with wave beam.The method of this beamformer output DFT base in advance can be into one Step reduces the complexity that code book generates, and accelerates code book and generates speed.

Code book production method of the present invention searches for optimal second PMI in the optimal value for determining first PMI and p When code book generate implementation procedure and need to only carry out primary/secondary wave beam in one step 1 of embodiment~bis- processes and reservation module 203 The value of memory is generated when subsequent each second PMI variation needs to generate code book without primary/secondary wave beam basic sequence is carried out The step of, only repeating step 3~tetra- can be completed code book generation.The method that this second PMI code book quickly generates The complexity of code book generation can be further decreased, accelerates code book and generates speed.

Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program Related hardware (such as processor) is completed, and described program can store in computer readable storage medium, as read-only memory, Disk or CD etc..Optionally, one or more integrated circuits also can be used in all or part of the steps of above-described embodiment It realizes.Correspondingly, each module/unit in above-described embodiment can take the form of hardware realization, such as pass through integrated electricity Its corresponding function is realized on road, can also be realized in the form of software function module, such as is stored in by processor execution Program/instruction in memory realizes its corresponding function.The present invention is not limited to the hardware and softwares of any particular form In conjunction with.

Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.

Claims

1. a kind of method realizing code book and generating characterized by comprising

The addressable address of DFT base infrastructure elements is determined according to code book related information, and enabled operation is carried out to DFT base infrastructure elements Enabled information；

Addressable address is exported according to preset address enable signal；Wherein, the addressable address of output is used for generated code for taking out This DFT base infrastructure elements；

DFT base infrastructure elements are taken out according to the addressable address of output, according to the enabled information of output to the DFT base basis member of taking-up Element carries out enabled operation, and the data after enabled operation are stored to preset DFT basic sequence storage region；

Twiddle factor is decomposed, and phase rotation is carried out to the data after enabled operation according to the twiddle factor obtained is decomposed, is obtained The data of each layer main beam and auxiliary wave beam；

Wherein, the addressable address of the DFT base infrastructure elements includes: the addressable address of the DFT base infrastructure elements of main beam and auxiliary The addressable address of the DFT base infrastructure elements of wave beam；

The enabled operation includes: real empty exchange and/or negates.

2. the method according to claim 1, wherein the default DFT base infrastructure elements include:

Wherein, each DFT base infrastructure elements are stored by a corresponding address；Each address includes 1 for storage element real part 1 byte of a byte and storage element imaginary part.

3. according to the method described in claim 2, it is characterized in that, the default DFT base infrastructure elements are according to following address Storage:

4. described in any item methods according to claim 1~3, which is characterized in that the code book related information includes with lower part Point or all information:

Horizontal direction oversample factor O1, vertical direction oversample factor O2, the horizontal port number N1 of antenna, antennas orthogonal port number N2, first order code book index 1first PMI1, first order code book index 2first PMI2, first order code book index 3first PMI3, power factor configuration information p.

5. described in any item methods according to claim 1~3, which is characterized in that described according to preset address enable signal Exporting addressable address includes:

One or more accumulators are controlled according to the preset address enable signal, to export the addressable address；

6. described in any item methods according to claim 1~3, which is characterized in that the decomposition twiddle factor includes:

Wherein, the twiddle factor includes: the phase rotation coefficient and auxiliary wave beam packet for the upper and bottom section that main beam includes The phase rotation coefficient of the upper and bottom section contained.

7. a kind of device realizing code book and generating characterized by comprising first unit, second unit, third unit, the 4th Unit, Unit the 5th and Unit the 6th；Wherein,

Second unit is used for: the addressable address of DFT base infrastructure elements is determined according to code book related information, and to DFT base basis member Element carries out making operable enabled information；

Third unit is used for: exporting addressable address according to preset address enable signal；Wherein, the addressable address of output is for taking Out for generating the DFT base infrastructure elements of code book；

Unit the 4th is used for: DFT base infrastructure elements is taken out according to the addressable address of output, according to the enabled information of output to taking-up DFT base infrastructure elements carry out enabled operation, and by the data storage after enabled operation to preset DFT basic sequence memory block Domain；

Unit the 5th is used for: being decomposed twiddle factor, and is carried out according to the twiddle factor obtained is decomposed to the data after enabled operation Phase rotation obtains the data of each layer main beam and auxiliary wave beam；

Unit the 6th is used for: being added with the main beam of acquisition and the data of auxiliary wave beam, and the data obtained after being added with are as code book Storage；

The enabled operation includes: real empty exchange and/or negates.

8. device according to claim 7, which is characterized in that the default DFT base infrastructure elements include:

9. device according to claim 8, which is characterized in that the default DFT base infrastructure elements are according to following address Storage:

10. according to the described in any item devices of claim 7~9, which is characterized in that the code book related information includes with lower part Point or all information:

11. according to the described in any item devices of claim 7~9, which is characterized in that the third unit is specifically used for:

12. according to the described in any item devices of claim 7~9, which is characterized in that Unit the 5th for decompose rotation because Son includes:

13. a kind of computer storage medium, computer executable instructions, the calculating are stored in the computer storage medium Machine executable instruction is for method described in any one of perform claim requirement 1~5.

14. a kind of terminal, comprising: memory and processor；Wherein,

Processor is configured as executing the program instruction in memory；

Program instruction reads in processor and executes following operation:

Store the default DFT base infrastructure elements generated offline；

The enabled operation includes: real empty exchange and/or negates.