CN109801897B

CN109801897B - Chip stack three-dimensional packaging structure and manufacturing method thereof

Info

Publication number: CN109801897B
Application number: CN201711138426.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2017-11-16
Filing date: 2017-11-16
Publication date: 2021-03-16
Anticipated expiration: 2037-11-16
Also published as: CN109801897A

Abstract

The invention provides a chip stack three-dimensional packaging structure and a manufacturing method thereof. The package structure includes: a die stack comprising a first die and an underlying die directly joined in a gapless manner; the first chip and the bottom chip are respectively provided with a first test pad and a first through hole, and a bottom test pad and a bottom through hole, wherein a first bearing pad and a bottom bearing pad are respectively formed at one end of the first through hole and one end of the bottom through hole, and the bottom through hole penetrates through the bottom test pad and is communicated to the first bearing pad, so that the bottom chip is electrically connected with the first chip. The manufacturing method comprises the following steps: forming a test pad on the surface of the wafer, testing the wafer by using the test pad, and directly bonding the wafer meeting the yield reference value; forming a through hole and a bearing pad to form electrical connection between the wafers; and cutting the substrate into a single body to form a chip stack three-dimensional packaging structure. According to the invention, the wafers are directly jointed, so that the signal transmission distance between the chips is shortened, and the packaging size is reduced; the yield is tested before the wafers are jointed, the low-yield wafers are prevented from being stacked, and the cost is saved.

Description

Chip stack three-dimensional packaging structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a chip stack three-dimensional packaging structure and a manufacturing method thereof.

Background

With the development of electronic products toward miniaturization, high density and high performance, Through Silicon Via (TSV) is used

2.5D (2.5Dimensional ) and 3D (3 Dimensional) stack packaging of (Through Silicon Via, TSV) have become more and more dominant technologies in the field of high density packaging. At present, for a Chip with through silicon via, a micro bump is generally formed on a Chip surface, and a Chip to Chip (C2C) or a Chip to Wafer (C2W) is connected by reflow soldering to form a Chip stack structure. Fig. 1 shows a typical stack package structure of a memory chip (memory chip) and a buffer chip (buffer chip). As shown in the figure, the

memory chips

112, 113 and the buffer chip 114 respectively have through-

silicon vias

112C, 113C and 114C,

micro bumps

111D, 112D and 113D are formed on the surfaces of the

chips

111, 112 and 113, respectively, and the memory chips and the buffer chip are bonded and connected through the micro bumps to form a chip stack 110; a Redistribution Layer (RDL) 120 is formed on the surface of the chip stack 110, so that the chip stack 110 is bonded to the substrate 140 in a flip chip bonding manner.

Compared with the traditional lead bonding mode, the packaging body structure formed by connecting the TSV and the micro bumps has the advantages that although the distance of signal transmission is greatly improved and the packaging size is obviously reduced, the problems of signal transmission deficiency and wafer damage during bonding are more and more difficult to overcome by adopting the micro bump connection mode along with the continuous improvement of the signal transmission quality requirement and the requirements on packaging miniaturization and high reliability. In addition, the micro bump method is generally used for connecting chips to chips or connecting chips to wafers, but the production efficiency is lower than that of the Wafer to Wafer (W2W) connection method. Therefore, the direct connection between the wafer and the through silicon via technology and the non-micro bump is becoming a development direction for the technology in the high density package field.

On the other hand, the conventional wafer-to-wafer connection method tests the wafers after the wafers are bonded and stacked, and if a wafer yield is found to be too low, the overall yield of the stacked package structure will be affected, resulting in cost loss.

The above description is intended only to aid those skilled in the art in understanding the background of the invention and is not intended to be a representation that is known or suggested to those skilled in the art.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a chip stack three-dimensional package structure to solve at least the problems in the prior art.

The technical solution of the embodiment of the present invention is achieved by providing a chip stack three-dimensional package structure according to an embodiment of the present invention, including:

a chip stack comprising: the first active surface of the first chip is directly attached to the stack back surface of the bottom chip in a gapless mode; the chip structure comprises a bottom chip and a plurality of bottom test pads, wherein the bottom chip is internally provided with a plurality of bottom perforations and a plurality of bottom bearing pads formed at one end of the bottom perforations, the bottom perforations penetrate through a first passivation layer of the first chip and are arranged on surface bonding pads of the first chip, and the bottom perforations further penetrate through a semiconductor layer of the bottom chip and are communicated to the bottom test pads of the bottom chip so as to be electrically connected with the first chip and the bottom chip.

In some embodiments, the surface pad is a first test pad of the first chip or a first support pad at one end of a first through hole of the first chip;

the chip stack three-dimensional packaging structure further comprises:

a first redistribution layer formed on the mounting surface, the first redistribution layer being electrically connected to the underlying support pad;

and the flip chip terminals are arranged on the first rewiring layer.

In some embodiments, the first active surface of the first chip and the stack back surface of the bottom chip are both plasma activated surfaces.

In some embodiments, the first chip has the first active surface and a stack back surface opposite to the first active surface, the first chip has a first active region, a surface of the first active region is formed with a first test pad, the first chip further has a plurality of first through holes therein and a plurality of first support pads formed at one end of the first through holes, the first chip includes a first passivation layer for providing the first active surface;

the bottom chip has a bottom active region, the bottom test pad is formed on a surface of the bottom active region, and the bottom chip further includes a bottom passivation layer for providing the mounting surface.

In some embodiments, the bottom layer via is integrally formed as the bottom layer receiving pad at one end of the mounting surface; and a bottom isolation layer is formed between the bottom bearing pad and the bottom passivation layer.

In some embodiments, at least one additional chip is stacked on the stacked back surface of the first chip, each additional chip has the same structure as the first chip, the additional chip has a second active surface and a stacked back surface opposite to the second active surface, the second active surface of the additional chip is directly attached to the stacked back surface of the first chip in a gapless manner, a plurality of second test pads of the additional chip are formed on the surface of a second active region of the additional chip, and the additional chip comprises a second passivation layer for providing the second active surface; the additional chip further comprises a plurality of second through holes and a plurality of second bearing pads formed at one end of the second through holes, and the first through holes penetrate through the second passivation layer of the additional chip and are communicated with the second bearing pads so as to electrically connect the first chip and the additional chip.

In some embodiments, the first chip and the additional chip are both memory chips, and the bottom chip is selected from one of a buffer chip and a memory chip.

In some embodiments, the bottom layer via includes a first portion and a second portion, the first portion of the bottom layer via includes, in order from the hole wall toward the hole center axis, an insulating layer, a barrier layer, a seed layer, and a conductor, and the second portion of the bottom layer via includes, in order from the hole wall toward the hole center axis, a barrier layer, a seed layer, and a conductor; the demarcation point of the first part of the bottom layer through hole and the second part of the bottom layer through hole is located between the first test pad and the bottom layer test pad and is 0-5 mu m away from the bottom layer test pad, so that the bottom layer through hole is electrically connected with the bottom layer test pad.

In some embodiments, the first pad has a width dimension of 2 to 5 times the diameter of the bottom layer through hole, and the first test pad has a length dimension of 4 to 15 times the diameter of the bottom layer through hole.

In some embodiments, the chip stack further comprises a substrate having a chip-bonding surface and a terminal-bonding surface, the chip stack being flip-chip bonded to the chip-bonding surface of the substrate via the flip-chip terminals.

In some embodiments, the substrate is a silicon interposer, including a plurality of through silicon interposer vias; the terminal bonding surface is formed with a second rewiring layer, the second rewiring layer is formed with an external terminal, and the external terminal is electrically connected to the flip chip terminal through the second rewiring layer and the through-silicon-interposer via.

A manufacturing method of a chip stack three-dimensional packaging structure comprises the following steps:

providing a first chip wafer and providing a bottom chip wafer, wherein the first chip wafer is provided with a first active surface, and the bottom chip wafer is provided with a mounting surface and a stack back surface opposite to the mounting surface;

directly bonding the stack back surface of the bottom chip wafer to the first active surface of the first chip wafer in a gapless manner; and

forming a plurality of bottom layer through holes and a bottom layer bearing pad in the bottom layer chip wafer, wherein the bottom layer bearing pad is formed at one end of the bottom layer through hole, the bottom layer through hole penetrates through a first passivation layer of the first chip wafer and is arranged on a surface welding pad of the first chip wafer, and the bottom layer through hole penetrates through a semiconductor layer of the bottom layer chip wafer and is communicated with a bottom layer test pad of the bottom layer chip wafer.

the manufacturing method of the chip stack three-dimensional packaging structure further comprises the following steps:

forming a first redistribution layer on the mounting surface of the bottom chip wafer, the first redistribution layer

The wire layer is electrically connected with the bottom layer bearing pad;

arranging a plurality of flip chip terminals on the first redistribution layer;

and performing monomer cutting to form a plurality of chip stack three-dimensional packaging structures.

In some embodiments, the first chip wafer and the bottom chip wafer are wafers that have been tested and have a chip yield greater than or equal to a yield reference value.

In some embodiments, the back surface of the bottom chip wafer and the first active surface of the first chip wafer are formed into plasma activated surfaces by a plasma activation technique and directly bonded in a gapless manner.

Due to the adoption of the technical scheme, the implementation mode of the invention has the following advantages:

1) through direct bonding of the wafers, the signal transmission distance between the chips is reduced, the signal quality is improved, the size of a packaging body is reduced, and the bonding efficiency is improved;

2) the yield is tested before the wafers are bonded, so that the low-yield wafers are prevented from being stacked, and the production cost is saved.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.

Fig. 1 is a schematic diagram of a chip stacking package structure using micro bumps.

Fig. 2 is a schematic diagram of a chip stack three-dimensional package structure according to an embodiment of the invention.

Fig. 3 is a partially enlarged view illustrating the structure of a chip stack according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 5 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 6 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 7 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 8 is a partially enlarged view illustrating the structure of a chip stack according to another embodiment of the present invention.

Fig. 9 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 10 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 11 is a schematic diagram of a chip stack three-dimensional package structure according to another embodiment of the invention.

Fig. 12 is a schematic diagram of a chip stack three-dimensional package structure according to yet another embodiment of the invention.

Fig. 13 is a manufacturing process of a chip stack three-dimensional package structure according to an embodiment of the invention.

Reference numerals

100: the chip stack three-dimensional packaging structure of the background art;

110: a chip stack; 111: a top chip; 111D: a flip chip terminal of the top chip; 112: a second chip; 112C: a through hole of the second chip; 112D: a flip chip terminal of the second chip; 113: a first chip; 113C: a through hole of the first chip; 113D: a flip-chip terminal of the first chip; 114: a bottom chip; 114A: a mounting surface; 114C: perforating the bottom chip;

120: a first rewiring layer; 121: a first redistribution routing;

130: a flip chip terminal;

140: a substrate; 141: a multilayer circuit; 142: a chip bonding surface; 143: a terminal bonding surface;

150: base glue;

160: molding the body;

170: a second metal pad;

180: and an external terminal.

200: embodiment 1 of the present invention;

210: a chip stack; 211: a top chip; 211A: a top active surface; 211B: carrying out wafer back; 212: a second chip; 212A: a second active surface; 212B: the stack back of the second chip; 212C: a second perforation; 213: a first chip; 213A: a first active surface; 213B: a stack back side of the first chip; 213C: a first perforation; 213H: a first bearing pad; 214: a bottom chip; 214A: a mounting surface; 214B: the back of the stack of the bottom chip; 214C: perforating the bottom layer;

220: a first rewiring layer; 221: a first redistribution routing;

230: a flip chip terminal;

240: a substrate; 241: a multilayer circuit; 242: a chip bonding surface; 243: a terminal bonding surface;

250: base glue;

260: molding the body;

270: a second metal pad;

280: and an external terminal.

B00: local amplification of the package structure of embodiment 1 of the present invention;

211D: a top substrate; 211E: a top active region; 211 EA: a top active region surface; 211F: a top test pad; 211G: a top passivation layer;

212 CA: a first portion of a second perforation; 212 CB: a second portion of the second perforation; 212C 1: an insulating layer; 212C 2: a barrier layer; 212C 3: a conductor; 212D: a second substrate; 212E: a second active region; 212 EA: a second active region surface; 212F: a second test pad; 212G: an inner passivation layer; 212H, and (3) a: a second bearing pad; 212J: a second isolation layer; 212K: a second passivation layer;

213 CA: a first portion of a first perforation; 213 CB: a second portion of the first perforation; 213C 1: an insulating layer; 213C 2: a barrier layer; 213C 3: a conductor; 213D: a first substrate; 213E: a first active region; 213 EA: a first active region surface; 213F: a first test pad; 213G: an inner passivation layer; 213H: a first bearing pad; 213J: a first isolation layer; 213K: a first passivation layer;

214 CA: a first portion of the bottom layer perforation; 214 CB: a second portion of the bottom layer perforation; 214C 1: an insulating layer; 214C 2: a barrier layer; 214C 3: a conductor; 214D: a base substrate; 214E: a bottom active region; 214 EA: a bottom active region surface; 214F: a bottom test pad; 214G: an inner passivation layer; 214H: a bottom layer bearing pad; 214J: a bottom layer isolation layer; 214K: a bottom passivation layer;

222: a first dielectric layer; 223: a second dielectric layer;

290: a first metal pad.

300: embodiment 2 of the present invention;

310: a chip stack; 314: a bottom chip; 314A: a mounting surface; 314B: a stacking surface of the bottom chip; 314C: and (4) perforating the bottom chip.

400: embodiment 3 of the present invention;

410: and a chip stack.

500: embodiment 4 of the present invention;

510: and a chip stack.

600: embodiment 5 of the present invention;

610: and a chip stack.

C00: the package structure of embodiment 5 of the present invention is partially enlarged.

700: embodiment 6 of the present invention;

710: and a chip stack.

800: embodiment 7 of the present invention;

810: and a chip stack.

815: a third chip; 815A: a third active surface; 815B: the back of the stack of the third chip; 815C: and (3) perforation of the third chip.

900: embodiment 8 of the present invention;

910: and a chip stack.

A00: embodiment 9 of the present invention;

a40: a silicon interposer; a41: perforating the silicon intermediate plate; a42: a chip bonding surface; a43: a terminal bonding surface;

a90: a second rewiring layer; a91: and a second redistribution circuit.

S100: a manufacturing process of the package structure of embodiment 2 of the present invention;

w11: a top chip wafer; w12: a second chip wafer; w13: a first chip wafer; w14: a bottom chip wafer;

212 HA: a second receiving pad hole.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "square," and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.

Embodiment mode 1

Fig. 2 is a schematic diagram of a chip stack three-dimensional package structure according to an embodiment of the invention. As shown in fig. 2, the chip stack three-dimensional package structure 200 according to the embodiment of the present invention includes: the chip package comprises a chip stack body 210, a first redistribution layer 220, a flip chip terminal 230, a substrate 240, an underfill 250, a plastic package body 260, a second metal pad 270, and an external terminal 280. The chip stack 210 includes: top chip 211, second chip 212, first chip 213, and bottom chip 214; top die 211 has a top active surface 211A and a back side 211B opposite top active surface 211A, second die 212 has a second active surface 212A and a stack back side 212B opposite second active surface 212A, first die 213 has a first active surface 213A and a stack back side 213B opposite first active surface 213A, and bottom die 214 has a mounting surface 214A and a stack back side 214B opposite mounting surface 214A; the active surface of each chip and the stack back surface of the chip adjacent to it, for example, the first active surface 213A of the first chip 213 and the stack back surface 214B of the bottom chip 214, are directly bonded to each other without a gap by forming a free bond by a plasma activation technique.

The second chip 212, the first chip 213 and the bottom chip 214 respectively include a plurality of second through holes 212C, first through holes 213C and bottom through holes 214C, and the through holes of the chips are connected to each other, so that the chips are electrically connected to each other through the through holes. The bottom chip 214 has a mounting surface 214A, a first redistribution layer 220 is formed on the mounting surface 214A, a first redistribution layer 221 is formed therein, and the first redistribution layer 221 is electrically connected to the bottom through hole 214C. A plurality of first metal pads (not shown) having Fan-out (Fan-out) formed on the surface of the first redistribution layer 220, and electrically connected to the first redistribution layer 221; a plurality of flip-chip terminals 230 are disposed on the first metal pads.

The substrate 240 is a BGA (Ball Grid Array) substrate, and includes a plurality of layers of circuits 241, and has a chip bonding surface 242 and a terminal bonding surface 243 disposed opposite to each other, and the chip stack 210 is flip-chip bonded to the chip bonding surface 242 of the substrate 240 through a plurality of flip-chip terminals 230 disposed on the first redistribution layer 220. An underfill 250 is filled between the surface of the first redistribution layer 220 and the die attach surface 242 of the substrate 240 to encapsulate the flip-chip terminals 230 and mitigate thermal stress mismatch between the first redistribution layer 220 and the substrate 240.

The molding compound 260 is formed on the chip bonding surface 242 of the substrate 240 to seal the chip stack 210, thereby forming a single-sided molding type of the substrate 240. A plurality of second metal pads 270 formed on the terminal bonding surface 243 of the substrate 240, and the external terminals 280 are disposed on the second metal pads 270, wherein the external terminals 280 may be a plurality of solder balls, and the second metal pads 270 may be Under Bump Metallurgy (UBM) so that the external terminals 280 and the terminal bonding surface 243 of the substrate 240 are firmly bonded. Here, the first redistribution line 221 shown in fig. 2 is a schematic representation for explanation only, and is not a specific connection method, and it is not to be understood that the connection method is limited to this connection method.

To further illustrate the connection mode between the through holes of the respective chips, the internal structure of the respective chips, particularly the structure and connection of the respective through holes and the receiving pads, will be described below. Fig. 3 is a partially enlarged schematic view of the structure of the chip stack and the first redistribution layer in the chip stack three-dimensional package structure according to embodiment 1 shown in fig. 2. As shown in fig. 3, the chip stack 210 shown in fig. 2 mainly includes: a top chip 211, a second chip 212, a first chip 213 and a bottom chip 214; wherein, the first chip 213 includes: the test device includes a plurality of first through holes 213C, a first substrate 213D, a first active region 213E, a plurality of first test pads 213F, an inner passivation layer 213G, a plurality of first bonding pads (bonding pads) 213H, a first isolation layer (block layer)213J, and a first passivation layer 213K, and has a first active surface 213A and a stack back surface 213B opposite to the first active surface 213A.

The first test pad 213F is formed on the surface 213EA of the first active region 213E, and the inner passivation layer 213G covers the surface 213EA of the first active region 213E and the plurality of first test pads 213F.

The first through hole 213C penetrates the inner passivation layer 213G, the first test pad 213F, the first active region 213E, and the first substrate 213D of the first chip 213; the first through hole 213C is formed with a first receiving pad 213H at an end close to the first test pad 213F, and a surface of the first receiving pad 213H away from the first test pad 213F is flush with a surface of the inner passivation layer 213G.

The first isolation layer 213J covers the inner passivation layer 213G and the plurality of first supporting pads 213H, and the first passivation layer 213K covers the first isolation layer 213J. The first isolation layer 213J functions to block Cu atoms in the conductor 213C3 of the first contact pad 213H from diffusing in the axial direction under the action of current, and in one embodiment, the first isolation layer 213J may be a multi-layer structure of a compound containing Si, C, N, or the like. A surface of the first passivation layer 213K is provided as a first active surface 213A of the first chip 213.

The bottom chip 214 has the same structure as the first chip 213, and includes: a plurality of bottom vias 214C, a bottom substrate 214D, a bottom active region 214E, a plurality of bottom test pads 214F, an inner passivation layer 214G, a plurality of bottom landing pads 214H, a bottom isolation layer 214J, and a bottom passivation layer 214K, and having a mounting surface 214A and a stack back surface 214B opposite the mounting surface 214A.

The stack back surface 214B of the bottom chip 214 and the first active surface 213A of the first chip 213 are formed into plasma-activated surfaces by a plasma activation technique, and are directly bonded in a gapless manner.

Bottom test pad 214F is formed on surface 214EA of bottom active region 214E, and inner passivation layer 214G covers surface 214EA of bottom active region 214E and the plurality of bottom test pads 214F.

The bottom through hole 214C further penetrates through the inner passivation layer 214G, the bottom test pad 214F, the bottom active region 214E, the bottom substrate 214D, and the first passivation layer 213K and the first isolation layer 213J of the first chip 213, and is electrically connected to the first support pad 213H; the bottom layer via 214C is formed with a bottom layer contact pad 214H at an end near the bottom layer test pad 214F, and a surface of the bottom layer contact pad 214H away from the bottom layer test pad 214F is flush with a surface of the inner passivation layer 214G.

Bottom isolation layer 214J covers inner passivation layer 214G and a plurality of bottom contact pads 214H, and bottom passivation layer 214K covers bottom isolation layer 214J. The surface of the underlying passivation layer 214K is provided as a mounting surface 214A of the underlying chip 214.

Bottom layer via 214C includes a first portion 214CA and a second portion 214CB, first portion 214CA of bottom layer via 214C includes, in order from the hole wall toward the hole center axis, an insulating layer 214C1, a barrier layer 214C2, a seed layer (not shown), and a conductor 214C3, and second portion 214CB of bottom layer via 214C includes, in order from the hole wall toward the hole center axis, a barrier layer 214C2, a seed layer (not shown), and a conductor 214C 3. In one embodiment, the boundary point between the first portion 214CA and the second portion 214CB of the bottom layer through hole 214C is located between the bottom layer test pad 214F and the first receiving pad 213H and is spaced from the bottom layer test pad 214F by 0-5 μm, so that the bottom layer through hole 214C penetrates and is electrically connected to the bottom layer test pad 214F. The insulating layer 214C1 is used to block the bottom via 214C from making electrical contact with the bottom substrate 214D and the bottom active region 214E, and in one embodiment, the insulating layer 214C1 may be one of silicon oxide, silicon nitride, or a polymer; barrier layer 214C2 is used to prevent atomic diffusion of conductor 214C3 into insulating layer 214C1, underlying substrate 214D and underlying active region 214E. in one embodiment, barrier layer 214C2 may use one of Ta, Ti, Cr, TaN/Ta, TiN or TiW, among others. Conductor 214C3 functions to make the via conductive, and in one embodiment, conductor 214C3 may be one of Cu, W, or doped polysilicon. It should be noted that the bottom layer through hole 214C penetrates through the bottom layer test pad 214F, so as to achieve the electrical connection between the bottom layer chip 214 and the first chip 213 through the bottom layer through hole 214C, and therefore, the portion of the bottom layer through hole 214C bonded to the bottom layer test pad 214F cannot have an insulating layer.

The first re-wiring layer 220 is formed on the mounting surface 214A of the underlying chip 214, and includes: a first redistribution layer 221, a first dielectric layer 222 and a second dielectric layer 223, wherein the first dielectric layer 222 is formed on the mounting surface 214A, the first redistribution layer 221 is formed on the first dielectric layer 222, and the second dielectric layer 223 covers the first dielectric layer 222 and the first redistribution layer 221, in one embodiment, the first dielectric layer 222 and the second dielectric layer 223 may be organic polymer materials, such as polyimide; the first redistribution traces 221 are recessed through the first dielectric layer 222, the bottom passivation layer 214K and the bottom isolation layer 214J, and are electrically connected to the bottom contact pads 214F of the bottom chip 214. A plurality of first metal pads 290 are formed on the surface of the first redistribution layer 220, and the first metal pads 290 are electrically connected with the first redistribution layer 221; the first metal pad 290 is provided with a flip-chip terminal 230.

The second chip 212 has the same structure as the first chip 213 and the bottom chip 214, and will not be described herein. The first through hole 213C further penetrates through the inner passivation layer 213G of the first chip 213, the first test pad 213F, the first active region 213E, the first substrate 213D, and the second passivation layer 212K and the second isolation layer 212J of the second chip 212, and is electrically connected to the second support pad 212H, so as to electrically connect the first chip 213 and the second chip 212.

The top chip 211 includes: a top substrate 211D, a top active region 211E, a plurality of top test pads 211F, a top passivation layer 211G, and having a top active surface 211A and a back side 211B opposite the top active surface 211A; a top test pad 211F is formed on a surface 211EA of the top active region 211E, a top passivation layer 211G covers the surface 211EA of the top active region 211E and the plurality of top test pads 211F, and the surface of the top passivation layer 211G is provided as a top active surface 211A of the top die 211.

The stack back surface 212B of the second chip 212 and the top active surface 211A of the top chip 211 form plasma-activated surfaces by a plasma-activation technique and are directly joined in a gapless manner.

The second through hole 212C further penetrates through the inner passivation layer 212G of the second chip 212, the second test pad 212F, the second active region 212E, the second substrate 212D and the top passivation layer 211G of the top chip 211, and is electrically connected to the top test pad 211F, so as to electrically connect the second chip 212 and the top chip 211.

Each test pad may be formed of a metallic material, such as Al. The material of each bearing pad is the same as that of the conductor in each through hole. The dimension of each support pad, such as the first support pad 213H, in the width direction is 2 to 5 times the diameter of each through hole, such as the bottom layer through hole 214C; the dimension of each test pad, e.g., the first test pad 213F, in the longitudinal direction is 4 to 15 times the diameter of each through hole, e.g., the bottom layer through hole 214C.

Embodiment mode 2

In the chip stack three-dimensional package structure shown in fig. 2, the bottom chip 214 may be a different chip from the top chip 211, the second chip 212 and the first chip 213, as shown in fig. 4. In some embodiments, the top chip 211, the second chip 212 and the first chip 213 are Memory chips, such as DRAM (Dynamic Random Access Memory) chips, and the bottom chip 214 is a buffer chip. The buffer chip is manufactured by separating a circuit for controlling data transmission in the memory chip into independent control chips and adopting a manufacturing process different from that of the memory chip, and the response speed of the buffer chip is greatly higher than that of the memory chip so as to improve the data transmission speed.

It should be noted that, although the bottom chip 214 is different from the top chip 211, the second chip 212, and the first chip 213, the bottom chip 214 is identical to the second chip 212 and the first chip 213 in terms of chip structure.

Embodiments 3 and 4

The chip stack three-dimensional package structure shown in fig. 2 and 4 may also be formed by stacking only three layers of chips, and the specific structures are shown in fig. 5 and 6, respectively. The embodiment of fig. 5 is different from the embodiment of fig. 6 in that the bottom chip 214 in fig. 5 is the same chip as the top chip 211 and the first chip 213, and the bottom chip 314 in fig. 6 is a different chip from the top chip 211 and the first chip 213. for the description of the same components shown in fig. 2 and fig. 4 in fig. 5 and fig. 6, respectively, reference may be made to the description of fig. 2 and fig. 4, and no further description is given here.

Embodiments 5 and 6

In addition, the chip stack three-dimensional package structure shown in fig. 2 and 4 may also be formed by stacking only two layers of chips, and the specific structures are shown in fig. 7 and 9, respectively. The embodiment of fig. 7 differs from the embodiment of fig. 9 in that the bottom chip 214 in fig. 7 is the same chip as the top chip 211, whereas the bottom chip 314 in fig. 9 is a different chip than the top chip 211. Fig. 8 is a partial enlargement of the structure of the three-dimensional chip-stack package shown in fig. 7, and as shown in the drawing, the chip stack 210 includes a top chip 211 and a bottom chip 214, the bottom chip 214 has a mounting surface 214A and a stack back surface 214B opposite to the mounting surface 214A, the top chip 211 has a top active surface 211A and a back surface 211B opposite to the top active surface 211A, and the top active surface 211A and the stack back surface 214B of the bottom chip 214 are directly attached without a gap; the bottom chip 214 includes a plurality of bottom vias 214C and a plurality of bottom pads 214H formed at one end of the bottom vias 214C, the bottom vias 214C penetrate through the inner passivation layer 214G of the bottom chip 214, the bottom active layer 214E, the bottom substrate 214D and the top passivation layer 211G of the top chip 211 and are connected to the top test pads 211F of the top chip 211 to electrically connect the top chip 211 and the bottom chip 214. The first redistribution layer 220 is formed on the mounting surface 214A and electrically connected to the bottom layer contact pad 214H. The description of the same components in fig. 8 as those shown in fig. 3 can be referred to the description of fig. 3, and will not be repeated here.

Embodiments 7 and 8

The chip stack three-dimensional package structure shown in fig. 2 and 4 may further stack at least one chip on the stack back side 213B of the first chip 213 to form a more chip stack three-dimensional package structure. In some embodiments, a third chip 815 is added to the package structure shown in fig. 2 and 4, the third active surface 815A of the third chip 815 is directly bonded to the stack back surface 213B of the first chip 213 without a gap by a plasma activation technique, and the stack back surface 815B of the third chip 815 is directly bonded to the second active surface 212A of the second chip 212 without a gap, as shown in fig. 10 and 11. The description of the same components in fig. 10 and 11 as those shown in fig. 2 and 4, respectively, can be referred to the description of fig. 2 and 4, and will not be repeated here.

Embodiment 9

In another embodiment of the invention, the substrate may also be a silicon interposer, as shown in fig. 12. Unlike the embodiment shown in fig. 2, a plurality of through silicon via a41 is formed inside the through silicon via a40, and the through silicon via a41 and the flip chip terminals 230 are in one-to-one correspondence and electrically connected to each other. The chip stack 210 is flip-chip bonded to the chip bonding surface a42 of the silicon interposer a40 through the plurality of flip-chip terminals 230 on the first redistribution layer 220. A second redistribution layer a90 having a second redistribution layer a91 formed therein is formed on the terminal bonding surface a43 of the silicon interposer a 40; a plurality of second metal pads 270 are formed on the surface of the second rewiring layer a90, and a plurality of external terminals 280 are disposed on the second metal pads 270. The second redistribution line a91 is electrically connected to the through-silicon-interposer a41 and the second metal pad 270. It should also be noted that the connection method of the first redistribution line 221 and the second redistribution line a91 shown in fig. 12 is merely an illustration for explanation, and is not a specific connection method, and it is not to be understood that the connection method is limited to this connection method. The description of the same components in fig. 12 as those shown in fig. 2 can be referred to the description of fig. 2, and will not be repeated herein.

In addition, the substrate 240 in each of the embodiments of fig. 4 to 7 and fig. 9 to 11 may also be applied to a silicon interposer in some embodiments, and will not be described herein again.

Fig. 13 is a manufacturing process of the chip stack three-dimensional package structure shown in fig. 2 according to an embodiment of the invention. As shown, in step S201, a top chip wafer W11 and a second chip wafer W12 are provided, preparation of a top metal layer is completed on a top active area surface 211EA of the top chip wafer W11 and a second active area surface 212EA of the second chip wafer W12, respectively, and a plurality of top test pads 211F and a plurality of second test pads 212F are disposed in the top metal layer, respectively.

In step S202, electrical performance tests are performed on the chips on the top chip wafer W11 and the second chip wafer W12 using the top test pad 211F and the second test pad 212F, respectively.

In step S203, the statistical test result is calculated, and the chip yield of the top chip wafer W11 and the second chip wafer W12 is calculated, and if the yield is greater than or equal to a set reference value, the wafers may be used for stack packaging, otherwise, the wafers are excluded from use, and in some embodiments, the set reference value is 85%.

In step S204, a top passivation layer 211G is deposited on the top active area surface 211EA of the top chip wafer W11 to cover the top active area surface 211EA and the plurality of top test pads 211F; an inner passivation layer 212G is deposited on the second active area surface 212EA of the second chip wafer W12 to cover the second active area surface 212EA and the plurality of second test pads 212F.

In step S205, a surface 211A of the top passivation layer 211G of the top chip wafer W11 and a back surface 212B of the second chip wafer W12 are pretreated by a plasma activation technique to remove a surface oxide layer and activate the surface to form a free bond; the back surface 212B of the second chip wafer W12 is attached to the surface 211A of the top passivation layer 211G to form a covalent bond at room temperature and a predetermined pressure, followed by an annealing process at an annealing temperature, which in some embodiments is between 200 ℃ and 400 ℃, to stabilize the bonding between the wafers.

In step S206, a hole is punched from the surface 212A of the inner passivation layer 212G of the second chip wafer W12 and through the second test pad 212F, the semiconductor layers 212D, 212E of the second chip wafer W12 and the top passivation layer 211G to the top test pad 211F, respectively, to form a second through hole 212C; holes are punched from the surface 212A of the inner passivation layer 212G to form second receiving pad holes 212HA, the second receiving pad holes 212HA being coaxial with the second through holes 212C and located at an end of the second through holes 212C remote from the top test pad 211F.

In step S207, an insulating layer is deposited in the second receiving pad hole 212HA and the second through hole 212C, a photoresist (not shown) is filled into the second receiving pad hole 212HA and the second through hole 212C, and a portion of the photoresist is removed by dry etching, so that the remaining surface of the photoresist is located between the second testing pad 212F and the top testing pad 211F and HAs a certain distance with the second testing pad 212F, in some embodiments, the distance is 0 to 0.5 μm; the insulating layer not covered by the photoresist is removed by wet etching, and then the remaining photoresist is removed to expose the remaining insulating layer 212C 1.

In step S208, a barrier layer 212C2, a seed layer (not shown) and a conductor 212C3 are sequentially deposited to form a second through hole 212C and a second contact pad 212H, which can be electrically conductive, and in some embodiments, can be deposited by electroplating or the like.

In step S209, the conductor 212C3, the seed layer (not shown) and the barrier layer 212C2 deposited on the surface 212A of the inner passivation layer 212G of the second chip 212 are removed to expose the surface 212A of the inner passivation layer 212G, which may be removed by Chemical Mechanical Polishing (CMP) in some embodiments.

In step S210, a second isolation layer 212J is deposited on the surface 212A of the inner passivation layer 212G and covers the second contact pad 212H.

In step S211, a second passivation layer 212K is deposited to the second isolation layer 212J.

In step S212, a first chip wafer W13 is provided, and the processes in steps S201 to S205 are repeated to bond the first chip wafer W13 and the second chip wafer W12.

In step S213, the processes of steps S206 to S211 are repeated to form a first through hole 213C and a first contact pad 213H, and the first through hole 213C is electrically connected to the second contact pad 212H.

In step S214, the processes of steps S212 to S213 are repeated to bond the bottom chip wafer W14 and the first chip wafer W13, and a bottom via 214C and a bottom contact pad 214H are formed, wherein the bottom via 214C is electrically connected to the first contact pad 213H.

In step S215, a first redistribution layer 220 is formed on the mounting surface 214A of the bottom chip wafer W14, such that the first redistribution layer 221 of the first redistribution layer 220 is electrically connected to the bottom receiving pad 214H;

in step S216, a plurality of first metal pads 290 are formed on the surface of the first redistribution layer 220, and a plurality of flip-chip terminals 230 are disposed on the first metal pads 290.

In step S217, singulation (not shown) is performed to form a plurality of chip stack three-dimensional package structures.

It should be noted that, the description is made only by way of stacking four layers of chips, but is not limited to the number illustrated here, and other embodiments of the present invention may stack more layers of chips, or only stack two or three layers of chips.

The embodiments of the present invention have been described above with reference to specific embodiments. However, the present invention is not limited to these specific embodiments. That is, those skilled in the art can appropriately design and modify the embodiments so long as the features of the present invention are included in the scope of the present invention. For example, the elements, the arrangement, the materials, the conditions, the shapes, the sizes, and the like of the elements included in the above embodiments are not limited to those illustrated in the drawings, and may be appropriately modified. The elements of the above-described embodiments may be combined as technically allowable, and the combination of these elements is also intended to be included in the scope of the present invention as long as the features of the present invention are included.

Claims

1. A chip stack three-dimensional packaging structure is characterized by comprising:

the chip stack body comprises a first chip and a bottom chip, wherein the bottom chip is provided with an installation surface and a stack back surface opposite to the installation surface, and a first active surface of the first chip is directly attached to the stack back surface of the bottom chip in a gapless mode; the bottom chip is internally provided with a plurality of bottom perforations and a plurality of bottom bearing pads formed at one end of the bottom perforations, the bottom perforations penetrate through a first passivation layer and a first isolation layer of the first chip and are arranged on a first bearing pad of the first chip, the bottom perforations further penetrate through a semiconductor layer of the bottom chip and are communicated with a bottom test pad of the bottom chip so as to electrically connect the first chip and the bottom chip, and the bottom test pad is used for carrying out electrical performance test on the bottom chip; the first isolation layer covers the first bearing pad of the first chip, and the first passivation layer is positioned between the bottom substrate of the bottom chip and the first isolation layer; wherein the content of the first and second substances,

the bottom layer through hole comprises a first part and a second part, the first part of the bottom layer through hole sequentially comprises an insulating layer, a barrier layer, a seed layer and a conductor from the hole wall to the hole central axis, and the second part of the bottom layer through hole sequentially comprises the barrier layer, the seed layer and the conductor from the hole wall to the hole central axis; the first part of the bottom layer through hole and the second part of the bottom layer through hole are located between the first test pad of the first chip and the bottom layer test pad and close to the bottom layer test pad, so that the bottom layer through hole is electrically connected with the bottom layer test pad.

2. The chip stack three-dimensional package structure of claim 1,

the chip stack three-dimensional packaging structure further comprises:

and the flip chip terminals are arranged on the first rewiring layer.

3. The chip stack three-dimensional package structure of claim 1, wherein the first active surface of the first chip and the stack back surface of the bottom chip are plasma-activated surfaces.

4. The chip stack three-dimensional package structure of claim 1, wherein:

the first chip is provided with a first active surface and a stack back surface opposite to the first active surface, the first chip is provided with a first active area, the surface of the first active area forms the first test pad, the first chip is also internally provided with a plurality of first through holes and a plurality of first support pads formed at one end of the first through holes, and the first chip comprises a first passivation layer used for providing the first active surface;

5. The stacked chip three-dimensional package structure according to claim 4, wherein the bottom layer through hole is integrally formed as the bottom layer receiving pad at one end of the mounting surface; and a bottom isolation layer is formed between the bottom bearing pad and the bottom passivation layer.

6. The three-dimensional chip stack package structure according to claim 4, wherein at least one additional chip is stacked on the stack back surface of the first chip, each additional chip having the same structure as the first chip, the additional chip having a second active surface and a stack back surface opposite to the second active surface, the second active surface of the additional chip being directly attached to the stack back surface of the first chip without a gap, the additional chip having a plurality of second test pads formed on a surface of a second active region thereof, the additional chip including a second passivation layer for providing the second active surface; the additional chip further comprises a plurality of second through holes and a plurality of second bearing pads formed at one end of the second through holes, and the first through holes penetrate through the second passivation layer of the additional chip and are communicated with the second bearing pads so as to electrically connect the first chip and the additional chip.

7. The chip stack three-dimensional package structure according to claim 6, wherein the first chip and the additional chip are both memory chips, and the bottom chip is selected from one of a buffer chip and a memory chip.

8. The stacked chip three-dimensional package structure of claim 4, wherein a boundary point between the first portion of the bottom layer through hole and the second portion of the bottom layer through hole is 0-5 μm away from the bottom layer test pad.

9. The stacked chip three-dimensional package structure of claim 4, wherein the dimension of the first pad in the width direction is 2-5 times the diameter of the bottom layer through hole, and the dimension of the first test pad in the length direction is 4-15 times the diameter of the bottom layer through hole.

10. The three-dimensional chip-on-chip package structure according to claim 2, further comprising a substrate having a chip bonding surface and a terminal bonding surface, wherein the chip-on-chip package is flip-chip bonded to the chip bonding surface of the substrate via the flip-chip terminal.

11. The chip stack three-dimensional package structure according to claim 10, wherein the substrate is a silicon interposer including a plurality of through silicon interposer vias; the terminal bonding surface is formed with a second rewiring layer, the second rewiring layer is formed with an external terminal, and the external terminal is electrically connected to the flip chip terminal through the second rewiring layer and the through-silicon-interposer via.

12. A manufacturing method of a chip stack three-dimensional packaging structure is characterized by comprising the following steps:

providing a first chip wafer and a bottom chip wafer, wherein the first chip wafer is provided with a first active surface, and the bottom chip wafer is provided with a mounting surface and a stack back surface opposite to the mounting surface;

forming a plurality of bottom layer through holes and a bottom layer bearing pad in the bottom layer chip wafer, wherein the bottom layer bearing pad is formed at one end of the bottom layer through holes, the bottom layer through holes penetrate through a first passivation layer and a first isolation layer of the first chip wafer and are arranged on the first bearing pad of the first chip wafer, the bottom layer through holes further penetrate through a semiconductor layer of the bottom layer chip wafer and are communicated with a bottom layer test pad of the bottom layer chip wafer, and the bottom layer test pad is used for carrying out electrical performance test on the bottom layer chip wafer; the first isolation layer covers a first bearing pad of the first chip wafer, and the first passivation layer is located between a bottom lining substrate of the bottom chip and the first isolation layer; the bottom layer through hole comprises a first part and a second part, the first part of the bottom layer through hole sequentially comprises an insulating layer, a barrier layer, a seed layer and a conductor from the hole wall to the hole central axis, and the second part of the bottom layer through hole sequentially comprises the barrier layer, the seed layer and the conductor from the hole wall to the hole central axis; the first part of the bottom layer through hole and the second part of the bottom layer through hole are located between the first test pad of the first chip and the bottom layer test pad and close to the bottom layer test pad, so that the bottom layer through hole is electrically connected with the bottom layer test pad.

13. The method of manufacturing the chip stack three-dimensional package structure according to claim 12,

forming a first redistribution layer on the mounting surface of the bottom chip wafer, the first redistribution layer being electrically connected to the bottom support pad;

arranging a plurality of flip chip terminals on the first redistribution layer;

14. The method of claim 12, wherein the first chip wafer and the bottom chip wafer are wafers that have been tested and have a chip yield greater than or equal to a yield reference value.

15. The method of claim 12, wherein the back surface of the bottom die wafer and the first active surface of the first die wafer are formed into plasma-activated surfaces by a plasma-activation technique and directly bonded without a gap.