CN109801207B - CPU-FPGA collaborative image feature high-speed detection and matching system - Google Patents
CPU-FPGA collaborative image feature high-speed detection and matching system Download PDFInfo
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Abstract
The invention provides a CPU-FPGA collaborative image feature high-speed detection and matching system, which comprises a first processor, a second processor, a third processor and a fourth processor, wherein the first processor is used for overall scheduling, image data transmission, image feature vector description and matching result storage and output; the second processor is used for detecting the image characteristic points and calculating the characteristic vector matching; the first processor transmits the image pixel data to the second processor; the second processor processes the coordinates of the image feature points and returns the coordinates to the first processor; the first processor generates and stores a feature vector; the first processor transmits the image feature vector data to the second processor, and the second processor transmits the best and suboptimal matching distance values of the feature vectors to be matched obtained by matching calculation and the feature vector numbers back to the first processor in real time; the first processor judges and outputs the matching point pair coordinates according to the optimal and suboptimal matching distance ratio. The invention is composed of the first processor and the second processor, and the number of the second processors is expanded according to the requirement, so that the image feature detection and matching calculation efficiency is improved.
Description
Technical Field
The invention relates to the field of geospatial information, in particular to a CPU-FPGA (Central processing Unit-field programmable gate array) collaborative image feature high-speed detection and matching system.
Background
Image matching is a basic function of digital photogrammetry 4D product generation, urban three-dimensional modeling, remote sensing image target detection, tracking and other visual applications. The continuous lift-off and operation of the novel high-resolution satellite remote sensing platform, the rapid development and maturation of various unmanned aerial vehicles and image sensor technologies enable the geometric level of the aerial (daily) image data volume to be increased. So far, affine invariant features (like) represented by SIFT and SURF can obtain a stable and reliable matching result, but the computational complexity and the time cost are high, and the conventional matching processing mode is difficult to meet the requirement of timely processing of massive remote sensing image data. Because the development speed of the multi-core processor is limited by the semiconductor technology, the effective strategy for improving the image matching efficiency is to construct a parallel computing system under the cooperation of heterogeneous processors, and the parallel computing system mainly comprises two modes of a CPU+GPU and a CPU+FPGA. Although the GPU adopts a SIMD (single instruction stream multiple data stream) mode to greatly improve the data parallel processing capability, the depth of a pipeline is limited, and each computing unit needs to do the same thing according to a uniform pace when processing different data packets, so that the input and output delay is increased, and the "bruise" with high delay (millisecond level) exists. Compared with a GPU, the second processor FPGA which defines the hardware function of the device through software programming has higher calculation efficiency, lower power consumption and cost, can realize data parallelism, pipeline parallelism and extremely low delay (microsecond level) at the same time, can effectively meet the real-time processing requirement of images, but is limited by the storage space on the FPGA chip, the number of logic arrays and the characteristics of being different from the Von Neumann structure order operation, realizing the upper bias addition and multiplication operation, and has difficult and extremely challenging FPGA function development.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a high-speed detection and matching system for image features in cooperation with a CPU-FPGA, so as to solve the problem of low computing efficiency in the prior art.
To achieve the above and other related objects, the present invention provides a CPU-FPGA collaborative image feature high-speed detection and matching system, which includes a first processor and at least one second processor;
the first processor is used for overall scheduling, image data transmission, image feature vector description and matching result storage and output;
the second processor is used for detecting image characteristic points and calculating characteristic vector matching;
the first processor transmits the image pixel data to the second processor according to a set sequence; the second processor processes the image feature points in real time and returns the image feature points to the first processor; the first processor synchronously generates and stores the image feature vectors until the image feature vectors are all generated; the first processor transmits the image feature vector data to the second processor, and the second processor transmits the best match, the suboptimal match distance value and the best match number of the feature vector to be matched, which are obtained through real-time matching calculation, back to the first processor in real time.
Optionally, the detection system further includes a data buffer, and the second processor is connected to the data buffer, and the second processor includes a feature detection IP core;
the data buffer area is used for buffering the image pixel stream transmitted by the first processor;
the feature detection IP core is used for processing the image pixel stream to obtain feature points; the feature detection IP core communicates the location of the feature point back to the first processor,
and the first processor generates a feature vector according to the feature point position pixel neighborhood information to finish feature binary coding.
Optionally, the system further comprises a memory area, said second processor further comprises a vector matching IP core,
the second processor is further used for receiving a certain feature vector of the image to be matched, which is transmitted by the first processor, in real time;
the vector matching IP core is used for completing the Hamming distance between the characteristic vector of the current image to be matched and all the reference image characteristic vectors in the data buffer area, and calculating the Hamming distance through a plurality of bit exclusive OR units and a bit accumulator;
the vector matching IP core is further used for importing a next batch of reference image feature vectors from the storage area and repeating matching calculation after the matching of the reference image feature vectors of the current batch and the feature vectors of the feature images to be matched is completed, until all the reference image feature vectors in the storage area and the feature vectors of the images to be matched are completed, recording the best matching, suboptimal matching distance value and best matching number of the current feature vectors to be matched and transmitting back to the first processor in real time;
the first processor is also used for judging whether the matching point is a matching point meeting the condition according to the ratio of the best matching distance to the suboptimal matching distance, and recording and outputting the matching point to the coordinate.
Optionally, the first processor is a central processor, and the second processor is a field programmable gate array.
As described above, the CPU-FPGA collaborative image feature high-speed detection and matching system has the following beneficial effects:
the invention is composed of CPU and FPGA processing board, the two are connected by PCI interface, USB3.0 interface and gigabit network interface, the number of FPGA boards can be expanded according to the interface setting and calculation energy demand, the image detection and matching calculation efficiency can be improved in multiple, the invention is applicable to desktop computers and portable notebook computers, and has the characteristic of flexible expansion; if the number of the limiting image detection angle points is not more than one thousandth of the total number of pixels, the FPGA can process up to 60 hundred million pixel scale images when being externally connected with a 3Gb storage area memory chip, and the matching of 2048 and 2048 characteristic points can be completed within 0.33ms without size limitation, so that the computing efficiency is extremely high, the cost is low, and the power consumption is low. The invention has good practical value for high-efficiency processing of large-scale and massive remote sensing images.
Drawings
For further explanation of the description of the present invention, the following describes the embodiments of the present invention in further detail with reference to the accompanying drawings. It is to be understood that these drawings are solely for purposes of illustration and are not intended as a definition of the limits of the invention.
FIG. 1 is a system block diagram in an embodiment of the invention;
FIG. 2 is a block diagram of FPGA processing board hardware in an embodiment of the invention;
FIG. 3 is a flow chart of FPGA matching in an embodiment of the invention;
fig. 4 is a diagram of FPGA vector matching IP verification in an embodiment of the invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
The invention provides an image characteristic high-speed detection and matching system based on CPU-FPGA cooperation, which comprises a first processor and at least one second processor;
the first processor is used for overall scheduling, image data transmission, image feature vector description and matching result storage and output;
the second processor is used for detecting image characteristic points and calculating characteristic vector matching;
the first processor transmits the image pixel data to the second processor according to a set sequence; the second processor processes the image feature point coordinates in real time and returns the image feature point coordinates to the first processor; the first processor synchronously generates and stores the feature vectors until the feature vectors of the images are all generated; the first processor transmits the image feature vector data to the second processor, and the second processor returns the coordinates of the same-name feature pairs obtained by real-time matching calculation to the first processor for output.
Specifically, in the present embodiment, a CPU (central processing unit ) is used as the first processor, and an FPGA (Field-Programmable Gate Array, i.e., field programmable gate array) is used as the second processor.
The implementation process of image feature detection and matching of the system comprises three stages of feature detection, feature vector (descriptor) generation and feature vector matching. The feature detection stage aims at acquiring local feature points on the image, and is completed by an FPGA board feature detection IP core in the system; the feature vector (descriptor) generation stage aims at carrying out neighborhood information binary coding on feature points detected in an FPGA (field programmable gate array) board, and is completed by a CPU (central processing unit) in the system; the feature vector matching stage aims to obtain homonymous (similar) feature pairs from all feature vector sets through Hamming distance calculation, and is completed by an FPGA board vector matching IP core in the system. Of the above three phases, the feature detection and feature vector (descriptor) generation phases overlap in time series.
As shown in fig. 1, the present embodiment provides a set of remote sensing CPU-FPGA collaborative image feature high-speed detection and matching system with high computation efficiency, low power consumption and cost, wherein the hardware frame of the system is formed by connecting multiple FPGA processing boards with a Computer (CPU), and the connection can adopt three modes of PCI, USB3.0 or gigabit network communication interfaces: when the PCI communication interface is selected, the number of the FPGA processing boards can be flexibly expanded according to the number of PCI slots on the computer main board; when the USB3.0 communication interface is selected, the number of the FPGA processing boards is flexibly expanded according to the number of the USB3.0 interfaces on the computer main board; flexibly expanding the number of FPGA processing boards according to the network capacity when the gigabit network port communication interface is selected; the number of FPGA processing boards can be expanded by mixing PCI, USB and gigabit network communication interfaces.
In this embodiment, a general CPU in a PC computer is responsible for task overall scheduling, image data transmission, image feature vector description, and matching result storage and output; the FPGA processing boards mainly complete image feature point detection and feature vector matching calculation, wherein the hardware configuration of each FPGA processing board is identical, the PC computer distributes addresses according to the number of the FPGA processing boards and performs coordinated control, and the processing speed of the FPGA processing boards can be doubled by expanding the number of the FPGA processing boards. The system scheduling method comprises the following steps: the CPU sequentially transmits the image pixel data to the FPGA processing board; the FPGA processing board processes the image feature point coordinates in real time to obtain image feature point coordinates and returns the image feature point coordinates to the CPU; the CPU synchronously generates and stores the image feature vectors until the image feature vectors are completely generated; the CPU transmits the feature vector data to the FPGA processing board, and the FPGA processing board returns the homonymous feature point coordinates obtained by real-time matching calculation to the CPU for storage and output.
As shown in fig. 2, the FPGA processing board hardware built in this embodiment includes: FPGA, 8 pieces of 512Mbit memory area chips, 4 pieces of 8Mbit SRAM chips, gigabit network interfaces, USB3.0 interfaces and PCIE X4 interfaces. The FPGA can adopt a cyclone V series chip of Altera company; an SRAM memory with 64-bit width is formed by expanding 4 16-bit SRAM chips; a total 4G bit memory with 128 bit width is formed by expanding 8 16-bit 512M bit memory chips; the designed external interfaces comprise a gigabit network interface, a USB3.0 interface and a PCIE X4 interface, and can be connected with a computer through the gigabit network interface, the USB3.0 interface or the PCI interface; the processing board forms a 128-bit data width data bus through an 8-bit memory area chip, and adopts a 400M frequency dual-channel memory scheme to transmit data.
In one embodiment, the detection system further includes a data buffer (hereinafter referred to as SRAM data buffer), and the second processor is connected to the data buffer, and the second processor includes a feature detection IP core;
the data buffer area is used for buffering the image pixel stream transmitted by the first processor;
the feature detection IP core is used for processing the image pixel stream to obtain feature points; the feature detection IP core communicates the location (X, Y coordinates) of the feature point back to the first processor,
and the first processor generates a feature vector according to the feature point position pixel neighborhood information to finish feature binary coding.
In one embodiment, the system further includes a memory region (described below as DDR 3), the second processor further includes a vector matching IP core,
the second processor is further used for receiving a certain feature vector of the image to be matched, which is transmitted by the first processor, in real time;
the vector matching IP core is used for completing the matching of the characteristic vector of the current image to be matched and the characteristic vector of all the reference images in the data buffer area, and the Hamming distance calculation is realized through a plurality of bit exclusive OR units and bit accumulators;
the vector matching IP core is further used for importing a next batch of reference image feature vectors from the storage area and repeating matching calculation after the matching of the reference image feature vectors of the current batch and the feature vectors of the feature images to be matched is completed, until all the reference image feature vectors in the storage area and the feature vectors of the images to be matched are completed, recording the best matching, suboptimal matching distance value and best matching number of the current feature vectors to be matched and transmitting back to the first processor in real time;
the first processor is further configured to determine whether a matching point that meets a condition (less than a set threshold) is a matching point according to the ratio of the best matching distance to the suboptimal matching distance, and record and output a coordinate pair of the matching point.
The FPGA characteristic detection process comprises the following steps: firstly, caching an image pixel stream transmitted by a CPU through a PCI, USB3.0 or gigabit network communication interface, processing the cached pixel by using a characteristic detection IP core designed in an FPGA board to obtain a characteristic point, and transmitting the position (X, Y coordinates) of the characteristic point back to a computer terminal by using the communication interface, so that a characteristic vector of a 64-bit binary number is generated on the computer, and the characteristic binary coding is completed.
As shown in fig. 3, the FPGA matching flow in this embodiment is: and a batch import mode from the storage area DDR3 to the SRAM is adopted, and a characteristic vector is matched with a batch of characteristic vectors in parallel. Storing all feature vectors of the reference image transmitted by the CPU in a storage area DDR3, and introducing the feature vectors from the storage area DDR3 into an SRAM data buffer area in batches by taking N feature vectors as units; receiving a certain feature vector to be matched of the image to be matched transmitted by the CPU in real time, and completing the matching of the current feature vector to be matched with all (particularly 2048) reference image feature vectors in the SRAM data buffer area in a feature vector matching IP core; feature matching of N/16 points is completed in parallel in one clock cycle. After the matching of the current batch of reference image feature vectors and the feature vectors to be matched is completed, importing the next batch of reference image feature vectors from the storage area DDR3, and repeatedly performing matching calculation until all the reference image feature vectors in the storage area DDR3 are matched with the feature vectors to be matched, recording the optimal (minimum) matching, sub-optimal matching distance and optimal matching number of the current feature vectors to be matched, and transmitting back to the CPU of the computer in real time; the transmission of communication data adopts 64-bit data width, and one data transmission is completed in two time periods, so that 16 clock periods are required for the transmission of each feature vector.
As shown in fig. 4, the FPGA vector matching IP block verification chart in the present embodiment. While the reference image feature vector is written into the storage area DDR3, the first 2048 feature vectors are written into the RAM data block, the rest feature vectors are batched and led into the cache data block from the storage area DDR3 by taking 2048 feature vectors as units, after the matching of the current feature vector to be matched with all the reference image feature vectors in the data block is completed, the next batch of reference image feature vectors are led into again to carry out matching calculation repeatedly, and feature matching of 128 points is completed in a single clock cycle. The data cache blocks designed in this embodiment are 16-bit deep, 4096-bit wide cache blocks, a total of 16 such data cache blocks, consuming 1Mbit in total; 128 512-bit exclusive or units are designed, and then Hamming distance calculation is realized through bit accumulation; the feature vector in the storage area DDR3 is read in a data block mode, the size of each read block is 65536 bits, an 8-bit storage area chip forms a 128-bit data width data bus, and if the 400M frequency dual-channel memory scheme FPGA is adopted, the data transmitted in one clock cycle are as follows: 4 x 2 x 128 = 2048 bits, then 32 clock cycles complete the transmission of 65536 bits; when the number of feature points in the matched image is not more than 2048, matching with 128 feature vectors is completed in each clock cycle, and under the condition that the main frequency is 100MHz, the matching time for completing 2048 and 2048 feature points is only 0.33ms; when the number of feature points in the matched image exceeds 2048, the feature points are imported in batches.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (4)
- The CPU-FPGA collaborative image feature high-speed detection and matching system is characterized by comprising a first processor and at least one second processor;the first processor is used for overall scheduling, image data transmission, image feature vector description and matching result storage and output;the second processor is used for detecting image characteristic points and calculating characteristic vector matching;the first processor transmits the image pixel data to the second processor according to a set sequence; the second processor processes the image feature points in real time and returns the image feature points to the first processor; the first processor synchronously generates and stores the image feature vectors until the image feature vectors are all generated; the first processor transmits the image feature vector data to the second processor, and the second processor transmits the best matching, the suboptimal matching distance value and the best matching number of the feature vector to be matched obtained by real-time matching calculation back to the first processor in real time;the process comprises three stages of feature detection, feature vector generation and feature vector matching; the feature detection stage aims at acquiring local feature points on the image, and is completed by an FPGA board feature detection IP core in the system; the feature vector generation stage aims at carrying out neighborhood information binary coding on the feature points detected in the FPGA board, and the neighborhood information binary coding is completed by a CPU in the system; the feature vector matching stage aims to obtain homonymous feature pairs from all feature vector sets through Hamming distance calculation, and the feature vector matching stage is completed by an FPGA board vector matching IP core in the system.
- 2. The system for detecting and matching the image features at high speed in cooperation with a CPU-FPGA as claimed in claim 1, wherein the detection system further comprises a data buffer, the second processor is connected with the data buffer, and the second processor comprises a feature detection IP core;the data buffer area is used for buffering the image pixel stream transmitted by the first processor;the feature detection IP core is used for processing the image pixel stream to obtain feature points; the feature detection IP core communicates the location of the feature point back to the first processor,and the first processor generates a feature vector according to the feature point position pixel neighborhood information to finish feature binary coding.
- 3. The system for high-speed detection and matching of image features in cooperation with a CPU-FPGA of claim 1, further comprising a memory area, said second processor further comprising a vector matching IP core,the second processor is further used for receiving a certain feature vector of the image to be matched, which is transmitted by the first processor, in real time;the vector matching IP core is used for completing the Hamming distance between the characteristic vector of the current image to be matched and all the reference image characteristic vectors in the data buffer area, and calculating the Hamming distance through a plurality of bit exclusive OR units and a bit accumulator;the vector matching IP core is further used for importing a next batch of reference image feature vectors from the storage area and repeating matching calculation after the matching of the reference image feature vectors of the current batch and the feature vectors of the feature images to be matched is completed, until all the reference image feature vectors in the storage area and the feature vectors of the images to be matched are completed, recording the best matching, suboptimal matching distance value and best matching number of the current feature vectors to be matched and transmitting back to the first processor in real time;the first processor is also used for judging whether the matching point is a matching point meeting the condition according to the ratio of the best matching distance to the suboptimal matching distance, and recording and outputting the matching point to the coordinate.
- 4. The system for high-speed detection and matching of image features in cooperation with a CPU-FPGA of claim 1, wherein said first processor is a central processing unit and said second processor is a field programmable gate array.
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